JPH11305868A - Digital signal processor and computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a computer system for transmitting data with high reliability by connecting a main body through an interface such as an AC link with an expanded device. SOLUTION: When a main body 100 is mechanically connected with a docking station 200, a lock switch 60 generates a docking signal DOCK for indicating the connecting state. A timing generating part 16 starts the counting of a synchronizing clock CLKs based on the docking signal DOCK, and generates a control signal CTL for indicating the establishment of synchronization when the counting reaches a prescribed number. A clock switching circuit 17 switches the synchronizing CLKs and an asynchronizing clock CLKa based on the control signal CTL, and outputs it. A mixing part 13 or an AC' 97 interface 14 operates based on the clock outputted from the clock switching circuit 17. Then, synthetic musical sound data SDmix generated by the mixing part 13 are transferred to a codex LSI 2 as output data SDout, and converted into an analog signal, and supplied to an outside speaker 300 as an output musical sound signal Sout.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing apparatus and a computer system suitable for performing data transmission with high reliability when data is transmitted through an interface such as an AC link.

[0002]

2. Description of the Related Art In recent years, many personal computers are equipped with a sound board for reproducing music compact discs and reproducing background sounds of game software.
The pronunciation data of the game software is given, for example, in a MIDI format. The sound data indicates sound parameters such as timbre, pitch and volume.
The sound data is converted into tone data by a tone generator LSI, and is converted into a tone signal via a DAC (Digital / Analog Converter).

[0003] As a standard specification of an LSI having such a sound function, AC (Audio Codec) '9 is used.
7 are known. In this specification, the number of input / output channels for analog signals, the sampling frequency, the S / N ratio (signal-to-noise ratio), the pin arrangement, and the like are specified, and the configuration includes an AC link described later.

FIG. 4 shows the configuration of a system conforming to AC'97. In this system, the digital controller 1 is connected to a PCI bus,
Sound processing such as pitch conversion is performed based on sound data supplied via the I bus. Also,
The codec LSI2 includes DAC and ADC (Analog / Digi
tal Converter) and sampling frequency (48KHz)
An oscillation circuit that oscillates a bit clock having a frequency 256 times as large as that of FIG. The digital controller 1 and the codec LSI 2 are connected by a 5-wire interface. This interface is an AC link
This is called LINK, whereby the bit clock CLKb is sent from the codec LSI 2 to the digital controller 1 and the input data SDin is transferred. On the other hand, when outputting tone data, the digital controller 1 outputs the output data SDout in synchronization with the bit clock CLKb.
To the codec LSI 2 and the synchronization signal SY
NC is generated.

Since the digital controller 1 performs various operations, it is often operated based on a clock faster than the bit clock CLKb. For this reason, a PLL may be provided therein to generate, for example, an internal clock having a frequency twice as high as that of the bit clock CLKb, and the arithmetic processing may be performed using the internal clock.

[0006]

By the way, in a notebook personal computer which is convenient to carry, miniaturization and weight reduction are important issues. For this reason, the main body of the computer is configured to support only the basic functions, and only the main body is used on the go. When the computer is used at a desk, a laptop personal computer is connected to an expansion device called a docking station. The ones to use are known. Normally, the docking station has an expansion slot, a drive bay, and ports (a mouse port, a keyboard port, a tone signal input / output terminal, and the like) that a desktop personal computer has as standard.

The AC'97 described above has not been applied to a docking station. However, if the AC'97 is applied, if the codec LSI 2 is provided on the docking station side, the digital controller 1 is provided on the personal computer main body side, and both are provided. An aspect in which connection is made by an AC link is conceivable. In this case, codec L
Since it is not necessary to incorporate the SI2 into the main body, the size and weight of the main body can be reduced.

[0008] In the PLL, a stable clock signal cannot be generated unless a certain time (lock-in time) has elapsed since the reference signal was input. Therefore, if data transmission is performed immediately after the docking station and the main unit are connected via the AC link, synchronization between the digital controller 1 and the codec LSI 2 will not be achieved, and erroneous data will be received.

The present invention has been made in view of the above-described circumstances, and when data transmission is performed by connecting a main unit and an expansion device via an interface such as an AC link, data transmission is performed with high reliability. It is an object to provide a computer system that can perform the operation.

[0010]

According to the first aspect of the present invention, there is provided an analog signal processing apparatus which performs analog processing by separating or combining with an analog signal processing apparatus.
In a separated state, digital processing is performed based on an internal clock, and in a coupled state, a digital signal processing apparatus that performs digital processing in synchronization with a reference clock supplied from the analog signal processing apparatus. Detecting means for detecting the coupling; synchronizing means for generating a synchronous clock synchronized with the reference clock; detecting that the mechanical means is mechanically coupled to the analog signal processing device by the detecting means; and After the synchronization by the synchronization means is established, a control means for controlling the digital processing based on the synchronization clock is provided.

Further, in the invention according to claim 2, the control means starts measurement based on a detection result of the detection means, and at least the synchronous clock generated by the clock generation means is stabilized. And a clock switching means for switching a clock used for the digital processing from the internal clock to the synchronous clock based on the measurement result of the time measuring means. According to a third aspect of the present invention, the time measuring means measures the time by counting the synchronous clock or the reference clock.

According to a fourth aspect of the present invention, there is provided a notebook computer and a docking station, wherein the notebook computer performs digital processing based on an internal clock in a separated state and the docking station in a coupled state. In a computer system that performs digital processing in synchronization with a reference clock supplied from a station, the docking station includes: an oscillation circuit that generates and outputs the reference clock; and a digital circuit that converts a digital signal into an analog signal using the reference clock. /
An analog converter, wherein the notebook computer has detection means for detecting that it is mechanically coupled to the docking station, and synchronization means for generating a synchronization clock synchronized with the reference clock supplied from the docking station. Means, a time measuring means for measuring a predetermined time by starting counting of the synchronous clock or the reference clock based on a detection result of the detecting means, and a fixed time measured by the time measuring means. After that, a clock switching unit that switches a clock used for digital processing from the internal clock to the synchronous clock, a digital processing unit that performs digital processing based on a clock output from the clock switching unit, and the time measurement unit After a certain time is measured, the digital processing Computer system characterized in that a transfer means for transferring the output data processed in unit to the docking station.

[0013] In the invention according to claim 5, the docking station includes storage means for storing identification data for identifying an optional function, and the digital processing means is fixed by the time measuring means. After the time is measured, the identification data is read from the storage unit, and digital processing is performed based on the identification data. Also, in the invention according to claim 6, the detecting means detects that the notebook computer and the docking station are mechanically coupled and that the two cannot be separated without an unlocking operation. Features.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Configuration of Embodiment Hereinafter, a configuration of a computer system according to an embodiment of the present invention will be described with reference to the drawings. 1-1: Mechanical Configuration First, the mechanical configuration of the computer system A will be described. FIG. 1 is a perspective view of a state in which a notebook personal computer and a docking station are connected, as viewed from the rear side. As shown in FIG.
Is a notebook personal computer 100 (hereinafter, referred to as a notebook personal computer 100).
The main body 100 is abbreviated to a docking station 200, and the main body 100 is slid along a groove (not shown) provided in the docking station 200 to connect the two to each other. (Not shown) can maintain the mechanical coupling state. In this case, the two cannot be separated unless a lock release operation is performed by the lock mechanism. When in the coupled state, various interfaces represented by an AC link are connected via a physical connector, so that data can be transmitted between the two.

Further, the main body 100 is provided with a lock switch as a part of the lock mechanism. This allows
It is possible to detect that the two are in the coupled state, and the lock switch outputs a docking signal DOCK indicating whether the two are in the coupled state or in the separated state. The main body 100 is provided with a main body speaker as a sounding means in addition to a keyboard and a liquid crystal display, and a digital controller 1 is provided therein. Further, in the separated state, the musical sound is emitted from the main body speaker 18.

On the other hand, the docking station 200 has a built-in codec LSI 2, and a card slot 210 is provided on a side surface thereof. On the back side, a mouse connection terminal 220 and an extended keyboard connection terminal 2 are provided.
30, video output terminal 240, audio output terminal 25
0, audio input terminal 260, microphone input terminal 27
0, an external input terminal 280, and an extension interface terminal 290.

1-2: Electrical Configuration Next, the electrical configuration of the computer system A will be described. FIG. 2 is a block diagram illustrating an electrical configuration of the computer system according to the present embodiment. First, the main body 10
0 will be described. The CPU 20 is connected to each component via a bus 70, and the computer system A
Take control of the whole. The RAM 30 is a readable and writable memory corresponding to a main storage device, and functions as a work area of the CPU 20. The ROM 40 is a read-only memory and stores a boot program and the like. The hard disk 50 corresponds to a secondary storage device, and stores a large amount of programs and data. The programs and data are loaded into the RAM 30 as needed. Further, as described above, the lock switch 60 is a part of the lock mechanism, and generates the docking signal DOCK that indicates whether the lock state is the coupled state or the separated state. As the bus 70, for example, a PCI bus capable of burst transfer of data is suitable.

Next, the digital controller 1 is composed of the following parts. First, the bus interface 11 is an interface for transmitting data to and from the bus 70,
A bus master function is provided so that data can be directly exchanged with the AM 30. Next, when the sound source data is supplied, the sound source unit 12 is configured to reproduce the tone data based on sound parameters such as a pitch and a tone specified by the sound data. Next, the mixing unit 13
Is configured to synthesize the musical tone data supplied from the sound source unit 12 and the musical tone data transferred from the hard disk 50 and output the synthesized musical tone data SDmix. Further, the mixing unit 13 outputs the synthesized musical sound data SD before the synchronization is detected by the control signal CTL described later.
The same data as mix SDmix 'is output to a DAC (not shown),
On the other hand, after the synchronization is established, the data SDmix ′ is not output. Thereby, the internal speaker 18
Emits sound based on the tone signal only in the separated state.

Next, the AC'97 interface 14
Is docking station 2 via AC link LINK
00 and the codec LSI2 provided on the
Data transmission is performed according to a predetermined communication rule called a link protocol. From the digital controller 1 to the codec LSI 2, the synthetic musical sound data SDmi
x is output as output data SDout, and a synchronization signal SYNC instructing the start thereof in synchronization with the output data SDout
And reset signal RS for initializing codec LSI2
Is output. When a higher-level application such as game software instructs the mixing unit 13 to change the gain, this information is multiplexed on the output data SDout and transmitted.

The input data SDin and the bit clock CL are transmitted from the codec LSI 2 to the digital controller 1.
Kb is output. As the input data SDin, for example, an audio signal input from the microphone input terminal 270 is input to an ADC provided inside the codec LSI2.
The audio data converted in the above corresponds. The bit clock CLKb has a frequency of 12.288 MHz (= 256 * 48 KHz), and the codec LSI 2 and the digital controller 1 operate in synchronization with the frequency.

Next, the PLL 15 is a well-known phase locked loop circuit, and is configured to generate a synchronous clock CLKs based on the bit clock CLKb. The frequency of the synchronous clock CLKs is 24.576 MHz, which is set to be twice the frequency of the bit clock CLKb.

The timing generator 16 is constituted by a counter or the like. When the state indicated by the docking signal DOCK changes from the separated state to the combined state, the timing generator 16 counts a predetermined number of synchronous clocks CLKs and outputs the codec LSI
2 to generate a control signal CTL indicating that synchronization has been established. In this case, the synchronous lock CL
The predetermined number for measuring Ks is a stable synchronous clock after at least the bit clock CLKb is input to the PLL 15.
It is set to correspond to the time until CLKs is obtained.
The control signal CTL is supplied to each part of the digital controller 1. Therefore, the mixing unit 13 and the AC'97 interface 14
CTL, docking station 2 and main unit 100
00 are mechanically coupled, and it can be detected that synchronization has been established between the two.

The clock switching circuit 17 is provided with a control signal
Synchronous clock CLKs and asynchronous clock CLKa based on CTL
Is switched to generate the main clock CLKm. Specifically, after synchronization is established between the digital controller 1 and the codec LSI 2, the synchronous clock CLKs is output as the main clock CLKm, and before the synchronization is established, the asynchronous clock CLKa is output as the main clock CLKm. It has become so. Although the asynchronous clock CLKa in this example is generated by an oscillation circuit (not shown), the clock supplied via the bus 70 may be converted to a desired frequency by the PLL 15 and used. Good.

Next, the codec LSI 2 includes an oscillation circuit that oscillates a bit clock CLKb using a data buffer, a DAC, an ADC, and a crystal oscillator XTL, and a bit clock CL.
In addition to a frequency dividing circuit that divides Kb to generate a sampling clock, a memory that stores an ID code for identifying a product type is built in. When the output data SDout is supplied to the codec LSI2, the output data SDout is temporarily stored in a data buffer, and then converted into an output tone signal Sout via a DAC. In this example, the bit clock CLKb is 12.288 MHz (= 2
Since the frequency has a frequency of 56 * 48 KHz), the frequency dividing circuit generates a sampling clock by dividing the frequency by 256. The output musical tone signal Sout converted into an analog signal by the DAC is supplied to the external speaker 300 via the audio output terminal 250 so that a musical tone is generated.

The input tone signals Sin1 to Sin3 are supplied to the codec LSI 2 via the audio input terminal 260, the microphone input terminal 270 and the external input terminal 280, and are converted into digital signals by the ADC. I have.

With the above configuration, the digital processing performed by the sound source unit 12, the mixing unit 13, the AC'97 interface 14, and the like is performed after the main body 100 and the docking station 200 are mechanically connected and the synchronization is established by the PLL 15. , Based on the synchronous clock CLKs. Therefore, the digital processing is not performed in a state where the pull-in by the PLL 15 is insufficient, that is, in a state where the synchronous clock CLKs is unstable, and the digital processing is performed based on the stable synchronous clock CLKs. As a result, the stable output data SDout can be transferred to the codec LSI2, and a high-quality output tone signal can be obtained.
You can get Sout.

In this example, the lock switch 60 detects that the main body 100 and the docking station 200 are mechanically connected by the lock mechanism.
Thereafter, the control signal CTL is generated by counting the synchronous clock CLKs. That is, it is a precondition for switching from the asynchronous clock CLKa to the synchronous clock CLKs that the lock mechanism is not separated unless the lock mechanism is released. This is based on the assumption that the main body 100 and the docking station 20 are not locked unless locked by the locking mechanism.
This is because 0 may be separated without an unlocking operation. For example, when the main body 100 and the docking station 200 are mechanically connected, but the connection state is shallow and the two are not locked by the lock mechanism, the main body 100 is separated only by slightly moving the main body 100, It is necessary to lock both again. On the other hand, in this example, the clock switching is performed under the above-described preconditions, so that such an inconvenience does not occur.

2. Next, the operation of the computer system A according to the present embodiment will be described with reference to the drawings. FIG. 3 is a flowchart showing the operation from the connection of the main body and the docking station to the start of data transmission.

Lock switch 6 provided in the lock mechanism
0 constantly monitors whether or not the main body 100 and the docking station 200 are mechanically connected (step S1), and generates a docking signal DOCK indicating the state. Then, when the two are coupled, a docking signal DOCK indicating the coupled state is generated (step S2), and this signal is supplied to the timing generator 16 provided in the digital controller 1 via the bus 70. The bit clock CLKb is supplied from the codec LSI 2 to the digital controller 1 by the combination of the two.

Next, when detecting that the docking signal DOCK has changed from the separated state to the coupled state, the timing generator 16 starts counting the synchronous clock CLKs (step S3), and the counted value reaches a predetermined value. It is determined whether or not (step S4). When the count value is less than the predetermined value, the counting is continued, and when the count value reaches the predetermined value, the control signal CTL is generated (step S5). In this case, the predetermined value is set so as to correspond to the time from when the bit clock CLKb is input to the PLL 15 to when the stable synchronous clock CLKs is obtained as described above. This indicates that the mechanical connection between the docking station 200 and the docking station 200 has been completed, and that a synchronous relationship has been established between the two.

Next, based on the control signal CTL, the clock switching circuit 17 controls the synchronous clock CLKs and the asynchronous clock CLKa.
To generate the main clock CLKm and supply it to each component of the digital controller 1 (step S6). Thereby, the clock can be automatically switched, and after the synchronization is established, the mixing circuit 13 and the AC'97 interface 14 can be operated based on the synchronization clock CLKs.

Thereafter, the ID code is read from the codec LSI 2 via the AC link LINK (step S).
7), transferred to the digital controller 1. By the way, the codec LSI2 complies with the AC'97 standard, but the function can be extended by an option. In a desktop personal computer, the digital controller 1 and the codec LSI 2 are generally arranged on the same board, so that the optional functions of the codec LSI 2 are known. Therefore, the digital controller 1 may be used in consideration of known optional functions.

However, when the main body 100 and the docking station 200 are separated from each other, the main body 100 may be connected to various docking stations 200. Therefore, it is necessary to know the optional function of the codec LSI2 used for each connection.
Reading of the ID code is performed for this purpose. When the ID code is read, the digital controller 1 refers to a table in which the ID code and the optional function are stored in the hard disk 50 in advance, and
An optional function of the combined codec LSI2 is detected. Then, the sound source unit 12 and the mixing unit 13 perform data generation processing according to the detection result.

When the synthesized musical sound data SDmix is generated in this manner, the AC'97 interface 14
Then, an output data SDout and a synchronization signal SYNC conforming to G.7 are generated (step S8), and these are transferred to the codec LSI2 via the AC link LINK. After this, the codec LS
I2 supplies an output tone signal Sout obtained by converting the output data SDout from a digital signal to an analog signal to the external speaker 300 via the audio output terminal 250.
In this case, since the mixing unit 13 does not output the data SDmix ′, the sound generation unit can be automatically switched from the internal speaker 18 to the external speaker 300.

As described above, according to the present embodiment, even when the docking signal DOCK indicates the connection state, the output data SDout is not immediately transferred to the codec LSI2. That is, by counting the synchronization clock CLKs by a predetermined number using the timing generation unit 16, after detecting that the synchronization has been established, digital processing is executed based on the synchronization clock CLKs to generate output data SDout, This is connected to the codec LSI2 via the AC link LINK.
To be forwarded to. Therefore, the output data SDout can be transferred based on the stable synchronous clock CLKs, and the reliability of data transmission can be improved.

Further, according to the present embodiment, it is shown that the coupled state indicated by the docking signal DOCK is not separated unless the lock mechanism is released, and this is a precondition for clock switching. The output data SDout is transferred to the codec LSI2 on condition that the docking station 100 and the docking station 200 are completely mechanically connected and both are locked by the lock mechanism. Thereby, for example, when the user is executing the game software, the main body 100 and the docking station 200 are separated from each other, and the inconvenience that the output tone signal Sout is suddenly interrupted is eliminated, and the output tone signal Sout is stabilized. And can be played.

Further, according to the present embodiment, the digital controller 1 reads out the ID code from the codec LSI 2 and detects its optional function.
Digital processing can be performed in accordance with the type of the codec LSI 2 used in the docking station 200 connected to “0”, and various sound processing can be realized using optional functions.

3. 2. Modifications Although the embodiment according to the invention has been described above, the invention is not limited to the embodiment described above, and various modifications described below are possible. In the embodiment described above, the timing generator 16
Detected that the synchronization between the bit clock CLKb and the synchronization clock CLKs was established by counting the synchronization clock CLKs by a predetermined number, but the present invention is not limited to this. Any means may be used if possible. For example, if the establishment of synchronization is detected by measuring time, the mono-multi may be operated with the docking signal DOCK as a trigger. Alternatively, a predetermined number of bit clocks CLKb may be counted by a counter instead of the synchronous clocks CLKs. In particular, in the latter case, if the electrical connection of the AC link LINK is poor, the bit clock CLKb is not counted, so that the establishment of synchronization can be reliably detected. In this case, the bit clock CL
If Kb is not supplied continuously, the count value may be reset. In the well-known PLL 15, the voltage controlled oscillator generally operates based on a phase error signal obtained by detecting a phase error between the synchronous clock CLKs and the bit clock CLKb, thereby generating the synchronous clock CLKs. Therefore, it may be detected whether or not the phase error signal falls within a certain range, thereby detecting that the synchronization has been established.

In the above-described embodiments and modifications, the lock switch 60 attached to the lock mechanism mechanically couples the main body 100 and the docking station 200 and does not separate them without the release operation. Is detected as a precondition for clock switching. However, the present invention is not limited to this. Only mechanical coupling may be detected, and this may be used as a precondition for clock switching. For example, a detection circuit for detecting the input of the bit clock CLKb may be provided, and this detection signal may be used instead of the docking signal DOCK. In this case,
Since it is possible to detect not only that the main body 100 and the docking station 200 are mechanically coupled but also that they are electrically coupled at the same time, the reliability can be further improved.

Also, in the above-described embodiments and modifications, the coupling of the main body 100 and the docking station 200 by AC'97 has been described as an example. However, the present invention is not limited to this. In a system including a device and a digital signal processing device, when both are separated, digital processing is performed based on an internal clock, and when combined, the digital signal processing device synchronizes with a reference clock supplied from an analog signal processing device. It is needless to say that the technical idea described above may be applied to a digital signal processing device that performs digital processing. In this case, the digital signal processing device performs digital video processing, and may transmit video data to and from the analog signal processing device.

[0041]

As described above, according to the present invention, when data transmission is performed by connecting a digital signal processing device and an analog signal processing device, the two are mechanically connected and synchronized. Is established, the clock is switched, so that data transmission can be performed with high reliability.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a state in which a notebook personal computer and a docking station according to an embodiment of the present invention are connected, viewed from the back side.

FIG. 2 is a block diagram showing an electrical configuration of the computer system according to the embodiment.

FIG. 3 is a flowchart showing an operation from when the main body and the docking station according to the embodiment are connected to when data transmission is started.

FIG. 4 shows a configuration of a system conforming to AC'97.

[Explanation of symbols]

13: mixing unit (digital processing means), 14: A
C'97 interface, 15 PLL (synchronizing means), 16 timing generator (control means, time measuring means), 17 clock switching circuit (control means, clock switching means), 60 lock switch (detecting means), 100
... notebook personal computer (digital signal processor), 200 ... docking station (analog signal processor), CLKa ... asynchronous clock (internal clock), CLKb ... bit clock (reference clock), CLKs ...
Synchronous clock.

Claims (6)

[Claims] An analog signal processing device that performs analog processing is used in a separated or combined manner. In a separated state, digital processing is performed based on an internal clock. In a combined state, a digital clock is applied to a reference clock supplied from the analog signal processing device. A digital signal processing device that performs digital processing in synchronization with the digital signal processing device; a detection unit that detects that the digital signal processing unit is mechanically coupled to the analog signal processing device; a synchronization unit that generates a synchronization clock synchronized with the reference clock; Control means for controlling that the digital processing is performed based on the synchronization clock after the mechanical connection with the analog signal processing device is detected by the means, and after the synchronization by the synchronization means is established; A digital signal processing device comprising: 2. A time measuring means for starting measurement based on a detection result of the detecting means and measuring at least a time until the synchronous clock generated by the clock generating means is stabilized, 2. The digital signal processing device according to claim 1, further comprising: a clock switching unit that switches a clock used for the digital processing from the internal clock to the synchronous clock based on a measurement result of the time measurement unit. 3. The digital signal processing device according to claim 2, wherein said time measuring means measures time by counting said synchronous clock or said reference clock. 4. A notebook computer and a docking station, wherein the notebook computer performs digital processing based on an internal clock in a separated state,
A computer system that performs digital processing in synchronization with a reference clock supplied from the docking station, wherein the docking station includes: an oscillation circuit that generates and outputs the reference clock; and a digital signal that is analog using the reference clock. A digital / analog converter for converting the signal into a signal, the notebook computer detecting means for detecting that the docking station is mechanically coupled to the docking station, and synchronizing with the reference clock supplied from the docking station. Synchronizing means for generating a synchronous clock, and starting counting of the synchronous clock or the reference clock based on a detection result of the detecting means,
Time measuring means for measuring a predetermined time; clock switching means for switching a clock used for digital processing from the internal clock to the synchronous clock after a predetermined time is measured by the time measuring means; Digital processing means for performing digital processing based on a clock output from the; a transfer means for transferring the output data processed by the digital processing means to the docking station after a certain time has been measured by the time measuring means; A computer system comprising: 5. The docking station includes storage means for storing identification data for identifying an optional function, wherein the digital processing means stores the identification data after a predetermined time has been measured by the time measurement means. The computer system according to claim 4, wherein the computer system reads out from the storage unit and performs digital processing based on the identification data. 6. The device according to claim 4, wherein the detecting means detects that the notebook computer and the docking station are mechanically connected to each other and cannot be separated without an unlocking operation. A computer system according to claim 1.