JPH06296173A - Digital audio interface receiver - Google Patents

Abstract

PURPOSE:To reduce a jitter quantity in a signal processing section of a transmitter to an equal degree of jitter quantity of a crystal oscillatidn circuit provided to the receiver. CONSTITUTION:The receiver is provided with a crystal oscillation circuit 3 being an oscillation source used to synchronize a transmitter of a digital audio signal externally and a frequency divider 5 generating an external synchronizing signal and data extracted by a digital audio interface demodulation circuit 16 of the receiver are processed by a sampling frequency 6a and a bit clock 6b generated by frequency-dividing an output of the crystal oscillation circuit 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital audio interface receiver having an external synchronizing function for synchronizing and using a digital audio interface transmitter, and more particularly to a compact disc player having a digital output. Related to digital amplifiers.

[0002]

2. Description of the Related Art For example, in a configuration such as a digital amplifier in which a signal output of a compact disc player is a digital output and the signal is amplified as an input signal, a crystal oscillation circuit which is an original oscillation is generally provided on a transmitter side for transmitting a signal, The receiving device that outputs the digital audio interface signal synchronized with the original oscillation, demodulates the signal, and outputs the signal is the PLL.
The circuit extracts the clock synchronized with the original oscillation, extracts the data, and performs signal processing in the subsequent stage.

When the transmitter has an external synchronizing function, the PLL circuit is synchronized with a reference clock generated externally and a digital audio interface signal is output. Then, on the signal receiving device side, a clock synchronized with the input digital audio interface signal is extracted by the PLL circuit, data is extracted, and signal processing is performed in the subsequent stage.

[0004]

However, since the receiving device side uses the clock extracted from the digital audio interface signal, it has a drawback that it includes jitter.

[0005]

Therefore, in the present invention, the receiving device side has a crystal oscillating circuit to be the original oscillation, and the transmitting device side is synchronized with the original oscillation. In this way, data is extracted from the digital audio interface signal synchronized with the original oscillation, and the data is latched and processed by the bit clock generated by dividing the original oscillation and the sampling frequency.

[0006]

Therefore, since the data is processed by the clock generated by the crystal oscillation circuit which is the original oscillation, the amount of jitter can be reduced to the same level as that of the crystal oscillation.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the block diagram of FIG. In this embodiment, a compact disc (CD)
Is shown by the structure of a CD player 1 that reproduces a digital output and a digital amplifier 2 that receives a digital signal. In the figure, a crystal oscillator circuit 3 generates a system clock 4 which is an original oscillation, and a frequency divider 5 generates a sampling frequency 6a. External synchronization signal 8 output via the output buffer 7
Is input to the PLL circuit 10 via the input buffer 9 of the CD player 1.

The PLL circuit 10 generates a system clock 11 synchronized with the sampling frequency 6a. The system clock 11 is sent to the signal processing circuit 12, and the sampling frequency 6
data signal 13a and bit clock 13 synchronized with a
b, the word clock 13c is generated. These signals are output as a digital audio interface signal 15 by the digital audio interface modulation circuit 14.

The digital audio interface signal 15 is input to the digital audio interface demodulation circuit 16 of the digital amplifier 2. In the digital audio interface demodulation circuit 16, the digital audio interface signal 15 to the data signal 17
a, the sampling frequency 17b, and the bit clock 17c are extracted.

The data signal 17a is generated by the system clock 4
Since it is synchronized with, the signal processing can be performed with the sampling frequency 6a generated by dividing the system clock 4 by the frequency divider 5 and the bit clock 6b. In FIG. 1, as an example of a signal processing circuit, a D / A converter 18 converts an audio signal and an amplifier 20 obtains an audio output.

Here, the bit clock 17c extracted from the digital audio interface demodulation circuit 16 and the bit clock 6b generated by the frequency divider 5 are detected by the phase comparator 21 as to whether or not they are synchronized, and the bit is selected by the selector 22. The clock and sampling frequency are those from the digital audio interface demodulation circuit 16,
The one from the frequency divider 5 is switched by the phase matching signal 19. This ensures that if the digital audio interface signal is out of sync with the sync signal,
The clock of the digital audio interface transmitter can be automatically switched. However, in this case, the amount of jitter is not the crystal oscillation accuracy.

As another embodiment, a plurality of Cs are used.
It is used for the D player 1 and the digital audio interface switching device 23. FIG. 2 shows a schematic configuration diagram thereof. The sampling frequency 24 is received from the outside, and the system clock 4 is generated by the PLL 10. Where PLL1
The crystal oscillator circuit 3 may be 0. This system clock 4 is frequency-divided by a frequency divider 5, and a plurality of Cs are provided as a synchronization signal 8.
Output to D player 1.

The CD player 1 outputs a digital audio interface signal 15 synchronized with the synchronizing signal 8. The digital audio interface switching device 23 obtains the data signal 17a from the digital audio interface signal 15 output from each CD player 1 by the digital audio interface demodulation circuit 16.

This is selected by the data selector 25 by the input switching signal 26 and input to the digital audio interface modulation circuit 14. By inputting the sampling frequency 6a generated by the frequency divider 5 and the bit clock 6b to the digital audio interface modulation circuit 14, it is possible to output a digital audio interface signal 15b with a jitter accuracy of one PLL stage.

[0015]

As described above, according to the present invention, the amount of jitter in the signal processing circuit of the transmitter can be reduced to a level equivalent to that of the crystal oscillator circuit provided in the receiver.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

[Explanation of symbols]

1 CD player 2 Digital amplifier 3 Crystal oscillator circuit 4 System clock 5 Divider 6a Sampling frequency 6b Bit clock 7 Output buffer 8 Sync signal 9 Input buffer 10 PLL circuit 11 System clock 12 Signal processing circuit 13a Data signal 13b Bit clock 13c Word clock 14 Digital audio interface modulation circuit 15 Digital audio interface signal 16 Digital audio interface demodulation circuit 17a Data signal 17b Sampling frequency 17c Bit clock 18 D / A converter 19 Phase matching signal 20 Amplifier 21 Phase comparator 22 Selector 23 Digital audio interface Switching device 24 Sampling frequency 25 Data selector 26 Input switching signal

Claims (1)

[Claims] 1. A crystal oscillating circuit serving as an original oscillation for externally synchronizing a transmitting device of a digital audio signal, and a frequency divider for generating an external synchronizing signal, wherein an output of the crystal oscillating circuit is divided. A digital audio interface receiving device, characterized in that data extracted by a digital audio interface demodulation circuit is subjected to signal processing by a sampling frequency and a bit clock generated by frequency division.