JPH11203877A - Semiconductor integrated circuit and design method thereof - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To optimize a sense amplifier activation timing with respect to a word line selection timing without performing a special tuning process. SOLUTION: A dummy memory cell (110) whose selection timing is synchronized with a word line selection timing, and a level change timing of a data line synchronized with a data read operation from the memory cell is set on a dummy data line (DBL). Simulate. The phase comparison circuit (130) increases the value of the counter (95) according to the phase difference between the change applied to the dummy data line through the operation of selecting the dummy memory cell and the change in the sense amplifier activation signal (VDL). A variable delay circuit (94) for instructing a count or a down count and receiving the count value controls the activation timing by the sense amplifier activation signal to be shifted so as to cancel the phase difference.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit including a memory, and more particularly to a technique for optimizing a sense amplifier activation timing with respect to a data line level change timing synchronized with a data read operation from a memory cell. For example, SRAM (Static Random Access Memor)
y: static random access memory) or S
The present invention relates to a technology effective when applied to a data processing device such as a microcomputer including a cache memory composed of a RAM.

[0002]

2. Description of the Related Art In an SRAM, a complementary data line (bit line) is precharged to a voltage near a power supply voltage before data reading is started. When the word line is set to the selection level, the voltage of the complementary data line is complementarily changed according to the storage information of the memory cell to which the selection terminal is coupled. The potential difference between the complementary data lines thus obtained is detected and amplified by the sense amplifier, and the logical value of the read data is determined. At this time, the timing for activating the sense amplifier is optimal immediately after the complementary data line starts changing complementarily according to the storage information of the memory cell. If the activation timing of the sense amplifier is earlier than that, the sense amplifier may output erroneous data once, and the logical value determination of the read data is undesirably delayed,
If the timing shift is remarkable, a malfunction may occur in data access by a microprocessor or the like. On the contrary, if it is too late, the operation of the sense amplifier is delayed every time, and accordingly, high-speed reading of data cannot be realized.

An operation delay time from a word line selection to a level change of a complementary data line is affected by a load on a complementary bit line or a scale of a memory cell array. Therefore, SRA
When the product type is developed by changing the storage capacity of M, the timing for activating the sense amplifier by the timing generation circuit is tuned according to the scale of the memory cell array, or
A redundant margin can be secured in advance at the sense amplifier activation timing with respect to the word line selection timing so that the present invention can be applied even when the storage capacity is large.

As an example of a document describing SRAM, there is “LSI Handbook”, pages 500 to 505, issued by Ohm Co., Ltd. on November 30, 1984.

[0005]

However, when memory types are developed with different storage capacities, when tuning the sense amplifier activation timing or the like by a timing generation circuit for each individual memory, the specification required by the user is required. Cannot be answered immediately. On the other hand, if an attempt is made to secure a redundant margin in advance to the sense amplifier activation timing with respect to the word line selection timing, high speed access is sacrificed even for a product having a small storage capacity that can be accessed at high speed. turn into.

An object of the present invention is to provide a semiconductor integrated circuit which can optimize the sense amplifier activation timing with respect to the word line selection timing without tuning the sense amplifier activation timing or the like by the timing generation circuit.

Another object of the present invention is to provide a semiconductor integrated circuit capable of optimizing a sense amplifier activation timing with respect to a word line selection timing without previously securing a redundant margin for a sense amplifier activation timing with respect to a word line selection timing. It is to provide a circuit.

Another object of the present invention is to provide a method of designing a semiconductor integrated circuit which can easily optimize a sense amplifier activation timing with respect to a word line selection timing depending on a circuit size of a memory cell array. .

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

[1] A semiconductor integrated circuit includes a memory (1) on one semiconductor substrate. This memory includes a memory cell array having a plurality of memory cells (5) each having a selection terminal connected to a word line (WL) and a data terminal connected to a data line (BL, BLb), and a word in the memory cell array. Word driver circuit for driving lines (3u)
A column switch circuit (6) for selecting a data line of the memory cell array; a sense amplifier circuit (7) for amplifying data on a data line selected by the column switch circuit; and a clock signal (CLK), respectively. And a timing generation circuit (93) for generating a sense amplifier activation clock signal (φ3). Further, this memory has a dummy memory cell (110) whose selection timing is synchronized with the word line selection timing, and the dummy memory cell determines a level change timing of the data line which is synchronized with a data read operation from the memory cell. A dummy memory cell array simulating on the connected dummy data lines (DBL, DBLb), and a dummy memory cell selection circuit () for receiving the word line selection clock signal and forming the dummy memory cell selection signal (123). 12u) and a timing compensating circuit (94, 9) for compensating the target timing of the sense amplifier activation with respect to the word line selection timing.
5,130). The timing compensation circuit includes:
A variable delay circuit (94) for receiving the sense amplifier activation clock signal and forming a sense amplifier activation signal (VDL); The variable delay circuit is configured to control the sense amplifier activation clock signal (φ) based on early or late of the sense amplifier activation signal (VDL) with respect to a level change timing simulated on the dummy data line (DBL).
The delay time of the sense amplifier activation signal (VDL) with respect to 3) is made variable.

As described above, the change of the data line due to the word line selection operation is simulated by the change of the dummy data line to determine the sense amplifier activation timing. Therefore, the frequency of the clock signal (CLK) and the variation in the device process are varied. The timing for activating the sense amplifier can be optimized without being affected by the above. Therefore, a malfunction can be prevented, and an excessive timing margin for the sense amplifier activation timing need not be expected.
Therefore, the speed of the access operation can be increased in the entire memory.

[2] The timing compensating circuit includes: a phase comparing circuit (130) for detecting early or late between the sense amplifier activating timing and a level change timing simulated on the dummy data line; Counter (9) that counts up / down according to the comparison result
5), and the variable delay circuit (94) can be configured to make the delay time of the sense amplifier activation signal (VDL) variable according to the magnitude of the count value of the counter. The phase comparison circuit instructs the counter to up-count or down-count in accordance with the phase difference between the change applied to the dummy data line through the operation of selecting the dummy memory cell and the change in the sense amplifier activation signal. The variable delay circuit receiving the count value controls so as to shift the timing of the activation timing by the sense amplifier activation signal so as to cancel the phase difference. As described above, the variable delay circuit, the phase comparison circuit, and the counter form a negative feedback loop. By performing the phase difference canceling operation as a training operation, the change in the sense amplifier activation signal and the dummy data line The phase with the change can be almost aligned and stabilized. It is sufficient that such a training operation be performed immediately after the clock signal is supplied to the memory.

[3] The semiconductor integrated circuit may be an LSI (Large Scale Integrated Circuits) composed of a single memory. In addition, the memory may be a logic LSI (201) such as a microcomputer or a microprocessor including a central processing unit (202) for executing an instruction. At this time, the central processing unit generates an address signal for addressing the memory.

[4] For the timing generation circuit, the dummy memory cell selection circuit is more Y than the word driver circuit.
A dummy memory cell disposed at a far end in the direction, and receiving a dummy word line selection signal output from the dummy memory cell selection circuit, disposed at a far end in the Y and X directions relative to the memory cell array with respect to the timing generation circuit; The phase comparison circuit can be arranged farther in the X direction than the sense amplifier circuit with respect to the timing generation circuit. Therefore, starting from the timing generation circuit (93) for generating the word line selection clock signal (φ1) and the sense amplifier activation signal (VDL), the operation from the dummy word line selection to the change in the dummy data line appears. The delay time and the operation delay time until the sense amplifier activation signal (VDL) is transmitted to the farthest end of the transmission path are always maximized for each layout configuration according to the storage capacity. Therefore, the sense amplifier activation timing is automatically optimized according to the storage capacity of the memory or the layout configuration.
Regarding the sense amplifier activation timing, there is no need for individual tuning processing in design.

[5] In the design method for developing the type of memory having the configuration of [4] in accordance with the desired storage capacity, the design method for determining the storage capacity of the memory and the number of data input / output bits is as follows. 1 process, a memory cell array unit for configuring the memory cell array by satisfying the storage capacity and the number of data input / output bits determined in the first process, and a word driver for configuring the word driver circuit A second process of determining a layout of a circuit unit, a column unit for configuring the column switch circuit and the sense amplifier circuit, and a dummy memory cell array unit for configuring the dummy memory cell array. Including. The above [4]
By satisfying the layout rules described in (1), the sense amplifier activation timing in the memories developed with different storage capacities can be optimally defined even when the memory type is developed according to the storage capacities. At this time, as described above, no special tuning is required in design to optimize the delay time. Since the optimization is automatically performed, it is possible to contribute to shortening the design period of a semiconductor integrated circuit that is developed in accordance with the storage capacity.

[6] The second processing can be performed using the design data of the memory cell array unit, word driver circuit unit, column unit, and dummy memory cell array unit already designed.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS << SRAM >> FIG. 1 shows a block diagram of an SRAM according to an example of the present invention. Although not particularly limited, the SRAM 1 shown in FIG. 1 is formed on one semiconductor substrate such as single crystal silicon by a CMOS integrated circuit manufacturing technique.

The SRAM 1 shown in FIG. 1 employs a circuit configuration for increasing or decreasing the storage capacity and easy to develop. In other words, it is designed by a design method that facilitates such kind development.

The SRAM 1 shown in FIG. 1 forms a memory cell array unit 2u for forming a memory cell array, a word driver circuit unit 3u for forming a word driver circuit, a column switch circuit and a sense amplifier circuit. Is designed as a design unit for determining the circuit scale of the memory cell array.

The memory cell array unit 2u includes memory cells (MC) 5 arranged in a matrix, word lines WL connected to select terminals of the memory cells, and complementary data lines BL connected to data input / output terminals of the memory cells. , B
Lb. Although the word line shown in FIG. 1 is not particularly limited, it has a main / sub word line structure, a selection terminal of a memory cell is connected to a sub word line made of polysilicon, and a plurality of sub word lines are made of a main line made of aluminum wiring. Connected to word line. Although a pair of the complementary data lines BL and BLb is shown as a representative, actually, a predetermined number of the data lines are provided.

The column unit 4u selectively connects the complementary data lines BL and BLb to the complementary common data lines CD and CD.
b, a sense amplifier circuit 7 for detecting and amplifying the potential difference between the complementary common data lines CD and CDb, and an output buffer circuit 8 for outputting the output of the sense amplifier circuit 7 to the outside.

The word driver circuit unit 3u
Have a number of word drivers corresponding to the number of word lines of one memory cell array unit 2u. The word driver is a series of two-stage drive inverters 30, 31
And a p-channel MOS transistor Qp1 and an n-channel MOS transistor Qn2 whose gate electrodes are commonly connected to the input terminal P1. The MOS transistor Qp1 is connected between the input of the first-stage inverter 30 and the power supply terminal Vdd.
, And the MOS transistor Qn2 is arranged between the input terminal P2 and the input of the first-stage inverter 30. The MOS transistors Qp1 and Qn2 constitute a part of decode logic for selecting a word line, and a predecode signal described later is supplied to the input terminals P1 and P2. In the drawings referred to in this specification, the p-channel MOS transistor is distinguished from the n-channel MOS transistor by adding an arrow to the base gate thereof.

In the SRAM 1, the number of the memory cell array unit 2u arranged in the row direction and the number of the memory cell array unit 2u arranged in the column direction are determined in accordance with the required scale (storage capacity) of the memory cell array. Word driver circuit unit 3u
Is a number corresponding to the number of arranged rows of the memory cell array unit 2u. The column unit 4u
Is a number corresponding to the number of arranged columns of the memory cell array unit 2u.

The control unit 9u includes an address buffer 9
0, a row predecoder 91, a column decoder 92, a timing generator 93, a variable delay circuit 94, and a counter 95.

The timing generator 93 has a clock signal (word line selection clock signal) φ1 for determining a word line selection timing and a clock signal (column selection clock) for determining a column selection timing based on an externally supplied clock signal CLK. Clock signal) and a clock signal (sense amplifier activation clock signal) φ3 used for generating the activation timing of the sense amplifier. Timing generator 93 automatically generates and outputs clock signals φ1, φ2, φ3 in synchronization with a change cycle of clock signal CLK supplied from the outside.

The address buffer 90 has a row address signal 10R and a column address signal 1 supplied from outside.
0C is converted to an internal complementary address signal. Each row predecoder 91 generates a predecode signal by taking a NOR logic with respect to a 2-bit internal complementary address signal corresponding to the row address signal 10R, although there is no particular limitation. The decoding operation of row predecoder 91 is synchronized with clock signal φ1. A predecode signal formed by a plurality of row predecoders 91 is allocated to and supplied to the plurality of word drivers 3u, whereby a word line selecting operation is performed.

The column decoder 92 decodes an internal complementary address signal corresponding to the column address signal 10C to generate a selection signal for the column switch circuit 6.

The variable delay circuit 94 receives the clock signal φ3
Is input to the clock signal φ3, and the 6-bit count data S32, S16, S8, S4, S2,
By giving a delay according to S1, the sense amplifier activation signal VD
Generate L. According to this example, the counter 95 is 6
It is a binary counter of bits. The counter 95 increments or decrements a clock signal (not shown). When the up signal UP is asserted, an increment operation (up count operation) is performed,
When the down signal DN is asserted, a decrement operation (down count operation) is performed.

An example of the variable delay circuit 94 is shown in FIG. The variable delay circuit 94 shown in the figure includes a first circuit portion 94A for controlling the number of gates through which the clock signal φ3 passes to make the delay time variable, and a variable delay time by controlling the operation current of the output circuit. The second circuit part 9
4B.

The first circuit portion 94A receives the clock signal φ.
The clocked inverter (inverter, p
Channel type MOS transistor and n-channel type M
CIV1 (illustrated by OS transistors)
CIV6 and inverters IV1 to IV4. The transmission path of the clock signal φ3 is selected by the upper two bits of the count data S32 and S16. That is, the clock signal φ3 passes through the clocked inverter CIV1 at S32, S16 = 1, 1, and S32, S16 = 1, 0
Inverter IV1 and clocked inverter CIC
2, CIV3, S32, S16 = 0, 1, inverters IV1, IV2 and clocked inverter CIC
4, CIV5, CIV3, S32, S16 =
At 0,0, it passes through inverters IV1 to IV4 and clocked inverters CIC6, CIV5, CIV3. As the values of the count data S32 and S16 are larger, the number of inverters and clocked inverters interposed in the transmission path of the clock signal φ3 is reduced, and the delay time is reduced.

The second circuit portion 94B outputs an output from the first circuit portion 94A through a series circuit of a clocked inverter CIV7, an inverter IV5, and a clocked inverter CIV8 to output a sense amplifier activation signal VDL. The operating current of the clocked inverters CIV7 and CIV8 is n-channel type control MOS transistor Qn5.
To Qn8 in proportion to the conductance. The MOS transistors Qn8, Qn7, Qn6, Qn5
The lower 4 bits of the count data S
8, S4, S2, S1 are supplied.

According to the example of FIG. 2, the variable delay circuit 94
6-bit count data S32, S16, S8, S4, S
2. As the value of S1 increases, the delay time of the sense amplifier activation signal VDL decreases.

The up signal UP and the down signal DN are generated by a phase comparison circuit 130. Phase comparison circuit 130
Detects the phase difference between the level change of the sense amplifier activation signal VDL and the level change of the dummy data line DBL, and if the change of the sense amplifier activation signal VDL is slower than the level change of the dummy data line, Up signal UP
Is asserted, and if fast, the down signal DN is asserted. The dummy memory cell 11 is connected to the dummy data line DBL.
A read signal from 0 is provided. FIG. 3 shows an example logic circuit diagram of the phase comparison circuit 130.

The dummy memory cell 110 is included in a dummy memory cell array unit 11u for forming a dummy memory cell array. The dummy memory cell array unit has a configuration electrically equivalent to the configuration related to the pair of bit lines of the memory cell array unit 2u, and is provided at a position farthest from the word driver circuit unit 3u. 2u
Are arranged in the area next to the. BLD, BLDb are a pair of dummy data lines, 110 is a dummy memory cell, DWL
Is a dummy word line. The dummy memory cell 110 is
As illustrated in FIG. 4, the memory information is different from the memory cell 5 in that the storage information is fixed. For example, the input of the CMOS inverter 110A in the CMOS static latch is coupled to the power supply voltage Vdd, and the dummy memory cell 11
0 indicates that when it is selected, its CMOS inverter 1
10A tries to output a low level, and the CMOS inverter 110B tries to output a high level. Incidentally, the dummy data line DB
The illustration of the precharge circuit and the equalize circuit of L and DBLb is omitted.

Dummy memory cell array unit 11
u is a number corresponding to the number of arranged columns of the memory cell array unit 2u. The dummy data lines DBL, DB
Lb is commonly connected between the dummy memory cell array unit units 11u, and one dummy data line DBL is connected to the CMO
The logic is inverted by the S inverter 131 and the phase comparison circuit 13
0 is supplied. The phase comparison circuit 130 and the CMOS inverter 131 are included in the phase comparison unit 13u, and are arranged in parallel with the column unit 4u.

The dummy word line DWL is located at a position farthest from the phase comparison circuit 130.
Dummy word line selection signal 123 is supplied corresponding to only dummy memory cell 110 coupled to DBLb. The other dummy word lines DWL are always supplied with the non-selection level via the ground terminal Vss.

The dummy word line selection signal 123 is generated by the dummy word line selection unit 12u, and is generated by the dummy word driver 122, the dummy row predecoder 1
21 and a counter 120. The dummy word driver 122 and the dummy row predecoder 121
It has the same circuit configuration as the word driver unit 3u and the row predecoder 91. The counter 120 is 2
It is a bit counter that counts the clock signal CLK. The dummy predecoder 121 outputs the timing signal φ1
When the 2-bit output of the counter 120 is 1, 1 in synchronization with the operation timing of the row predecoder 91, the dummy word line selection signal 123 is changed to the selection level. Therefore, dummy word line selection signal 123
Is set to the selection level once every four times of the word line selection timing synchronized with the clock signal CLK.

Next, the operation of generating the sense amplifier activation timing in the SRAM will be described. SRAM
, The timing generator 93 synchronizes with the clock signal CLK to supply the clock signal φ 1,
The counter 120 outputs φ2 and φ3, and the counter 120 repeats the counting operation. As a result, the dummy word line selection signal 123 is set to the selection level once every four times of the word line selection timing synchronized with the clock signal CLK. Each time, the dummy data line is selected through the dummy memory cell 110 selection operation. DBL repeatedly changes from high level to low level. This change is applied to one input terminal of the phase comparison circuit 130 via the inverter 131. Phase comparison circuit 1
30 has a sense amplifier activation signal VD
The inverted level of L is provided, and the phase difference between the transition of both signals to low level is detected. When the change of the sense amplifier activating signal is slow with respect to the level change of the dummy data line, the up signal UP is asserted, and when it is fast, the down signal DN is asserted. The counter 95 outputs an up signal UP
Up count (increment) by
Down count (decrement) is performed by the down signal DN. Variable delay circuit 94, phase comparison circuit 13
0 and the counter 95 constitute a negative feedback loop,
By performing the above operation (training operation), the change of the sense amplifier activating signal VDL and the dummy data line D
The phase with the change in BL is stabilized almost completely.

The change from the high level to the low level of the dummy data line DBL is slightly delayed from the operation of selecting the word line of any memory cell. The dummy word line selection unit 12u is arranged at the farthest end in the column direction from the timing generator 93 for any row predecoder 91,
This is because the dummy memory cell 110 selected by the dummy word line selection signal 123 is located farthest in the row direction than any of the memory cells 5. Therefore, after the training period, the sense amplifier activation timing by the sense amplifier activation signal VDL is optimized with respect to the word line selection timing. This state is shown in FIG. 5B, and the sense amplifier is activated immediately after the complementary bit line starts to change the level complementarily in accordance with the storage information of the memory cell due to the word line selection. This prevents the sense amplifier activation timing from being too early as shown in FIG. 3A or the sense amplifier activation timing being too late as shown in FIG.

As is apparent from the above operation, the sense amplifier activation timing is determined by simulating the change of the complementary bit line due to the word line selection operation by the change of the dummy data line, so that the frequency of the clock signal CLK, SR
The sense amplifier activation timing can be optimized without being affected by variations in the AM device process. Therefore, malfunction can be prevented, and
It is not necessary to expect an excessive timing margin with respect to the sense amplifier activation timing. From the above, SRA
As a whole, the speed of the memory access operation can be increased as a whole.

<< Development of SRAM Type >> Next, the above SRAM
Will be described. If the SRAM 1 is developed in accordance with the required storage capacity, the word driver circuit unit (B) may be used in accordance with the required storage capacity.
0) 3u, memory cell array unit (D0) 2
u, the number of column unit (C0) 4u, and the number of dummy memory cell array unit (X1) 11u are determined. The control unit (A0) 9u and the phase comparison unit (X
0) 13u, dummy word line selection unit (X2) 12
u is adopted one by one regardless of the storage capacity. For example, FIG. 6 shows a relatively large storage capacity (large number of words and bits).
FIG. 7 shows an example of a layout configuration of each unit when the SRAM is developed, and FIG. 7 shows an example of a layout configuration of each unit when the SRAM is developed with the minimum storage capacity (the number of words and bits is small). .

In the layout configuration of FIGS. 6 and 7, the dummy word line selection unit (X2) 12u is arranged at the farthest end in the column direction with respect to the control unit (A0) 9u, regardless of the storage capacity. Word line selection signal 123
Memory cell array unit (X1) receiving the
11u is arranged at the farthest end in the column direction and the row direction with respect to the control unit (A0) 9u, and the phase comparison unit (X
0) 13u is arranged at the farthest end in the row direction with respect to the control unit (A0) 9u. Therefore, the clock signal φ
1. Starting from the control unit (A0) 9u that generates the sense amplifier activation signal VDL, an operation delay time from the selection of the dummy word line to the appearance of a change in the dummy data line;
The operation delay time until the sense amplifier activation signal VDL is transmitted to the farthest end of the transmission path is always maximized for each layout configuration according to the storage capacity. Therefore, the sense amplifier activation timing is automatically optimized by the layout configuration.

For example, FIG. 8 shows a change in the sense amplifier activation signal VDL with respect to the clock signal CLK in a layout configuration having a large storage capacity corresponding to FIG. 6, and FIG. 9 shows a small storage corresponding to FIG. FIG. 14 shows a change in a sense amplifier activation signal VDL with respect to a clock signal CLK in a layout configuration having a capacitance. The activation timing of the sense amplifier is delayed in FIG. 8 corresponding to the SRAM having a large storage capacity (T1> T2). Time T
Reference numerals 1 and T2 define optimized sense amplifier activation timings in SRAMs developed with different storage capacities. As described above, no special tuning is required for the design in order to optimize the delay time. Optimized automatically.

As shown in FIGS. 6 and 7, a design method for developing an SRAM with a required storage capacity can be performed in accordance with the procedure shown in FIG. The procedure includes a process of determining a memory capacity (S1), a process of determining a design unit of a memory cell array (S2), a circuit design and layout design process of a design unit (S3), and an entire memory using data of a design unit. Layout design processing (S4).

The processing for determining the memory capacity (S1) is to determine the storage capacity of the entire memory and the number of data input / output bits according to the specification required by the user. In the process of determining the design unit of the memory cell array (S2), the word driver circuit unit (B0) 3 is used to satisfy the storage capacity of the entire memory and the number of data input / output bits.
u, the number of memory cell array unit (D0) 2u, the number of column unit (C0) 4u, and the number of dummy memory cell array unit (X1) 11u, in other words, the size of each circuit is determined. Based on this, the word driver circuit unit (B0) 3
u, the memory cell array unit (D0) 2u, the column unit (C0) 4u, and the dummy memory cell array unit (X1) 11u, etc. The circuit design and layout design processing (S3) are performed. This processing (S3) is also performed on the control unit (A0) 9u, the phase comparison unit (X0) 13u, and the dummy word line selection unit (X2) 12u. If the circuit of the design unit is already provided in a library or the like, the library data can be used without newly developing a design unit circuit.

Then, a layout design process (S4) for the entire memory using the data of the design unit is performed. In the layout design process, the layout rules described with reference to FIGS. 6 and 7 are satisfied.

<< Microcomputer >> FIG. 11 is a block diagram of a microcomputer (single-chip microprocessor, single-chip microcontroller) using the SRAM 1. A microcomputer (MPU) 201 shown in FIG. 1 is formed on one semiconductor substrate (semiconductor chip) such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique, for example. Although not particularly limited, the microcomputer 1 includes a local bus L-bus, an internal bus I-bus, a peripheral bus P-bus, and the like. These buses are provided with data, address, and control signal lines.

The local bus L-bus includes, but is not limited to, a central processing unit (CPU) 202, a digital signal processor (DSP) 203, a cache memory (CACHE) 204, and a clock pulse generator (CPG) 214. Is done. The cache memory 204 is coupled on the other hand to an internal bus I-bus, which has a write-back buffer (WBBUF) 206 and a bus controller (BSC).
207 are connected. The bus controller 207 is connected to the external input / output circuit (EXIF) 209 and the peripheral bus P-bus. The external input / output circuit 209 is
It is possible to interface with an external bus EX-bus having signal lines for address, data and control signals. External memory (EMEM) for external bus EX-bus
220 is representatively shown. The peripheral bus P-bus includes, for example, a direct memory access controller (DMAC) 20 as a peripheral module.
8 and other peripheral circuits (PMD) 210 are coupled.

The microcomputer 1 is operated in synchronization with a clock signal 215 output from a clock pulse generator (CPG) 214. The CPU 202
And DMAC 208 constitute a bus master module. The other peripheral circuits 210 are, but not limited to, a serial communication interface controller, a real-time clock circuit, a timer circuit, and the like. The peripheral circuit 210 is connected to the bus controller 207.
Via the CPU 202 or the DMAC 208.

Although not particularly limited, the CPU 202 controls an arithmetic unit represented by a general-purpose register and an arithmetic and logic unit, a control register group such as a program counter, and fetches and decodes an instruction, and controls an instruction execution procedure. An instruction control unit for performing arithmetic control is provided. The CPU
202 fetches an instruction from an external memory 220 or the like,
By decoding the instruction with an instruction decoder, data processing according to the instruction is performed. CPU 202 is a DSP
In addition to performing a data fetch for 203,
Fetch all instructions including fixed point instructions for SP203.

The bus controller 207 includes a CPU 2
The bus cycle is controlled by controlling access data size, access time, insertion of a wait state, and the like according to an access target circuit (address area to be accessed) by the DMAC 02 or the DMAC 208.

Although not particularly limited, the cache memory 2
04 is applied to the SRAM 1. If the cache memory 204 is set associative, the SR
AM1 is used for an address array and a data array which constitute each way of the cache memory 204. In the microcomputer 201, the memory access speed of the CPU 202 can be increased by securing a certain amount of storage capacity of the built-in cache memory 204, but the chip size of the microcomputer is correspondingly increased. The storage capacity of the cache memory 204 is determined according to the chip size, the use of the microcomputer, and the like. At this time, SR
AM1 is automatically optimized for the sense amplifier activation timing in consideration of the product development for the storage capacity.
This can contribute to shortening the design period of the microcomputer that meets the specifications required by the user and increasing the data processing speed.

Although the invention made by the inventor has been specifically described based on the embodiment, it is needless to say that the present invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. No.

For example, the memory cell of the SRAM is CMOS
It is not limited to the static type, but may be a resistance load type. Further, the control format of the SRAM may be the same as that of a so-called synchronous SRAM which gives an operation in a command format. Further, the semiconductor integrated circuit incorporating the SRAM is not limited to the microcomputer, but may be another logic LSI.

[0056]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

[1] The change in the data line due to the word line selection operation is simulated by the change in the dummy data line to determine the sense amplifier activation timing. Therefore, the variation in the frequency of the clock signal (CLK) and the device process The timing for activating the sense amplifier can be optimized without being affected by the above. Therefore, a malfunction can be prevented, and an excessive timing margin for the sense amplifier activation timing need not be expected. Therefore, the speed of the access operation can be increased in the entire memory.

[2] When the timing compensating circuit is constituted by a phase comparing circuit, a counter, and a variable delay circuit, the phase comparing circuit is capable of controlling a change given to a dummy data line through a dummy memory cell selecting operation. In response to a phase difference from the change in the sense amplifier activation signal, the counter instructs an up-count or a down-count, and a variable delay circuit receiving the count value uses a sense amplifier activation signal so as to cancel the phase difference. The activation timing is controlled so as to be shifted. Since the variable delay circuit, the phase comparison circuit, and the counter form a negative feedback loop, by performing the phase difference canceling operation as a training operation, the phase of the change of the sense amplifier activation signal and the change of the dummy data line can be changed. The operation of stabilizing almost the same can be facilitated.

[3] The dummy memory cell selection circuit is more Y than the word driver circuit for the timing generation circuit.
A dummy memory cell disposed at a far end in the direction, and receiving a dummy word line selection signal output from the dummy memory cell selection circuit, disposed at a far end in the Y and X directions relative to the memory cell array with respect to the timing generation circuit; If the rule of arranging the phase comparison circuit at the far end in the X direction relative to the timing generation circuit with respect to the sense amplifier circuit is adopted, the clock signal for selecting a word line (φ1) and the sense amplifier activation signal (VDL) are generated. Timing generation circuit (9
Starting from 3), the operation delay time from the selection of the dummy word line to the change in the dummy data line and the operation delay time from when the sense amplifier activation signal (VDL) is transmitted to the farthest end of the transmission path are defined. The maximum can always be maximized for each layout according to the storage capacity, so that the design for automatically optimizing the sense amplifier activation timing according to the storage capacity or the layout configuration of the memory can be greatly facilitated. By satisfying the above layout rule, even when the type of memory is developed according to the storage capacity, the sense amplifier activation timing in the memories developed with different storage capacities can be optimally defined. At this time,
As described above, no special tuning is required in design to optimize the delay time. Automatically optimized.
This can contribute to shortening the design period of a semiconductor integrated circuit that is developed in accordance with the storage capacity.

[Brief description of the drawings]

FIG. 1 is a block diagram of an SRAM according to an example of the present invention.

FIG. 2 is a circuit diagram showing an example of the variable delay circuit.

FIG. 3 is a logic circuit diagram illustrating an example of a phase comparison circuit.

FIG. 4 is a circuit diagram showing an example of a dummy memory cell.

FIG. 5 is a timing chart showing an example of a relationship between a sense amplifier activation timing and a word line selection timing.

FIG. 6 is an explanatory diagram showing an example of a layout configuration of each unit when an SRAM is developed with a relatively large storage capacity.

FIG. 7 is an explanatory diagram showing an example of a layout configuration of each unit when an SRAM is developed with a minimum storage capacity.

8 is a timing chart showing a change timing of a sense amplifier activation timing signal with respect to a clock signal in a layout configuration having a large storage capacity corresponding to FIG. 6;

9 is a timing chart showing a change timing of a sense amplifier activation timing signal with respect to a clock signal in a layout configuration having a small storage capacity corresponding to FIG. 7;

FIG. 10 is a flowchart illustrating an example of a procedure of a design method when an SRAM is developed with a required storage capacity.

FIG. 11 is a block diagram illustrating an example of a microcomputer in which an SRAM is applied to a cache memory.

[Explanation of symbols]

 Reference Signs List 1 SRAM 2u memory cell array unit BL, BLb complementary data line WL word line 3u word driver circuit unit 4u column unit 5 memory cell 6 column switch circuit 7 sense amplifier circuit 8 output buffer circuit 9u control unit 11u dummy memory cell array unit 12u Dummy word line selection unit 13u Phase comparison unit 93 Timing generator CLK clock signal φ1 Word line selection clock signal φ2 Column selection clock signal φ3 Sense amplifier activation clock signal 94 Variable delay circuit 95 Counter 110 Dummy memory cell DBL, DBLb Dummy data line DWL Dummy word line 123 Dummy word line selection signal 201 Microcomputer 202 Central processing unit 204 Flash memory

Claims (7)

[Claims] A memory cell array having a plurality of memory cells each having a selection terminal connected to a word line and a data terminal connected to the data line; a word driver circuit for driving a word line of the memory cell array; A column switch circuit for selecting a data line of the memory cell array, a sense amplifier circuit for amplifying data of the data line selected by the column switch circuit, a word line selecting clock signal synchronized with a clock signal, and a sense amplifier activation A memory including a timing generating circuit for generating a clock signal for use in a semiconductor integrated circuit, comprising: a dummy memory cell whose selection timing is synchronized with the word line selection timing. Level of the data line synchronized with the data read operation from A dummy memory cell array that simulates the conversion timing on a dummy data line to which the dummy memory cell is connected; a dummy memory cell selection circuit that receives the word line selection clock signal to form a selection signal for the dummy memory cell; A timing compensation circuit for compensating a target timing of sense amplifier activation with respect to the word line selection timing, wherein the timing compensation circuit forms a sense amplifier activation signal by inputting the sense amplifier activation clock signal; A variable delay circuit, wherein the variable delay circuit activates the sense amplifier with respect to the sense amplifier activation clock signal based on an early or late of the sense amplifier activation signal with respect to a level change timing simulated on the dummy data line. Variable delay time of the The semiconductor integrated circuit according to claim. 2. The timing compensating circuit according to claim 1, wherein the timing compensating circuit is configured to detect whether the sense amplifier activation timing is earlier or later than a level change timing simulated on the dummy data line. And a counter that counts down / counts down, wherein the variable delay circuit changes the delay time of the sense amplifier activation signal in accordance with the count value of the counter. Item 2. The semiconductor integrated circuit according to item 1. 3. The timing generation circuit according to claim 1, wherein the dummy memory cell selection circuit is more Y than the word driver circuit.
A dummy memory cell arranged at a far end in the direction and receiving a dummy word line selection signal output from the dummy memory cell selection circuit is arranged at a far end in the Y direction and the X direction relative to the memory cell array with respect to the timing generation circuit; 3. The semiconductor integrated circuit according to claim 2, wherein the phase comparison circuit is arranged farther in the X direction than the sense amplifier circuit with respect to the timing generation circuit. 4. The memory cell according to claim 1, wherein said memory cell is a static memory cell.
A semiconductor integrated circuit according to the item. 5. The apparatus according to claim 1, further comprising a central processing unit for executing an instruction, wherein said central processing unit generates an address signal for addressing said memory. A semiconductor integrated circuit according to the item. 6. The method for designing a semiconductor integrated circuit according to claim 3, wherein the first processing determines a storage capacity of the memory and the number of data input / output bits, and the first processing determines the first processing. A memory cell array unit for configuring the memory cell array, a word driver circuit unit for configuring the word driver circuit, the column switch circuit and the sense, satisfying storage capacity and the number of data input / output bits; A method for designing a semiconductor integrated circuit, comprising: a column unit for forming an amplifier circuit; and a second process for determining a layout of the dummy memory cell array unit for forming the dummy memory cell array. . 7. The second process is performed by using previously designed design data of a memory cell array unit, a word driver circuit unit, a column unit, and a dummy memory cell array unit. The method for designing a semiconductor integrated circuit according to claim 6.