JPH11203200A - Parallel processor and memory control method - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To provide a parallel processor capable of exhibiting high operation performance. SOLUTION: Tag data indicating the necessity of write-back is stored in a tag data area 120 for each of subpages stored in subbanks 41 to 44. When the subpage requested by the processor element is not stored in the memory cell area 90, a plurality of addresses having continuous addresses including the requested subpage read from the main memory via the external access bus 26 are stored. And the banks 80 ₀ to 80 determined by referring to the tag data such that the number of sub-pages and sub-pages requiring write-back are reduced.
_Replace with the page stored in _m-1 .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a parallel processor in which a plurality of processor elements and a shared memory are connected via a common bus, a memory control method, and a processor.

[0002]

2. Description of the Related Art In a computer, in order to increase the data access speed of a processor element (PE), the processor element accesses only a high-speed memory. However, since a high-speed memory is expensive, a memory structure in which a high-speed small-capacity memory and a low-speed large-capacity memory are hierarchically constructed is employed. In such a memory structure, for example, a cache memory, a main memory, and a secondary storage medium are sequentially and hierarchically constructed, and by utilizing the locality of addresses in data access from the processor element, Data is transferred in units of predetermined lines or blocks (pages) between memories of different layers according to access requests. For example, data is transferred between the cache memory and the main memory in line units in response to an access request from the processor element, so that the data requested by the processor element exists in the cache memory with a high probability.

In such a cache memory, when data is accessed from a processor element, the cache memory refers to tag data for managing data in the main memory stored in the cache memory and includes the requested data. It is determined whether the line exists in the cache memory. In the cache memory, if a line containing requested data is not stored in the cache memory, for example, the line with the oldest access time among the lines stored in the cache memory is saved in the main memory. The line containing the requested data is read into the cache memory. Note that the cache memory manages data in line units for data transfer to and from the main memory, but generally the storage area itself is physically continuous.

For data transfer between a main memory and a secondary storage medium such as a hard disk, for example, a paging mechanism that divides and manages physical addresses into units called fixed-length pages is employed. In such a paging mechanism, conversion from a logical address to a physical address is performed using an address conversion table called a page table.

For example, in a page table of the associative memory system, a request for determining whether a requested page is stored in a main memory is determined by using a page address registered in the page table. Is compared with the page selector (identification number) of the page where there is, and the page selector of the registered page. Further, when a page requested by a processor element is paged in from the secondary storage medium to the main memory, invalid pages are taken out of a plurality of pages registered in the page table in consideration of the validity of those pages. Select a page and target it for page swapping. Then, the page requested by the processor element is read from the secondary storage medium and stored in the storage area where the selected page is stored.

If there is no invalid page in the pages registered in the page table, for example, among the pages registered in the page table, for example, the page with the oldest recent access is subjected to page replacement. And

In recent years, a parallel processor has been developed in which a plurality of instructions that can be executed simultaneously in a program are executed in parallel by a plurality of processor elements incorporated in one chip to reduce the execution time of the entire program. Have been done. Various architectures of such a parallel processor have been proposed. One of them is one in which a plurality of processor elements and a shared memory are connected to a set of a common bus (shared bus).

FIG. 15 is a system configuration diagram of a conventional general parallel processor 1. As shown in FIG. 15, the parallel processor 1, the common bus 2 in one chip, n pieces of processor elements 3 ₁ to 3 _n, the shared memory 4, and the bus unit 5 is incorporated, processor element 3 ₁ to common bus 2 To 3 _n , the shared memory 4 and the bus unit 5 are connected. In addition, the bus unit 5
Are connected to a main memory 7 via an external chip interface 6. In the memory cell area 4a of the shared memory 4, one data port I / O is provided. In the parallel processor 1, when the processor elements 3 _{1 to} 3 _n access data stored in the shared memory 4, data is transmitted via the common bus 2 and the data port I / O.

[0009]

However, in the above-described parallel processor 1, the processor elements 3 ₁ to 3 ₁
3 _n and data transfer between the data transfer and the common memory 4 and the main memory 7 between the shared memory 4 are both performed through the common bus 2, moreover, shared memory 4 memory cell region 4a is one since the data port I / O only equipped, for reasons described below, there is a problem of a high possibility that the waiting time of the processor element 3 ₁ to 3 _n is prolonged. That is, a page fault occurs in the shared memory 4, while performing the replacement of pages to and from the shared memory 4 and the main memory 7, since the common bus 2 is in use, the processor element 3 ₁ to 3 _n is Cannot access shared memory 4. Thus, access requests to the shared memory 4 from the processor element 3 ₁ to 3 _n is would have to wait until the page replacement process is completed, operation performance of the parallel processor 1 is decreased.

To solve such a problem, FIG.
As shown in (1), a plurality of data ports I / O (1) to I / O (k) may be provided in the memory cell area 4b of the shared memory 4. These data ports are connected to corresponding common buses 10, respectively. However, if a plurality of data ports are provided for the entire storage area of the shared memory 4, the area of the memory cell area 4 b greatly increases, and the memory area of the shared memory 4 is reduced due to the chip area required for the parallel processor 1. Memory capacity must be reduced. As a result, there is a problem that the shared memory 4 cannot have a sufficient memory capacity, the frequency of page faults increases, and the operation performance of the parallel processor 1 is reduced.

[0011] In the parallel processor 1, as access to the shared memory by the processor element 3 ₁ to 3 _n is not delayed, between the main memory 7 in response to the access request from the processor element and the shared memory 4 It is important to use the method of page replacement in the above. However, when a special memory structure is used for a parallel processor, it is not appropriate to use the data transfer method between layers adopted in the conventional memory hierarchy described above in order to obtain high computation performance. There is also. The same is true for a processor using a single processor element.

The present invention has been made in view of the above-mentioned problems of the prior art, and has a parallel processor capable of exhibiting high arithmetic performance.
It is an object to provide a memory control method and a processor.

[0013]

In order to solve the above-mentioned problems of the prior art and to achieve the above-mentioned object, the parallel processor of the present invention has an internal memory for storing one or more subpages. A plurality of processor elements that perform arithmetic processing using data stored in the internal memory, a main memory that stores a plurality of pages each including a plurality of subpages, and a shared memory that is accessed from the plurality of processor elements And Here, the shared memory is configured to read and store a partial page of the plurality of pages stored in the main memory, and to store a subpage stored in the first storage unit. For each of them, a second storage means for storing characteristic data indicating whether or not it is necessary to write back to the main memory, and a subpage requested by the processor element is stored in the first storage means. When there is no page, the page to be replaced is selected from the plurality of pages stored in the first storage means so that the number of subpages that need to be written back to the main memory is reduced. The processor page stored in the main memory is stored in the storage area of the first storage unit where the reference page is determined and the determined page is stored. And a control means for controlling to read out stored page containing the subpage has been requested from the instrument.

In the parallel processor of the present invention, when it is determined that the subpage including the necessary data is not stored in the internal memory during the operation processing by the processor element, the processor element transfers the data to the shared memory. The subpage is requested. If the control unit of the shared memory determines that the subpage requested by the processor element is not stored in any of the plurality of subbanks, the subpage is stored in the second storage unit. The page to be replaced is determined from the plurality of pages stored in the first storage means so that the number of subpages that need to be written back to the main memory is reduced with reference to the characteristic data. You. The control unit stores a page including a subpage requested by the processor element stored in the main memory in a storage area of the first storage unit in which the determined page is stored. It is controlled to read and store. Then, the requested subpage is transferred and stored from the first storage unit to the internal memory of the processor element that has issued the request. The data of the requested subpage is used for arithmetic processing by the processor element.

In the parallel processor according to the present invention, the control means of the shared memory determines whether the requested subpage is stored in the first storage means, and determines that the subpage is stored. If so, the requested subpage is transferred and stored from the first storage means to the internal memory of the requested processor element. The data of the requested subpage is used for arithmetic processing by the processor element.

Further, in the memory control method according to the first aspect of the present invention, a part of a plurality of pages each including a plurality of subpages stored in a main memory is accessed from a plurality of processor elements. A memory control method for storing in a shared memory, reading a subpage requested from an arbitrary processor element among the plurality of processor elements from the shared memory, and outputting the read subpage to the processor element that has issued the request, wherein the processor When a subpage requested by an element is not stored in the shared memory, a plurality of pages stored in the shared memory so that the number of subpages that need to be written back to the main memory is reduced. The page to be replaced from among the pages is stored in the shared memory. For each page determined by referring to the characteristic data indicating the presence or absence of a need for write-back to the main memory. Then, a page including a subpage requested by the processor element stored in the main memory is read and stored in a storage area of the shared memory in which the determined page is stored. Then, the requested subpage is read from the shared memory and output to the processor element that issued the request.

Further, the processor of the present invention has an internal memory for storing one or more subpages, and a single processor element for performing arithmetic processing using data stored in the internal memory, and a plurality of subelements. A main memory for storing a plurality of pages, and an intermediate memory accessed by the processor element; Here, the intermediate memory reads out and stores a part of the plurality of pages stored in the main memory, and a sub-page stored in the first storage unit. For each of them, a second storage means for storing characteristic data indicating whether or not it is necessary to write back to the main memory, and a subpage requested by the processor element is stored in the first storage means. When there is no page, the page to be replaced is selected from the plurality of pages stored in the first storage means so that the number of subpages that need to be written back to the main memory is reduced. The processor page stored in the main memory is stored in the storage area of the first storage unit where the reference page is determined and the determined page is stored. And a control means for controlling to read out stored page containing the subpage has been requested from the instrument.

The processor of the present invention is also applicable to a single processor element. In the processor of the present invention, when it is determined that the subpage including the necessary data is not stored in the internal memory while the arithmetic processing is being performed by the processor element, the subpage is stored in the intermediate memory from the processor element. Required. When the control unit of the intermediate memory determines that the subpage requested by the processor element is not stored in any of the plurality of subbanks, the subpage is stored in the second storage unit. The page to be replaced is determined from the plurality of pages stored in the first storage means so that the number of subpages that need to be written back to the main memory is reduced with reference to the characteristic data. You. Then, the first means in which the determined page is stored by the control means.
Is controlled so that a page including a subpage requested by the processor element stored in the main memory is read and stored in a storage area of the storage means. Then, the requested subpage is transferred and stored from the first storage unit to the internal memory of the processor element. The data of the requested subpage is used for arithmetic processing by the processor element.

Also, in the memory control method according to the second aspect of the present invention, a part of a plurality of pages each including a plurality of subpages stored in a main memory is stored in an intermediate memory, A memory control method for reading a requested subpage from the intermediate memory and outputting the read subpage to the processor element, wherein the subpage requested by the processor element is not stored in the intermediate memory. A page to be replaced is selected from among a plurality of pages stored in the intermediate memory so as to reduce the number of subpages that need to be written back to the memory for each of the subpages stored in the intermediate memory. A decision is made with reference to the characteristic data indicating whether or not it is necessary to write back to the main memory. To. Then, a page including a subpage requested by the processor element stored in the main memory is read and stored in a storage area of the intermediate memory in which the determined page is stored. Then, the requested subpage is read from the intermediate memory and output to the processor element.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a parallel processor, a processor and a memory control method according to an embodiment of the present invention will be described in detail. FIG. 1 is a system configuration diagram of the parallel processor 21 of the present embodiment. As shown in FIG.
Parallel processor 21 may be, for example, common bus 22, the processor element 23 ₁ ~ 23 _n as a first bus,
It has a shared memory 24, a bus unit 25, and an external access bus 26 as a second bus.

In the parallel processor 21, the common bus 22
The processor element 23 ₁ ~ 23 _n and the shared memory 24 is connected. External access bus 2
6, a shared memory 24 and a bus unit 25 are connected.

The common bus 22 has a bus width of 128 bits, and the external access bus 26 has a bus width of 32 bits. The common bus 22 has a data transfer speed four times or more that of the external access bus 26. The bus width of the common bus 22 and the external access bus 26 can be the same. The processor element 23 _1-2
3 _n indicates, for example, that the parallel processor 1 has a MIMD (Multipl
e Instruction Multiple Data) type parallel processors have individual program counters, and perform processing in accordance with instructions stored at addresses of instruction memory (not shown) indicated by the program counters independently of each other. . Processor element 23
₁ The ~ 23 _n, for example, RISC (Reduced Instr
A general-purpose processor of the auction set computer type is used.

The processor elements 23 ₁ to 23 _n are:
Each of a plurality of subpages, for example, subbanks 27 ₁ , 2 as internal memories capable of storing three subpages
And a 7 _2, 27 _3. Here, the subpage is 512-byte data stored in a storage area of a continuous address on the main memory 7, and one page is constituted by the subpages of four continuous addresses. Incidentally, the number of sub-banks by the processor element 23 ₁ ~ 23 _n are provided, it is also possible to mutually different. Processor elements 23 ₁ ~ 23 _n, as described later, is stored in the sub-banks 27 _{1-27 3} reads the sub-page from the shared memory 24, the processor element 23 ₁ ~ 23 _n each other and sub-bank 2
7 _1-27 can store subpage different pages among _three mutually. The bus unit 25 is connected to the main memory 7 via the chip interface 6 provided outside the parallel processor 21. Main memory 7 is 4G
It has a memory space with consecutive addresses of bytes.

FIG. 2 is a configuration diagram of the shared memory 24 shown in FIG. As shown in FIG. 2, the shared memory 24 includes, for example, a common bus control circuit 31 and an external bus control circuit 3.
2, control circuit 33, memory internal buses 51, 52, multiplexers (MUX) 53, 54, 55, 56, memory cell area 90 as first storage means, address decoders 57, 58, 59, 60, second It has a tag data area 120 and a request queue 125 as storage means.

In this embodiment, the control circuit 31 for the common bus, the control circuit 32 for the external bus, and the control circuit 33
Function as control means of the present invention. The control circuit 33
A control circuit 31 for a common bus, a control circuit 32 for an external bus,
Multiplexers 53-56, address decoders 57-6
Control 0. Further, the control circuit 33 determines whether if you enter a sub-page replacement request signal (access request) from the processor element 23 ₁ ~ 23 _n, sub-page there is a request are stored in the memory cell region 90 (page (The presence or absence of a hit) is determined by referring to the tag data as the characteristic data stored in the tag data area 120,
If it is determined that a page fault has occurred, a page to be paged in from the main memory 7 is replaced from a plurality of pages stored in the memory cell area 90 by a method described later with reference to FIG. Determine the target page. Further, the control circuit 33 to transfer from the first main memory 7 subpages there is a request from the processor element 23 ₁ ~ 23 _n to the shared memory 24,
The page transfer between the shared memory 24 and the main memory 7 is controlled.

The common bus control circuit 31 controls the transfer of subpage between the processor elements 23 ₁ ~ 23 _n and the memory sub-banks 41 to 44 through the memory internal bus 51 and common bus 22. More specifically, the common bus control circuit 31 controls the address decoders 57 to 60 by outputting a control signal S31 based on the control signal from the control circuit 33, and also controls the multiplexers 53 to 5.
4 is controlled.

The external bus control circuit 32 controls page transfer between the memory subbanks 41 to 44 and the main memory 7 via the memory internal bus 52 and the external access bus 26. Specifically, the external bus control circuit 32
Outputs a control signal S32 based on a control signal from the control circuit 33 to control the address decoders 57 to 60 and to control switching of the multiplexers 53 to 54.

The multiplexers 53 to 56 output control signals S
The memory sub-banks 41 to 44 are connected to one of the memory internal buses 51 and 52 based on the control signals from the control circuit 31 and S32 and the control circuit 33, respectively.

The address decoders 57 to 60 decode the control signals S31 and S32, and control access to the memory subbanks 41 to 44, respectively.

The memory cell area 90 is physically divided equally into four memory sub-banks 41 to 44. Each of the memory sub-banks 41 to 44 has a single data port. The memory cell area 90 is divided by _m banks 80 ₀ to 80 _m−1 so as to equally lie over the memory sub-banks 41 to 44, respectively. Each of the memory subbanks 41 to 44 has a storage capacity capable of storing, for example, m subpages. The subpage is, for example, image data.
The memory sub-banks 41 to 44 include multiplexers 53 to 56, a memory internal bus 51, and a common bus 2 respectively.
Through 2, between the processor elements 23 ₁ ~ 23 _n, transfer data sub-page basis. Here, the data transfer operation for writing data from the processor element 23 ₁ ~ 23 _n to the memory sub-banks 41 to 44, operation of reading data from the memory sub-banks 41 to 44 processor element 23 ₁ ~ 23 _n, and,
Both operations are included.

Since the common bus 22 has a bus width of 128 bits, in the bus operation via the common bus 22 in which the subpage is a unit of data transfer per transfer, to transfer a 512-byte subpage, 3 bytes are required.
At least two (= 512 × 8/128) bus transactions are required.

The memory subbanks 41 to 44 are connected to the respective banks 80 ₀ to 80 via multiplexers 53 to 56, a memory internal bus 52 and an external access bus 26.
Data is transferred to and from the main memory 7 in page units stored in _m-1 . Here, one page is 2 Kbytes and is composed of four subpages. Therefore, the start address of the sub-pages processor elements 23 ₁ ~ 23 _n is trying to access is, A address indicated in Fig. 3, (A + 5
12) Address, (A + 1024) address or (A + 15)
36) If the address is an address, one page of data stored at a continuous address of 2 Kbytes from address A is transferred from the main memory 7 to the shared memory 24, and this one page of data is transferred to four sub-addresses. Divided into pages, each bank 8
Store it in the range from ₀ to 80 _m . In the present embodiment, the 4 GB memory space of the main memory 7 is indicated by a 32-bit address. Here, of the 32-bit address, the 31st to 11th bits indicate the head address of the page, and the 10th to 0th bits indicate the address in the page. The 10th and 9th bits indicate the subbank.

The subpages stored in the memory subbanks 41 to 44 are stored in all the processor elements 23 ₁
It is desirable to unify the data amount of the subpages throughout the system so that the data can be shared by 23 _n . In the present embodiment, the memory capacity of the sub-banks 27 ₁ of the processor elements 23 ₁ ~ 23 _n to 512 bytes, the data amount of the sub-page is also 512 bytes. Here, since the external access bus 26 has a bus width of 32 bits, in a single bus operation via the external access bus 26 in which a page is a unit of data transfer, a 2K byte page is transferred. 512 (= 2048 × 8
/ 32) The minimum number of bus transactions is required.

As shown in FIG. 2, the tag data area 120 stores tag data as characteristic data of the subpage stored in the memory cell area 90 including the memory subbanks 41 to 44. The tag data area 120 includes tag banks 130 _{0 to} 13 corresponding to the banks 80 ₀ to 80 _m -1.
0 _m-1 and the tag banks 130 _{0 to} 130 _m-1 have:
Data indicating characteristics of the subpages stored in the banks 80 ₀ to 80 _m are stored. The tag data includes a valid identification area 121 and a daddy identification area 122.
And a page selector area 123.

The valid identification area 121 stores one valid bit indicating the validity of the data of each subpage.
It has as many subpages. For example, in the valid identification area 121, “1” indicating valid is set in a valid bit corresponding to a valid subpage, and “0” indicating invalid is set in a valid bit corresponding to an invalid (invalid) subpage. Is set.

The dirty identification area 122 has one dirty bit, which indicates whether or not the data of each subpage is dirty, by the number of subpages. Here, it is dirty, to the sub-page, when means that has been written from the processor element 23 ₁ ~ 23 _n, releases the storage area in which the sub-page is stored, the sub-page Must be written back to the main memory 7. That is, it is necessary to perform write back. For example, in the dirty identification area 122, a dirty bit corresponding to a dirty subpage is set to “1” indicating validity, and a dirty bit corresponding to a non-dirty subpage is set to “0” indicating invalidity. .

The page selector area 123 includes the bank 80
It has a page selector that indicates the page identification number (for example, the top address of the page) stored in ₀ to 80 _m .

Further, the request queue 125, the processor element 23 21 _to the to the shared memory 4 generated through the common bus 22 and a memory internal bus 51
If the access request from 3 _n conflict, accumulated access requests in a queue and processed in order.

Hereinafter, the operation of the parallel processor 21 will be described. FIG. 4 is a flowchart for explaining the operation of the parallel processor 21. Hereinafter, when there is access to the shared memory 24 from the processor element 23 ₁ ~ 23 _n, will be described with reference to FIG. 4 the operation of the parallel processor 21 of the case of the shared memory 24 is when a page miss you page hit . 6, 8, and 1.
0, bits irrelevant to the description of the present embodiment in the tag data shown in FIGS. 11 and 12 are blank. However, in the actual tag data, “1” or “0” is set in these blank bits.

[0040] In case of page hit [if the page replacement is not required] FIG 5, the bank 80 ₆ of the memory sub-banks 41 to 44 in the memory cell region 90, the sub-page 91 to 94 respectively are stored. Further, in FIG. 6, in the stored tag data to the tag data area 120, among the valid identification area 121 stored in Tagubanku 130 ₆ corresponding to the bank 80 _6, the valid bit for the memory sub-bank 42 is "1", That is, it indicates that it is valid (valid). In the case shown in FIGS. 5 and 6, for example, the processor element 23 _3, when the sub-page 92 that includes the address read request occurs is not stored in the sub-banks 27 _{1-27 3} processor element 23 ₃ , sub-page replacement request signal for the sub-page 92 is output to the shared memory 24 from the processor element 23 ₃ (step S1).

The control circuit 33 determines whether or not the subpage 92 indicated by the subpage replacement request signal is stored in the memory subbanks 41 to 44 by checking the page selector of the tag data stored in the tag data area 120. The determination is made with reference to the area 123 (step S
2). Specifically, the page selector of the subpage 92 indicated by the subpage replacement request signal and the tag bank 1
30 _0-130 and page selector page selector area 123 are all in the memory of the _m-1 are compared. Then, for example, when the page selector stored in the page selector and Tagubanku 130 ₆ subpage 92 matches the bank corresponds to Tagubanku 130 ₆ 8
0 ₆ subpages 92 there is the request is determined to be stored in. Also, it is determined from the ninth and tenth bits of the address of the subpage 92 indicated by the subpage replacement request signal that the subpage 92 is stored in the memory subbank 42.

Next, the control circuit 33 controls the tag bank 130 ₆ in the tag data valid identification area 121.
It is determined whether the valid bit of the memory sub-bank 42 is valid “1” or invalid “0” (step S3). At this time, as shown in FIG. 6, the valid bit of with sub-bank 42 of Tagubanku 130 ₆ is determined to be "1", that is, effective.

Next, according to the control from the control circuit 33,
The control signal S31 is output from the common bus control circuit 31 to the address decoder 58. Thus, for example, by the address decoder 58, the multiplexer 54 is connected to a memory internal bus 51, the sub-page 92 is transferred to the processor element 23 ₃ via a common bus 22. Subpages 92 processor element 23 ₃
It is stored, for example in the sub-banks 27 _1. Thereafter, the processor element 23 _3, from the sub-page 92 stored in the sub-banks 27 _1, read data at the address read request has occurred, calculation (image calculation) processing line using the read data (Step S4).

[0044] [If step S13 is executed] step S13, when the sub-page that is requested from the processor element 23 ₃ ~ 23 _n are have been stored in the shared memory 24, the sub-page is invalid Be executed. The control circuit 33, in step S3, when the valid bit for the memory sub-banks 42 of Tagubanku 130 ₆ in valid identification area 121 of the tag data is determined as "0", i.e. is invalid, the request from the processor element 23 ₃ page containing the subpage 92 there was is transferred and stored from the main memory 7 to the bank 80 ₆ in the memory cell region 90.

Next, according to the control from the control circuit 33,
The control signal S31 is output from the common bus control circuit 31 to the address decoder 58. Thus, for example, by the address decoder 58, the multiplexer 54 is connected to a memory internal bus 51, the sub-page 92 is transferred to the processor element 23 ₃ via a common bus 22. Subpages 92 processor element 23 ₃
It is stored, for example in the sub-banks 27 _1. Thereafter, the processor element 23 _3, from the sub-page 92 stored in the sub-banks 27 _1, read data at the address read request has occurred, processing is performed using the read data (step S4 ).

[0046] [If step S7 is executed] For a page fault step S7, the sub-page that is requested from the processor element 23 ₃ ~ 23 _n is not stored in the shared memory 24, the request is This is executed when there is one invalid subpage among the subpages already stored in the subbank storing the existing subpage.

[0047] In Figure 7, the bank 80 ₉ of the memory sub-banks 41 to 44 in the memory cell area 90, sub-page 201 to 204 respectively are stored. Further, in FIG. 8, among the valid bits stored in Tagubanku 130 ₉ corresponding to the tag data area 120 tag data definitive bank 80 ₉ stored in the valid bit is "0" for the memory sub-bank 42, i.e., It is invalid (invalid). Further, the valid bit for the memory sub-bank 42 stored in Tagubanku 130 ₉ non Tagubanku are all "1", i.e. is enabled (valid).

[0048] In the case shown in FIGS. 7 and 8, for example, the processor element 23 _3, sub-page including the address read request has occurred, it is stored in the sub-banks 27 _{1-27 3} built in the processor element 23 ₃ If not, a subpage replacement request signal for this subpage is output to the shared memory 24 (step S1). Then, the control circuit 33 determines whether or not the subpage indicated by the subpage replacement request signal is stored in the memory subbanks 41 to 44 with reference to the page selector area 123 of the tag data stored in the tag data area 120. Is determined (step S2). Specifically, the control circuit 33 compares the page selector of the subpage indicated by the subpage replacement request signal with the page selector of the page selector area 123, and determines the page selector of the subpage indicated by the subpage replacement request signal. And tag bank 130 ₀ -13
It is determined that the page selector stored at 0 _m-1 does not match. That is, the subpages indicated by the subpage replacement request signal correspond to the memory subbanks 41 to 44.
Is determined to be stored.

Next, in the control circuit 33, of the valid bits stored in the tag banks 130 _{0 to} 130 _m -1 in the tag data, the memory sub bank in which the sub page indicated by the sub page replacement request signal is stored is stored. A search is made for a bit whose valid bit is “0”, that is, indicates that it is invalid (step S5). Here, from the ninth and tenth bits of the address of the subpage indicated by the subpage replacement request signal, it is determined that the subpage is stored in the memory subbank 42,
In the valid identification area 121, the memory subbank 42
Are searched for those in which the valid bit for is invalid, that is, "0". As a result of this search, only the valid bit of the sub-banks 42 of Tagubanku 130 ₉ is determined to indicate an invalid (step S
6).

Next, according to the control from the control circuit 33,
The control signal S32 is output from the external bus control circuit 32 to the address decoder 58 (step S7). Thereby, for example, the multiplexer 54 is connected to the memory internal bus 52 by the address decoder 58, and the subpage 212 indicated by the subpage replacement request signal is read from the main memory 7 as shown in FIG. Via the bus 26 and the memory internal bus 52,
It is stored in the bank 80 ₉ of the memory sub-banks 42. Thus, as shown in FIG. 10, the valid bit corresponding to the memory sub-banks 42 of Tagubanku 130 ₉ is set to "1".

[0051] After the sub-page 212 is stored in the bank 80 ₉ sub-banks 42, the control of the control circuit 33, a control signal from the common bus control circuit 31 S31
Is output to the address decoder 58. This allows
For example, the multiplexer 54 is connected to the memory internal bus 51 by the address decoder 58, and the subpage 2
12 through a memory internal bus 51 and common bus 22, is transferred to the processor element 23 _3.

[0052] Further, since the data transfer between the shared memory 24 and the main memory 7 is a page unit, the sub-page 212 after being stored in the bank 80 ₉ sub-banks 42, other pages with subpages 212 Subpage 2
13, 214 and 211 are memory subbanks 4 respectively.
It is stored sequentially in the bank 80 ₉ 3,44,41. Note that the process of transferring subpage 212 from the memory sub-banks 42 in the processor element 23 ₃ via a common bus 22, the memory sub-banks 41 and 43 via the external access bus 26 subpages 211,213,214 from the main memory 7, The processing of transferring the data to the memory 44 and storing it is performed in parallel (multiplexing). Here, the control circuit 33
In the subpages 203, 204, and 201, the subpage in which the dirty bit of the dirty identification area 122 is valid is replaced after being written back to the main memory 7 (written back).

[0053] sub-page 212, when it is transferred to the processor element 23 ₃ via a common bus 22, is stored in the processor element 23 _3, for example, in the sub-banks 27 _1. Thereafter, the processor element 23 _3, the sub-page 212 stored in the sub-banks 27 _1, data of an address read request is generated are read, operation processing by using the read data is performed (step S4).

[When Step S10 is Executed] Here, the case where the storage state of the memory sub-banks 41 to 44 is shown in FIG. 9 and the tag data stored in the tag data area 120 is shown in FIG. 11 will be described. . in this case,
In steps S1, S2 and S5 shown in FIG. 4, the above-described processing is performed. However, as a result of the search in step S5 in the control circuit 33, it is determined that the valid bit in the tag data for the memory subbank 42 of the tag banks 130 ₆ , 130 ₉ , and 130 ₁₂ is “0”, that is, it indicates invalid (step S5). S6).

Next, in the control circuit 33, of the valid bits of the tag banks 130 ₆ , 130 ₉ , and 130 ₁₂ in the tag data, the sub page to be replaced next to the sub page indicated by the sub page replacement request signal is stored. Whether the valid bit for the memory sub-bank 43 is “0”, that is, indicates invalid, and whether the dirty bit for the memory sub-bank 43 is “0”, ie, indicates invalid. Is searched (step S8). In the example shown in FIG. 11, the tag banks 130 ₆ , 13 ₆
0 ₉ and 130 ₁₂ do not exist (step S9). Therefore, Tagubanku 130 _6, 130 _9, 130 ₁₂ bank 80 corresponding to _6, 80 _9, 80 ₁₂ of the pages stored in, be directed replace any page. For example, in such LRU scheme directed to replace the pages that are stored in the bank 80 _9.

[0056] Then, the sub-page shown in subpage replacement request signal from the processor element 23 ₃ is read from the main memory 7, the external access bus 26
And through a memory internal bus 52 and stored in the memory sub-bank 42 of the bank 80 ₉ (step S10).
Then, a control signal S 31 is output from the common bus control circuit 31 to the address decoder 58 in accordance with the control from the control circuit 33. Thus, for example, by the address decoder 58, the multiplexer 54 is connected to a memory internal bus 51, the sub-pages stored in the memory sub-bank 42 of the bank 80 ₉ via a memory internal bus 51 and common bus 22, the processor element 23
Transferred to ₃ . This subpage is stored in the processor element 23 _3, for example, in the sub-banks 27 _1. Thereafter, the processor element 23 _3, from the sub-pages stored in the sub-banks 27 _1, data of an address read request is generated are read out (step S
4).

At this time, the main memory 7 and the shared memory 2
Since the data transfer between the 4 is a page unit, the other three sub-pages of the page subpages a request belongs, is stored in the bank 80 ₉ of the memory sub-banks 41, 43, 44, respectively. Also, since the dirty bit corresponding to the memory sub-banks 43 of Dadi identification area 122 of the tag data stored in the Tagubanku 130 ₉ is "1", i.e. effective, are stored in the bank 80 ₉ of the memory sub-banks 43 the subpage was after write-back to main memory 7 stores a subpage corresponding from the main memory 7 to the bank 80 ₉ of the memory sub-banks 43. The memory sub-banks subpage stored in the memory sub-bank 42 of the bank 80 ₉ through a process of transferring the processor element 23 ₃ through the memory internal bus 51 and common bus 22, the external access bus 26 41, 43, 44 The sub-page transfer process and the write-back process between the memory and the main memory 7 are performed in parallel.

[Step S11 is executed] Here, the storage state of the memory sub-banks 41 to 44 is shown in FIG. 9, and the storage state of the tag data stored in the tag data area 120 is shown in FIG. Will be described.
In this case, steps S1, S2, S5 shown in FIG.
In S6 and S8, the above-described processing is performed. However,
If the result of the search at step S8, the valid bit stored in Tagubanku 130 ₉ in the tag data, the memory sub-banks 43 subpages replaced with the following sub-page indicated in the sub-page replacement request signal is performed are stored Is determined to be invalid. Also, the dirty bit stored in Tagubanku 130 ₁₂ in the tag data, the dirty bit for the memory sub-bank 43 is determined to be invalid. And the tag bank 13
0 _9, 130 ₁₂ bank 80 corresponding to _9, 80 ₁₂ of, the target is replaced pages stored in any bank. For example, the bank 80 ₉
Is a replacement target.

Next, sub-page shown in subpage replacement request signal from the processor element 23 ₃ is read from the main memory 7 through the external access bus 26 and a memory internal bus 52, the memory sub-banks of the bank 80 ₉ 42 (step S11). Then, a control signal S 31 is output from the common bus control circuit 31 to the address decoder 58 in accordance with the control from the control circuit 33. Thus, for example, by the address decoder 58, the multiplexer 54 is connected to a memory internal bus 51, the memory sub-banks 4 banks 80 ₉
2 is stored in the processor element 23 ₃ via the memory internal bus 51 and the common bus 22.
Is forwarded to This subpage is stored in the processor element 23 _3, for example, in the sub-banks 27 _1. Thereafter, the processor element 23 _3, from the sub-pages stored in the sub-banks 27 _1, data of an address read request is generated are read out (step S
4).

At this time, the main memory 7 and the shared memory 2
Since the data transfer between the 4 is a page unit, the other three sub-pages of the page subpages a request belongs, it is stored in order in the bank 80 ₉ of the memory sub-banks 43,44,41, respectively . Further, "0" valid bit corresponding to the memory sub-banks 43 of Tagubanku 130 ₉ in the tag data, that is, the disabled, the sub-page which has been stored in the bank 80 ₉ of the memory sub-banks 43 in the main memory 7 write without back, it stores the sub-pages corresponding from the main memory 7 to the bank 80 ₉ of the memory sub-banks 43. The memory sub-banks subpage stored in the memory sub-bank 42 of the bank 80 ₉ through a process of transferring the processor element 23 ₃ through the memory internal bus 51 and common bus 22, the external access bus 26 41,43,4
4 and the main memory 7 are performed in parallel with the subpage transfer process.

[0061] Search in step S5 by the control circuit 33 [step S12 may be selected] Results of back lid bits corresponding to the sub-banks subpages a request from the processor element 23 ₃ of the tag data is stored If all are “1”, that is, valid, all pages stored in the banks 80 ₀ to 80 _m are targeted, for example, by using the LRU method, etc. the replacement targeting, after the write-back to main memory 7 as needed, and transfers the page containing the subpage was from the processor element 23 ₃ of the request from the main memory 7 and stored in the memory cell region 90.

Multiple access Next, as shown in FIG.
In response to a read request from the _3, the sub-page 91-94, which is stored in the bank 80 ₁ of the shared memory 24, stored in the main memory 7 is transferred via the memory internal bus 52 and the external access bus 26 sub Pages 101-
While being replaced with 104, suspension page 11 stored from the processor element 23 ₄ other than the processor element 23 ₃ to the bank 80 ₆ of the shared memory 24
The process performed by the parallel processor 21 when a read request is issued to the second processor will be described.

[0063] In this case, the read request to the sub-page 112 is output to the shared memory 24 from the processor element 23 ₄ through the common bus 22, the common bus control circuit 31 the read request as the control signal S70 Is output. At this time, since the subpage 112 is stored in the memory subbank 42, the control signal S31 is output from the common bus control circuit 31 to the address decoder 58, and the multiplexer 54 is connected to the memory internal bus 51. As a result, the sub-page 112
But through a memory internal bus 51 and common bus 22, it is outputted to the processor element 23 _4.

[0064] In the parallel processor 21, in parallel with the transfer processing of the sub-page 112 as described above, the sub-page 101 to 104 stored in the sub-page 91-94 and the main memory 7 stored in the bank 80 ₁ of the shared memory 24 Is performed. That is, the parallel processor 21
In the process of transferring subpage between the shared memory 24 and the processor element 23 ₁ ~ 23 _n, and a page transfer processing between the shared memory 24 and the main memory 7 it can be multiplexed.

As described above, the parallel processor 21
According to the above, when a page fault occurs in the shared memory 24, as in steps S8 and S9 shown in FIG.
Other sub-banks subpage is stored by the processor elements 23 ₁ ~ 23 _n is requesting, by considering the valid bit and dirty bid sub-banks to be replaced subpage Following the sub-banks, the write-back The bank to be replaced with a page is determined so as to minimize the occurrence. Therefore, it is possible to reduce the probability of write-back occurs, the latency of the processor elements 23 ₁ ~ 23 _n by the write-back process is to shorten, can realize a high-performance computation processing.

In particular, like the parallel processor 21, the data transfer capability of the common bus 22 is four times the data transfer capability of the external access bus 26, and the memory cell area 90 is divided into four memory subbanks 41 to 44. In this case, the processing time involved in the write-back differs by a factor of four or more between the case of writing back one subpage and the case of writing back four subpages for one entire page.
Therefore, the time required for page replacement may differ by more than seven times depending on whether a page including many subpages requiring write-back is to be replaced or not. That is, like the parallel processor 21,
To the page number is small sub pages that need writeback subject to replacement pages, very in order to reduce latency associated with accessing the shared memory 24 by the processor element 23 ₁ ~ 23 _n It is effective.

In the parallel processor 21, when a page fault occurs in the shared memory 24, even if all the pages are not read from the main memory 7 to the shared memory 24, even when a necessary subpage is read. in the processor element 23 ₁ ~ 23 _n may access the loaded subpage. Therefore, the processor element 23 ₁ associated with a page fault
~ 23 _n latency can significantly reduce the, result, high speed processing is realized.

In the field of image processing and the like, data in the same page is stored in the processor elements 23 ₁ to 23 _1.
In many cases, access is continuously made from _n. However, in the case where a page fault occurs, in the parallel processor 21, in addition to the requested subpage, three other subpages having addresses continuous with the relevant subpage are provided. Page is also in main memory 7
To the shared memory 24, the possibility of a page fault occurring next time can be reduced. That is, a request from the characteristics of the image processing, the near future for the sub-pages of consecutive addresses and subpages a request, for access from the processor element 23 ₁ ~ 23 _n is likely to occur, these subpages Reading from the main memory 7 to the shared memory 24 together with the subpage where the error occurred is effective in reducing the future occurrence rate of page faults.

Further, according to the parallel processor 21, using the one having a data port singular as sub-bank of memory cells in the shared memory 24, the sub between the shared memory 24 and the processor element 23 ₁ ~ 23 _n Since the page transfer process and the page transfer process between the shared memory 24 and the main memory 7 can be performed in parallel,
High-speed processing can be realized. That is, the shared memory 24
Despite being a single port, it can functionally achieve substantially the same performance as a two port.

According to the parallel processor 21, FIG.
As shown in FIG. 16, the memory cell region 90 is physically divided into four memory sub-banks 41 to 44, and a single data port is provided in each of the memory sub-banks 41 to 44. Compared with the case where four data ports are provided for the entire memory cell region as in the memory 4, the number of wirings can be greatly reduced, and the memory cell region 90 can be downsized. As a result, it is possible to provide a memory cell area having a larger capacity than the conventional one in a limited area in the parallel processor 21.

The present invention is not limited to the above embodiment. For example, in the above embodiment, as shown in FIG. 1 has been described by way of parallel Purossa of connecting the n processor elements 23 ₁ ~ 23 _n to the common bus 22, the present invention is, for example, as shown in FIG. 14 , it can be applied to the processor 200 which connects the processor element 23 ₁ of the singular in the common bus 22. Processor 20 shown in FIG.
Even 0, similarly to the parallel processor 21 described above, at the request of the sub-page by the processor element 23 _1, the processing shown in FIG. 4 described above, the common bus 22
Processor element 23 ₁ and intermediate memory 20 via
4 and a page transfer between the intermediate memory 204 and the main memory 7 via the external access bus 26. Here, the intermediate memory 204
Has the same configuration as the shared memory 4 shown in FIG. According to the processor 200, by employing the data transfer process shown in FIG. 4, when a page fault occurs, the number of times that a page stored in the intermediate memory 204 is written back to the main memory 7 can be reduced, It can reduce the waiting time of the processor element 23 _1.

In the embodiment shown in FIG.
A case has been exemplified where the memory sub-banks 43 in the subsequent memory sub-banks 42 subpages there is a request from the processor element 23 ₃ is stored becomes the target of a replacement subpage, the memory sub-banks 41 in the subsequent memory sub-banks 42 Subpages may be replaced. In this case, step S8 shown in FIG.
In, among Tagubanku 130 ₉ and 130 _12,
The one in which at least one of the valid bit and the dirty bit corresponding to the memory sub-bank 41 is invalid is searched.

[0073] Further, in the above embodiment, in step S8 in FIG. 4, the memory sub-bank 43 to be replaced subpage to the next memory sub banks subpages there is a request from the processor element 23 ₃ is stored Although the case where the corresponding subpage is to be replaced has been exemplified, the valid bit corresponding to the memory subbank in which all or a part of other subpages included in the page belonging to the requested subpage are stored and Dirty bits may be considered.
At this time, for example, in consideration of the valid bit and the dirty bit corresponding to the memory subbank in which all the other subpages included in the page belonging to the requested subpage are stored, the valid bit and the dirty bit are considered. The bank in which at least one of the banks is invalid is set as a target of page replacement. According to the parallel processor 21, when determining the bank of the shared memory 24 that stores the page to be read from the main memory 7, all of the four subpages that constitute the page already stored in the bank are written back. By considering the necessity, it is possible to suppress the decrease in the memory access speed due to the write-back processing to about four times.

Further, in the above-described embodiment, in steps S11, S12, and S13 shown in FIG. 4, the bank to be replaced is determined by the LRU method, but the bank may be determined by another method.

[0075] Further, in the above embodiment, a case has been exemplified where the processor element 23 ₁ shown in the processor element 23 ₁ ~ 23 _n and 14 shown in FIG. 1 reads data from the sub-page, writes the data to the sub-page Even in this case, the subpage transfer processing via the common bus 22 and the page transfer processing via the external access bus 26 are the same.

In the above embodiment, the memory cell area of the shared memory 24 is divided into four memory subbanks 41 to 41.
Although the case of dividing into 44 is illustrated, the number of memory subbanks is arbitrary. Therefore, for example, the memory cell area of the shared memory 24 may be divided into eight memory sub-banks. In this case, one page is composed of eight subpages. In the above-described embodiment, the data amount of a single sub-page is set to 512 bytes. However, the data amount is not particularly limited, and may be 256 bytes or 1024 bytes.

The page replacement process between the shared memory 24 and the main memory 7 described with reference to FIG.
If the replacement process for the subpage 92 stored in the subbank 42 is performed first, then the subbank 4
Subpages 91, 93, 9 stored in 1, 43, 44
4 may be replaced with the main memory 7 in any order. For example, in the above-described embodiment, the subpages 93, 94, and 91 are replaced in the order of incrementing the address next to the requested subpage 92, but the subpages are replaced in the direction of decrementing the address. Sub-pages 91, 94, and 93 may be replaced in the order of 92.

In the page replacement process between the shared memory 24 and the main memory 7 described with reference to FIG. 13, the order of replacing the subpages 91 to 94 is 24 (= 4 × 3 × 2 × 1). ) There are streets. Therefore, in the parallel processor 21, the shared memory 24 and the main memory 7
The sub-pages may be replaced in any of these 24 ways. For example, without considering an access request from the processor element 23 ₁ ~ 23 _n, for example, may always replace subpage in the order of sub-pages 91, 92, 93, and 94.

[0079] Further, the present invention is, for example, to determine the operating mode of the processor elements 23 ₁ ~ 23 _n, the data access pattern of each processor element 23 ₁ ~ 23 _n is in either direction to increase and decrease the memory address It is also possible to provide a judgment circuit for judging whether or not there is. In this case, based on the determination result of the determination circuit, the order replacement subpage between the shared memory 24 and the main memory 7, the processor elements 23 ₁ to
As access latency of 23 _n becomes shorter, it can be configured to flexibly set. Here, as means for controlling the replacement order of the subpages in the shared memory 24, it is desirable to provide a programmable circuit such as a sequencer capable of flexibly changing the replacement order according to conditions, in addition to a fixed logic circuit. .

In the parallel processor 21 described above,
As shown in FIG. 2, the case where one set of the memory internal bus 51 and the common bus 22 is used is illustrated, but a plurality of sets of the memory internal bus 51 and the common bus 22 that are equal to or less than the number of memory subbanks may be provided. In this case, depending on the number of the set, at the same time allows access to a sub-bank of different shared memory 24 from the processor element 23 ₁ ~ 23 _n, can realize further high-speed processing.

[0081]

As described above, according to the parallel processor of the present invention, the waiting time when a plurality of processor elements access the shared memory can be reduced, and high operation performance can be realized. Further, according to the parallel processor of the present invention, the storage capacity of the first storage unit per unit area can be increased by dividing the first storage unit into a plurality of subbanks each having a single data port. Also,
According to the processor of the present invention, the waiting time when the processor element accesses the intermediate memory can be reduced,
High computing performance can be realized. Also, according to the processor of the present invention, the storage capacity of the first storage unit per unit area can be increased by dividing the first storage unit into a plurality of subbanks each having a single data port. Further, according to the memory control method of the first aspect of the present invention, the waiting time when the processor element accesses the shared memory can be reduced, and the processor element can achieve high arithmetic performance. According to the memory control method of the second aspect of the present invention, the waiting time when the processor element accesses the intermediate memory can be reduced,
It becomes possible to realize high operation performance in the processor element.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram of a parallel processor according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a shared memory shown in FIG. 1;

FIG. 3 is a diagram for explaining subpages stored in a memory subbank shown in FIG. 2;

FIG. 4 is a flowchart for explaining a process in a control circuit of a shared memory in the parallel processor shown in FIG. 1;

FIG. 5 is a diagram for explaining a storage state of a memory subbank.

FIG. 6 is a diagram for explaining a storage state of a tag bank when the page replacement of FIG. 4 is not performed;

FIG. 7 is a diagram for explaining a storage state of a memory subbank;

FIG. 7 is a diagram for explaining a storage state of a tag bank when the process of step S7 in FIG. 4 is performed.

FIG. 9 is a diagram for explaining a storage state of a memory sub-bank;

FIG. 10 is a diagram for explaining a storage state of the tag bank after the processing of step S7 of FIG. 4 is executed and the requested subpage is stored in the memory cell area from the main memory. .

FIG. 11 is a diagram for explaining a storage state of a tag bank when the process of step S10 in FIG. 4 is performed.

FIG. 12 is a diagram for explaining a storage state of a tag bank when the process of step S11 in FIG. 4 is performed.

FIG. 13 is a diagram for explaining a multiplexing process of the parallel processor illustrated in FIG. 1;

FIG. 14 is a system configuration diagram of a processor according to another embodiment of the present invention.

FIG. 15 is a system configuration diagram of a conventional general parallel processor.

FIG. 16 is a system configuration diagram of another conventional parallel processor.

[Explanation of symbols]

6 chip interface, 7 main memory, 22
Common bus, 23 ₁ ~23 _n ... processor element,
24 shared memory, 25 bus unit, 26 external access bus, 27 _{1 to} 27 ₃ , 41 to 44 sub bank, 31 control circuit for common bus, 32 control circuit for external bus, 33 control circuit, 53 to 56 multiplexer, 57-60 address decoder, 80 ₀ -80 _m
Bank: 120: Tag data area, 121: Valid identification area, 122: Dardy identification area, 123: Page selector area, 130 _{0 to} 130 _{m -1} : Tag bank, 20
4: Intermediate memory

Claims (34)

[Claims] An internal memory for storing one or a plurality of subpages, a plurality of processor elements for performing arithmetic processing using data stored in the internal memory, and a plurality of processor elements each comprising a plurality of subpages A main memory that stores a page; and a shared memory that is accessed from the plurality of processor elements. The shared memory reads and stores a part of the plurality of pages stored in the main memory. A first storage unit for storing, for each of the sub-pages stored in the first storage unit, a second storage unit for storing characteristic data indicating the necessity of writing back to the main memory; If the subpage requested by the processor element is not stored in the first storage means, Determining a page to be replaced from the plurality of pages stored in the first storage means with reference to the characteristic data so that the number of subpages that need to be written back to the memory is reduced, A control is performed such that a page including a subpage requested by the processor element stored in the main memory is read and stored in a storage area of the first storage unit in which the determined page is stored. A parallel processor having control means for performing 2. The control means stores, in a storage area of the first storage means in which the determined page is stored, a subpage requested by the processor element stored in the main memory. After reading and storing the containing page, control is performed such that a subpage requested by the processor element is read from the first storage means and stored in the internal memory of the processor element that has issued the request. 2. The parallel processor according to 1. 3. The control unit according to claim 1, wherein said subpage requested by said processor element is stored in said first storage unit, and said requested subpage is stored in said first storage unit. 2. The parallel processor according to claim 1, wherein the parallel processor is controlled to read and store in the internal memory of the processor element which has issued the request. 4. The control means stores, in a storage area of the first storage means in which the determined page is stored, a subpage requested by the processor element stored in the main memory. 2. The parallel processor according to claim 1, wherein when reading and storing a page including the sub-page, control is performed such that the requested sub-page is first read from the main memory and stored in the first storage unit. 3. 5. The parallel processor according to claim 1, wherein said first storage means can access at a higher speed than said main memory. 6. The parallel processor according to claim 1, wherein said first storage means has a storage area divided into a plurality of subbanks each having a data port, and stores one or a plurality of subpages in each subbank. . 7. A system according to claim 1, further comprising: a first bus connecting said plurality of processor elements to said first storage means; and a second bus connecting said first storage means to said main memory. 7. The parallel processor according to 6. 8. The first storage means includes storage areas each storing a single subpage of a plurality of different subbanks, and has a plurality of banks each storing a single page. 7. The parallel processor according to claim 6, wherein control is performed such that pages read from said main memory are stored in said first storage means in bank units. 9. The controller reads the requested subpage from the main memory when the subpage requested by the processor element is not stored in the first storage means. Referring to the characteristic data of the sub-page already stored in the sub-bank of the first storage unit in which the sub-page is to be stored, the sub-stored sub-bank of the plurality of banks of the first storage unit is referred to. 9. The parallel processor according to claim 8, wherein control is performed such that a page including the requested subpage is stored in a bank whose page does not need to be written back to the main memory. 10. The method according to claim 10, wherein the second storage unit stores, for each of the subpages stored in the first storage unit,
In addition to the data indicating the necessity of writing back to the main memory, specific data indicating the validity of the corresponding subpage is stored, and the control unit determines whether the subpage requested by the processor element is If not stored in the first storage means, reference is made to the characteristic data of the subpage already stored in the subbank of the first storage means for storing the requested subpage, Searching for a bank including a storage area in which the already stored subpage is not valid, and storing the page including the requested subpage in the searched bank when there is one such bank; A plurality of banks including a storage area in which the subpage stored in the subbank of the first storage unit that intends to store the requested subpage is invalid. In the case of standing,
Referring to the specific data, among the plurality of banks,
A subpage already stored in a subbank in which the requested subpage is to be stored is searched for a bank that does not need to be written back to the main memory, and the searched bank stores the requested subpage in the searched bank. 9. The parallel processor according to claim 8, wherein control is performed to store a page including a page. 11. A plurality of selection means provided corresponding to the sub-bank and connecting each of the sub-banks to a selected one of the first bus and the second bus, respectively. A parallel processor according to item 1. 12. The sub-page transferred between the first storage unit and the processor element and the sub-page transferred between the first storage unit and the main memory. Is different from the first storage means and the processor element,
And the sub-page transfer process between the first storage means and the main memory via the second bus is controlled in parallel. A parallel processor according to claim 7. 13. The parallel processor according to claim 7, wherein a data transfer rate of said first bus is equal to or faster than a data transfer rate of said second bus. 14. The parallel processor according to claim 6, wherein a single data port is provided in each sub-bank of the storage area of said first storage means. 15. The parallel processor according to claim 6, wherein a plurality of subbanks of said first storage means have the same storage capacity. 16. The parallel processor according to claim 6, wherein the number of subbanks in said first storage means is the same as the number of subpages constituting said page. 17. The parallel processor according to claim 1, wherein said internal memory of said processor element stores a plurality of subpages. 18. The parallel processor according to claim 1, wherein the plurality of subpages constituting the page have consecutive addresses in an address space of the main memory. 19. The parallel processor according to claim 1, wherein the data of the subpage is image data, and the plurality of processor elements perform image processing using the image data. 20. A part of a plurality of pages each consisting of a plurality of subpages stored in a main memory, stored in a shared memory accessed by a plurality of processor elements, and A memory control method for reading a subpage requested from an arbitrary processor element from the shared memory and outputting the read subpage to the processor element that issued the request, wherein the subpage requested from the processor element is stored in the shared memory. If not stored, the page to be replaced is selected from the plurality of pages stored in the shared memory so that the number of subpages that need to be written back to the main memory is reduced. The main memory for each of the sub-pages stored in The processor element stored in the main memory in a storage area of the shared memory in which the determined page is stored, in the storage area of the shared memory in which the determined page is stored. And reading and storing a page including the requested subpage from the shared memory, and reading the requested subpage from the shared memory and outputting the read subpage to the processor element that issued the request. 21. After reading and storing a page including a subpage requested by the processor element stored in the main memory into a storage area of the shared memory in which the determined page is stored, 21. The memory control method according to claim 20, wherein a subpage requested by the processor element is read from the shared memory and stored in the internal memory of the processor element that has issued the request. 22. When a subpage requested by the processor element is stored in the shared memory, the requested subpage is read from the shared memory, and the subpage of the processor element that issues the request is read. The memory control method according to claim 20, wherein the information is stored in an internal memory. 23. When reading and storing a page including a subpage requested by the processor element stored in the main memory, in a storage area of the shared memory storing the determined page. 21. The memory control method according to claim 20, wherein the requested subpage is first read from the main memory and stored in the shared memory. 24. The memory control method according to claim 20, wherein the shared memory can be accessed at a higher speed than the main memory. 25. The memory control method according to claim 20, wherein the storage area of the shared memory is divided into a plurality of subbanks each having a data port, and each subbank stores one or more subpages. 26. Transfer of a subpage between the plurality of processor elements and the shared memory via a first bus, and transfer between the shared memory and the main memory via a second bus. 3. A sub-page is transferred.
0. The memory control method according to 0. 27. The storage area of the shared memory is constituted by storage areas each storing a single subpage of a plurality of different subbanks, and is divided into a plurality of banks each storing a single page. 26. The memory control method according to claim 25, wherein the read page is stored in the shared memory for each bank. 28. When the subpage requested by the processor element is not stored in the shared memory, the subpage to be read from the main memory after the requested subpage is stored. Referring to the characteristic data of the sub-page already stored in the sub-bank of the shared memory, among the plurality of banks of the shared memory, the already-stored sub-page becomes the bank which does not need to be written back to the main memory. And storing a page including the requested subpage.
3. The memory control method according to 1. 29. The specific data includes, for each of the subpages stored in the shared memory, data indicating whether necessity of writing back to the main memory and validity of a corresponding subpage. If the sub-page requested by the processor element is not stored in the shared memory and contains the data indicating that the requested sub-page is already stored in the sub-bank of the shared memory in which the requested sub-page is to be stored. With reference to the characteristic data of the subpage, a search is made for a bank including a storage area where the already stored subpage is not valid.
If there is one, a page including the requested subpage is stored in the searched bank, and a subpage stored in a subbank of the shared memory in which the requested subpage is to be stored. When there are a plurality of banks including a storage area that is not valid, referring to the specific data, a sub-bank already stored in a sub-bank in which the requested sub-page is to be stored among the plurality of banks is referred to. 28. The memory control method according to claim 27, wherein a page is searched for a bank that does not need to be written back to the main memory, and a page including the requested subpage is stored in the searched bank. 30. When a subpage transferred between the shared memory and the processor element is different from a subpage transferred between the shared memory and the main memory, the shared memory and the Sub-page transfer processing via the first bus with the processor element and sub-page transfer processing via the second bus between the shared memory and the main memory are performed in parallel. 21. The memory control method according to claim 20, wherein the memory control method is performed. 31. The memory control method according to claim 20, wherein the plurality of subpages constituting the page have continuous addresses in an address space of the main memory. 32. The memory control method according to claim 20, wherein the data of the sub-page is image data, and the plurality of processor elements perform image processing using the image data. 33. An internal memory for storing one or more subpages, a single processor element for performing arithmetic processing using data stored in the internal memory, and a plurality of pages each comprising a plurality of subpages And a middle memory accessed from the processor element, wherein the middle memory reads and stores a part of the plurality of pages stored in the main memory. A second storage unit that stores, for each of the sub-pages stored in the first storage unit, characteristic data indicating whether writing back to the main memory is necessary, the processor element When the subpage requested by the user is not stored in the first storage means, A page to be replaced is determined from the plurality of pages stored in the first storage unit with reference to the characteristic data so that the number of subpages requiring rewriting is reduced. Control means for reading and storing a page including a subpage requested by the processor element stored in the main memory in a storage area of the first storage means in which the read page is stored. And a processor comprising: 34. A part of a plurality of pages each consisting of a plurality of subpages stored in a main memory is stored in an intermediate memory, and a subpage requested by a processor element is read from the intermediate memory. A memory control method for outputting to the processor element, wherein when a subpage requested by the processor element is not stored in the intermediate memory, the number of subpages that need to be written back to the main memory is In order to reduce the number of pages to be replaced from among the plurality of pages stored in the intermediate memory, it is determined whether or not it is necessary to write back to the main memory for each of the subpages stored in the intermediate memory. Is determined with reference to the characteristic data shown, and the determined page is stored. In the storage area of the intermediate memory, a page including a subpage requested by the processor element stored in the main memory is read and stored, and the requested subpage is read from the intermediate memory to read the page. A memory control method for outputting to a processor element.