JPH08330355A - Semiconductor device - Google Patents

Abstract

PURPOSE: To provide a semiconductor device of simple structure which can be manufactured easily at low cost. CONSTITUTION: An anisotropic conductive sheet 38 is arranged on the passivation film 34 of a semiconductor chip 32, a wiring pattern 40 is formed on the anisotropic conductive sheet 38, and the wiring pattern 40, the semiconductor chip 32 and an electrode 36 have an electric continuity by applying pressure to the anisotropic conductive sheet 38. An electric insulating film 42 is formed on the anisotropic conductive sheet 38 and the wiring pattern 40 by exposing the outer connection terminal junction part 40a of the wiring pattern 40, and an outer connection terminal 46 is formed on the exposed outer connection terminal junction part 40a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip size semiconductor device.

[0002]

2. Description of the Related Art There is a strong demand for miniaturization of a semiconductor device having a semiconductor chip mounted thereon in order to increase its packaging density. The miniaturization of this semiconductor device is nothing but the miniaturization of the package enclosing the semiconductor chip. In order to meet this demand, a CSP type, that is, a chip size package has recently appeared. There are various types of CSP,
FIG. 19 shows an example thereof. Reference numeral 10 is a semiconductor chip, and 12 is a ceramic substrate. The ceramic substrate 12 is formed to have substantially the same size as the semiconductor chip 10. A wiring pattern 14 is formed on the ceramic substrate 12, and the wiring pattern 14 is connected via a via 16 to a land (external terminal) 18 formed on the lower surface side of the ceramic substrate 12 in a required arrangement. The semiconductor chip 10 has Au bumps 20 and AgPd.
It is connected to the wiring pattern 14 via the paste 22, and the resin 24 is sealed in the gap between the semiconductor chip 10 and the ceramic substrate 12.

[0003]

According to the above semiconductor device, downsizing can be achieved, but since the ceramic substrate 10 and the Au bumps 20 are used, it becomes expensive.
Therefore, the present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device which has a simple structure, is easy to manufacture, and is inexpensive.

[0004]

The present invention has the following constitution in order to achieve the above object. That is, the other surface of the anisotropic conductive sheet having a wiring pattern formed on one surface is fixed to the surface of the semiconductor chip on which the passivation film is formed, and the wiring pattern and the electrodes of the semiconductor chip have the anisotropic shape. It is electrically connected through a conductive sheet, the external connection terminal joint of the wiring pattern is exposed to form an electrically insulating film, and the external connection terminal is formed at the external connection terminal joint. Is characterized by. The anisotropic conductive sheet can be electrically connected by pressing with the wiring pattern. Alternatively, bumps protruding outward from the passivation film may be formed on the electrodes of the semiconductor chip, and the anisotropic conductive sheet may be pressed by the bumps for electrical connection. This is advantageous because the wiring pattern can be kept substantially flat.

Further, according to the present invention, a plurality of anisotropic conductive sheets each having a wiring pattern formed on one surface thereof are laminated and fixed, and a passivation film is formed on the other surface of the lowermost anisotropic conductive sheet. Fixed to the surface of the semiconductor chip,
External connection between the wiring patterns and between the wiring patterns and the electrodes of the semiconductor chip are electrically connected via the anisotropic conductive sheet, and the wiring patterns formed on the uppermost anisotropic conductive sheet are externally connected. The terminal joint portion is exposed to form an electrically insulating film, and the external connection terminal joint portion is formed with an external connection terminal. The anisotropic conductive sheet can be electrically connected by pressing with the wiring pattern.

Alternatively, bumps projecting outward from the passivation film are formed on the electrodes of the semiconductor chip, and bumps are also formed on the wiring pattern formed on the anisotropic conductive sheet as an inner layer. By pressing the anisotropic conductive sheet, electrical connection can be established. Further, in this case, either of the wiring patterns can be formed as a solid pattern for power supply or grounding. When the solid pattern for the power supply is used, it is easy to route the power supply line, and when the solid pattern for grounding is used, a so-called decoupling capacitor can be formed and the electrical characteristics can be improved.

Further, in each of the above cases, a plurality of semiconductor chips are connected, the common anisotropic conductive sheet is fixed to the plurality of semiconductor chips, and the required electrodes of the plurality of semiconductor chips are connected by the wiring pattern. Electrically connected,
By forming the common electric insulation film on the wiring pattern of the uppermost layer, a multi-chip module can be formed in a chip size. Further, in each of the above cases, the electrically insulating film can be formed of a photosensitive solder resist film, and in this case, the external connection terminal joint portion of the wiring pattern can be easily exposed by photolithography. The external connection terminals formed on the external connection terminal joints may be formed on the bumps to form a BGA type semiconductor device.

Further, in the semiconductor device according to the present invention, the one surface of the insulating sheet having the wiring pattern formed on the one surface is provided on the semiconductor chip surface having the passivation film via the anisotropic conductive sheet. The wiring pattern and the electrode of the semiconductor chip are fixed and electrically connected to each other through the anisotropic conductive sheet, and a through hole is provided in the insulating sheet to bond an external connection terminal of the wiring pattern. The external connection terminal is formed at the external connection terminal joining portion. Further, a plurality of insulating sheets each having a wiring pattern formed on one surface thereof are laminated and fixed, and the one surface of the lowermost insulating sheet is anisotropic on the semiconductor chip surface on which the passivation film is formed. The wiring patterns are fixed to each other via a conductive sheet, and the wiring patterns and the electrodes of the semiconductor chip are electrically connected to each other. The connection terminal joint portion is exposed, and the external connection terminal is formed on the external connection terminal joint portion.

Any of the above wiring patterns can be formed into a solid pattern for power supply or grounding. When the solid pattern for the power supply is used, it is easy to route the power supply line, and when the solid pattern for grounding is used, a so-called decoupling capacitor can be formed and the electrical characteristics can be improved. Further, bumps protruding outward from the passivation film may be formed on the electrodes of the semiconductor chip, and the bumps may press the anisotropic conductive sheet for electrical connection. A BGA type semiconductor device can be formed by using bumps as the external connection terminals formed in the external connection terminal joint portion.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 shows a cross-sectional view of the semiconductor device 30. 32 is a semiconductor chip, 34 is Si
A passivation film made of O ₂ or the like, and 36 is an Al pad (pad portion) which is an electrode built in the semiconductor chip 32. The passivation film 34 is formed on the Al pad 36.
Is not formed and the Al pad 36 is exposed. A large number of Al pads 36 are formed on the semiconductor chip 32 in a required pattern. An anisotropic conductive sheet 38 is formed so as to cover the passivation film 34. The anisotropic conductive sheet 38 has a conductive filler 39 (FIG. 2) such as metal powder mixed in a resin, and by applying pressure, the conductive fillers 39 are continuous in the pressing direction and have conductivity in the pressing direction. It happens.

A wiring pattern 40 is formed on the anisotropic conductive sheet 38 in a required pattern. As shown in FIG. 2, the wiring pattern 40 is pressed so as to bite into the anisotropic conductive sheet 38, whereby the anisotropic conductive sheet 38 at the site is pressed, and the anisotropic conductive sheet 3 at the site is pressed.
8 is conducted, and the Al pad 36 and the wiring pattern 40 are electrically connected. The wiring pattern 40 is formed by adhering a metal foil such as a copper foil on the anisotropic conductive sheet 38 and etching the metal foil into a required pattern. Alternatively, a metal foil such as copper or aluminum is formed by sputtering or the like,
It may be etched to form a pattern. Reference numeral 42 denotes a photosensitive resist film (electrically insulating film), which is formed so as to cover the anisotropic conductive sheet 38 and the wiring pattern 40. The photosensitive resist film 42 is a protective film for the wiring pattern 40, and photosensitive solder resists made of various materials can be used.

Each wiring pattern 4 of the photosensitive resist film 42
For example, the photosensitive resist film 4 is provided at an appropriate portion corresponding to 0.
The through holes 44 are formed in a matrix arrangement on the wiring pattern 2 (wiring pattern 4 exposed by the through holes 44).
The 0 portion is the external connection terminal joint portion 40a). Reference numeral 46 denotes a bump which is an external connection terminal, is disposed by being electrically connected to each external connection terminal bonding portion 40a through each through hole 44, and is projected on the photosensitive resist film 42 to be formed as an external connection terminal. . The bumps 46 can be formed into ball bumps such as solder balls as shown in the drawing, but can also be formed into a flat land shape or another shape. Alternatively, lead pins may be connected to serve as external connection terminals. The bumps may be formed by plating such as nickel / gold plating. Reference numeral 48 denotes a protective film, which is formed so as to cover the side walls of the semiconductor chip 32, the passivation film 34, and the anisotropic conductive sheet 38,
Prevents ingress of moisture from the boundary of each layer. Protective film 48
Can be formed using a resist such as a resin made of an appropriate material, but it is not always necessary to provide it. Further, instead of the protective film 48, a frame body made of metal or the like may be fixed.

Since it is formed as described above, it can be formed in the semiconductor device 30 having the same size as the semiconductor chip 32.
Further, since the anisotropic conductive sheet 38 and the photosensitive resist film 42 which will be the interposer can be thinly formed, the thin semiconductor device 30 can be formed. Since the anisotropic conductive sheet 38 and the photosensitive resist film 42 are not so high in hardness,
It also functions as a buffer layer that protects the surface of the semiconductor chip 32. It is preferable that the opposite surface of the semiconductor chip 32 is exposed to enhance heat dissipation. Further, in order to improve heat dissipation, a heat sink or heat spreader (not shown) may be fixed.

FIG. 3 shows another embodiment. In the present embodiment, the bumps 37 are provided on the Al pads 36 of the semiconductor chip 32 so as to be projected higher than the passivation film 34 by Au, for example, and are projected when the anisotropic conductive sheet 38 is fixed onto the passivation film 34. The anisotropic conductive sheet 38 is pressed by the bumps 37 so that the anisotropic conductive sheet 38 in that portion is brought into conduction and the Al pad 36 and the wiring pattern 4 are connected.
0 is electrically connected. Other parts of this embodiment are the same as those of the embodiment shown in FIG. Also in this embodiment, the same effect as described above is obtained. Further, in the present embodiment, the wiring pattern 40 can be formed substantially flat, which is advantageous when stacking layers.

FIGS. 4 and 5 show manufacturing steps for manufacturing the semiconductor device 30 shown in FIG. As shown in FIG. 4, a metal foil such as a copper foil is attached to the anisotropic conductive sheet 38, and the metal foil is etched by a known photolithography process to form a wiring pattern 40. Alternatively, the wiring pattern 40 may be formed by forming a metal layer by sputtering and etching the metal layer. As shown in FIG. 5, the anisotropic conductive sheet 38 on which the wiring pattern 40 is formed is positioned and arranged on the passivation film 34 of the semiconductor chip 32 so that the wiring pattern 40 overlaps the corresponding Al pad 36. Then, the wiring pattern 40 and the anisotropic conductive sheet 38 are pressed and heated by using the crimping jig 43 in which the pressing protrusions 41 are formed according to the arrangement pattern of the Al pads 36, and the anisotropic conductive sheet 38 is heated.
Is thermocompression bonded onto the passivation film 34. At that time, the wiring pattern 40 is pressed by the pressing protrusions 41 to be deformed into the state shown in FIG. 2, and the anisotropic conductive sheet 38 in this portion is pressed to contact with the Al pad 36 and conduct with each other. The Al pad 36 is electrically connected.

Next, in order to form the electrically insulating film 42, a photosensitive resist (photosensitive solder resist) is applied on the anisotropic conductive sheet 38 and the wiring pattern 40, exposed and developed to form the through holes 44. Form. The electrically insulating film 42 may be formed on the anisotropic conductive sheet 38 and the wiring pattern 40 in advance, and then the anisotropic conductive sheet 38 may be fixed on the semiconductor chip 32. Solder balls (bumps 46) are arranged in the through holes 44 and reflowed to fix the solder balls on the wiring pattern 40. The semiconductor device 30 can be completed as described above. If necessary, a resist is applied to the side wall of the semiconductor device 30 and dried to form the protective film 48.

In the above embodiment, the semiconductor chip 32 is used as an individual piece, but a wafer having a large number of semiconductor chips 32 built therein may be used. Then, in the same manner as above, the anisotropic conductive sheet 38, the wiring pattern 40, and
By forming the photosensitive resist film 42 and the bumps 46 and then slicing them into individual pieces, a large number of semiconductor devices 30 can be formed at one time, and the cost can be reduced. In addition, the wiring pattern 40 is the anisotropic conductive sheet 3
It may be formed after fixing 8 to the semiconductor chip 32.

Next, the semiconductor device 3 of the embodiment shown in FIG.
A method for producing 0 will be described. First, the Al of the semiconductor chip 32
Gold bumps 37 may be previously formed on the pads 36, and an anisotropic conductive sheet 38 having a wiring pattern 40 shown in FIG. 4 may be placed on the gold bumps 37 and thermocompression bonded. In this case, it is not necessary to use the crimping jig 43 having the pressing protrusions 41 as shown in FIG. That is, by pressing the anisotropic conductive sheet 38 as a whole during thermocompression bonding, the gold bumps 37 bite into the anisotropic conductive sheet 38, thereby pressing the anisotropic conductive sheet 38 at that portion. It will be conducted and will be conducted. The photosensitive resist film 42 and the bumps 46 can be formed in the same manner as in the above embodiment. The wiring pattern 40 may be formed after the anisotropic conductive sheet 38 is thermocompression bonded. The electrically insulating film 42 is formed on the anisotropic conductive sheet 38 and the wiring pattern 40 in advance, and then the anisotropic conductive sheet 38 is formed on the semiconductor chip 3.
It may be fixed on the surface 2.

FIG. 6 shows still another embodiment of the semiconductor device 30. In this embodiment, a plurality of semiconductor chips 32
Is mounted on a common substrate 47 such as a heat spreader, and a common anisotropic conductive sheet 38 is formed on the plurality of semiconductor chips 32 in the same manner as described above.
8 each wiring pattern 4 corresponding to each semiconductor chip 32
0 and a wiring pattern 45 for connecting between the required electrodes 36 for electrically connecting the adjacent semiconductor chips 32.
Are formed in the same manner as in the above-mentioned embodiment, a common electric insulating film 42 is formed thereon in the same manner as described above, and the bumps 4 are formed on the external connection terminal joints 40a of the wiring patterns 40.
6 is formed. That is, it is formed in one semiconductor device (multichip module) 30 using a plurality of semiconductor chips 32. As the plurality of semiconductor chips 32, for example, an MPU, a cache memory, and a plurality of memories can be connected. In the present embodiment, since a plurality of semiconductor chips are mounted on the common substrate 47 and the electrodes are electrically connected by the wiring pattern, the wiring can be shortened and the electrical characteristics such as signal delay prevention are excellent. A semiconductor device can be provided. In addition, manufacturing is facilitated by forming the anisotropic conductive sheet and the electrically insulating film in common. If the plurality of semiconductor chips 32 are held by a common frame (not shown), the substrate 47 is unnecessary. Alternatively, a plurality of semiconductor chips can be formed on a common wafer. The semiconductor device 30 of the present embodiment can also be manufactured by the same steps as described above.

FIG. 7 shows still another embodiment of the semiconductor device 30. The same members as those in the above embodiment are designated by the same reference numerals. In this embodiment, the anisotropic conductive sheets 38 formed on the upper surface of the semiconductor chip 32 are formed in multiple layers (two layers in the embodiment). The anisotropic conductive sheet 38 of the first layer is used for the semiconductor chip 3 as in the embodiment shown in FIG.
The wiring pattern 40 and the Al pad 36 are electrically connected to each other by being pressed by the bump 37 formed of Au or the like on the second Al pad 36. Similarly, the anisotropic conductive sheet 38 of the second layer is pressed by the bumps 37 formed at appropriate positions of the wiring pattern 40 of the first layer to electrically connect the wiring patterns 40 of the first layer and the second layer. I am trying to establish continuity. Reference numeral 42 denotes a photosensitive resist film (electrically insulating film), which is formed so as to cover the anisotropic conductive sheet 38 and the wiring pattern 40. The photosensitive resist film 42 is a protective film for the wiring pattern 40, and photosensitive solder resists made of various materials can be used.

Each wiring pattern 4 of the photosensitive resist film 42
For example, the photosensitive resist film 4 is provided at an appropriate portion corresponding to 0.
The through holes 44 are formed in a matrix arrangement on the wiring pattern 2 (wiring pattern 4 exposed by the through holes 44).
The 0 portion is the external connection terminal joint portion 40a). Reference numeral 46 denotes a bump which is an external connection terminal, is disposed by being electrically connected to each external connection terminal bonding portion 40a through each through hole 44, and is projected on the photosensitive resist film 42 to be formed as an external connection terminal. . The bumps 46 can be formed into ball bumps such as solder balls as shown in the drawing, but can also be formed into a flat land shape or another shape. Alternatively, lead pins may be connected to serve as external connection terminals. Note that, also in the present embodiment, between the wiring patterns 40 and between the wiring patterns 4
The connection between 0 and the Al pad 36 may be made by pressing the wiring pattern 40 as shown in FIG.

Also in this embodiment, the semiconductor chip 3 is used.
It is possible to form the semiconductor device 30 having the same size as 2. Further, since the anisotropic conductive sheet 38 and the photosensitive resist film 42 which will be the interposer can be formed thin, the thin semiconductor device 3 can be formed.
Can be formed to 0. Since the anisotropic conductive sheet 38 and the photosensitive resist film 42 have not so high hardness, they also function as a buffer layer for protecting the surface of the semiconductor chip 32. It is preferable that the opposite surface of the semiconductor chip 32 is exposed to enhance heat dissipation. Further, in order to improve heat dissipation, a heat sink or heat spreader (not shown) may be fixed.

FIG. 8 shows another embodiment in which the anisotropic conductive sheets 38 are provided in multiple layers. In this embodiment, one of the wiring patterns 40, which is an intermediate layer, is formed as a solid pattern 40b for power supply or grounding.
As shown in the figure, the upper wiring pattern 40 and the Al pad 36 of the semiconductor chip 32 are connected to each other by the bump 37 and the Al provided on the pattern 40c which is independent of the solid pattern 40b by providing a ring-shaped through hole in the solid pattern 42b. Pad 3
It is also possible to connect via bumps 37 formed in 6. Alternatively, it is also possible to simply provide a through hole in the solid pattern 40b and press the wiring pattern 40 in the upper layer so as to connect via the anisotropic conductive sheets 38, 38. The connection between the Al pad for power supply or ground and the solid pattern 40b and the connection between the solid pattern 40b and the necessary portion of the wiring pattern 40 in the upper layer also press the bumps 37 or the wiring patterns 40, 40b in the same manner as above. You can do it. When the solid pattern 40b is used as a solid pattern for power supply, the wiring of the power supply line of the upper wiring pattern 40 or the arrangement of Al pads for power supply can be freely and easily performed. In addition to improving the degree of freedom, a so-called decoupling capacitor can be formed on the solid pattern by sputtering or the like, and the electrical characteristics can be improved. Further, an element such as a resistor may be formed by sputtering or the like.

9 and 10 show still another embodiment. Reference numeral 41 is an insulating sheet made of polyimide, epoxy, polyester or the like, and a wiring pattern 40 is formed on one surface of the insulating sheet with copper foil or the like. A through hole 44 is formed in the insulating sheet 41 at a portion of the wiring pattern 40 that will be the external connection terminal bonding portion 40a, and the external connection terminal bonding portion 40a is exposed (FIG. 9). Reference numeral 38 is an anisotropic conductive sheet containing a conductive filler such as metal powder as described above. Further, 37 is a bump formed on the Al pad of the semiconductor chip 32. In the present embodiment, the semiconductor chip 3 with the one surface of the insulating sheet 41 on which the wiring pattern 40 is formed facing the anisotropic conductive sheet 38 side.
2. The anisotropic conductive sheet 38 and the insulating sheet 41 are laminated and pressed to be integrated. By this, the anisotropic conductive sheet 38 is pressed by the bumps 37, and the wiring pattern 40 and the Al pad at that portion are electrically connected. Bumps 46 serving as external connection terminals are formed in the through holes 44 to complete the semiconductor device 30. The bumps 37 may be formed on the wiring pattern 40 side. Also in this embodiment, a chip-sized semiconductor device can be easily formed. The connection between the wiring pattern 40 and the Al pad can be easily made through the anisotropic conductive sheet 38. FIG. 11 shows the wiring pattern 4
An embodiment is shown in which the insulating sheets 41 provided with 0 are provided in multiple layers on the semiconductor chip 32. Bonding between the insulating sheets 41 is performed by an adhesive 43, and the wiring pattern 40,
The electrical connection between the 40 is connected by a via 45. The lowermost insulating sheet 41 is fixed and electrically connected through the anisotropic conductive sheet 38 in the same manner as described above. Also in this embodiment, the intermediate wiring pattern may be provided in the pattern for the power supply or the ground.

Although the wiring pattern 40 is formed of a metal foil such as a copper foil in each of the above-mentioned embodiments, the anisotropic conductive sheet 38 is pressed in advance to the shape of the wiring pattern 40 by a press or the like to press the pressed portion. It is also possible to use the one having conductivity as it is. By doing so, the process can be shortened and the cost can be further reduced. The wiring pattern in the present invention includes the case where the anisotropic conductive sheet is formed by pressing.

FIG. 12 shows an anisotropic conductive sheet 50 with a conductor layer used in the semiconductor device of the present invention. The anisotropic conductive sheet 50 with a conductor layer is formed by forming a conductor layer 54 such as a copper foil on the surface of an anisotropic conductive sheet 52. The anisotropic conductive sheet 52 is made by mixing a resin such as epoxy, polyimide, or silicone with a conductive filler such as metal powder. Since the silicone resin has rubber-like elasticity, stress generated between the semiconductor chip and the mounting substrate can be relaxed. Conductive fillers include metal powder such as Ni, Ag, Ag-Pd, Ni, Ag, Ag-Pd
Sheets of metal powder coated with resin (epoxy, polyimide, silicone, etc.), resin core (epoxy, polyimide, silicone, etc.) coated with Ni, Ag, Ag-Pd, etc. By pressing, the conductive filler is brought into contact with the resin to be mixed in the resin in an amount necessary for generating conductivity. The conductor layer 54 is the anisotropic conductive sheet 52.
In addition to the one in which a metal foil such as a copper foil is attached, the anisotropic conductive sheet 52 can be formed by sputtering or vapor depositing a metal such as copper. Alternatively, anisotropic conductive material with conductive layer is prepared by casting (doctor blade method) an anisotropic conductive material prepared by mixing conductive filler with resin into a paste on a metal foil such as copper to cure into a sheet. It can be formed into a sheet. This anisotropic conductive sheet 50 with a conductor layer is used for the semiconductor device 30 shown in FIGS.
It can be preferably used for forming a wiring board, and can also be preferably used for a wiring board as shown below.

FIG. 13 shows an example of the wiring board 56. 58
Is a printed wiring board having a wiring pattern 60 formed on its surface by a known method using copper foil or the like. 52 is shown in FIG.
Is an anisotropic conductive sheet having a wiring pattern 62 formed on the surface by etching the conductive layer 54 of the anisotropic conductive sheet with a conductive layer 50 shown in FIG. The anisotropic conductor sheet 52 is fixed on the surface of the printed wiring board 58 on the surface opposite to the surface on which the wiring pattern 62 is formed. Then, a portion of the wiring pattern 62 is pressed from above the wiring pattern 62 by an appropriate pressing jig (not shown) to deform the wiring pattern 62, so that the wiring pattern 62 and the wiring pattern are intervened via the anisotropic conductive sheet 52. It is in electrical continuity with 60.

Reference numeral 64 is a photosensitive resist film (electrically insulating film), which is formed so as to cover the anisotropic conductive sheet 52 and the wiring pattern 62. The photosensitive resist film 64 is a protective film for the wiring pattern 62, and photosensitive solder resists made of various materials can be used. Through holes 66 are formed in appropriate portions of the photosensitive resist film 64 corresponding to the respective wiring patterns 62 (the portions of the wiring pattern 62 exposed by the through holes 66 are external connection portions 62a). External electronic parts can be connected to the external connection portion 62a by soldering or the like.

Since the anisotropic conductive sheet 52 and the photosensitive resist film 64 can be thinly formed, they can be formed on the thin wiring board 56. In particular, when a silicone resin is used, since it has rubber-like elasticity, the stress generated between the printed wiring board and the external electronic component mounted can be relaxed. Since the anisotropic conductive sheet 52 and the photosensitive resist film 64 are not so high in hardness, they also function as a buffer layer that protects external electronic components to be mounted. Further, as described above, since the anisotropic conductive sheet 52 is used, the wiring patterns 60, 62
Electrical connection between them can be easily made.

FIG. 14 shows another embodiment of the wiring board 56. The same members as those in the embodiment shown in FIG. 13 are designated by the same reference numerals, and the description thereof will be omitted. In the present embodiment, similarly to the case shown in FIG. 3, bumps 61 are formed on the wiring pattern 60 by Au or the like, and the anisotropic conductive sheet 52 is pressed by the bumps 61, whereby the wiring patterns 62, 6 are formed.
The electrical connection between 0 is taken. Bump 61
By forming the wiring pattern, the wiring pattern 62 can be maintained substantially flat, which is advantageous when the anisotropic conductive sheets 52 are laminated.

FIG. 15 shows an embodiment in which anisotropic conductive sheets 52 are provided in multiple layers on a printed wiring board 58. The connection between the wiring patterns 62 of the lower and upper anisotropic conductive sheets 52 and the connection between the wiring patterns 62 and 60 are performed by pressing and deforming the wiring patterns in the same manner as shown in FIG. Or the anisotropic conductive sheet 5 by the bumps 61, 61 formed on the wiring pattern 60 and the wiring pattern 62 as shown in the drawing.
You may make it connect by pushing 2. In this way, the anisotropic conductive sheet 52 can be easily electrically connected to form the multilayer wiring board 56. Further, in this case, the intermediate wiring pattern 62 can be formed as a solid pattern (not shown) for power supply or grounding by the same structure as shown in FIG. When the solid pattern is used as a solid pattern for power supply, the wiring of the power supply line of the upper wiring pattern 62 can be freely and easily performed. When the solid pattern for grounding is used, the degree of freedom of wiring can be improved and the sputtering can be performed on the solid pattern. By so doing, a so-called decoupling capacitor can be formed and electrical characteristics can be improved. These solid patterns for power supply or ground may be partially provided corresponding to the electronic components to be mounted.
A ceramic wiring board may be used as the wiring board.

FIG. 16 shows still another embodiment of the wiring board 56. In this embodiment, the anisotropic conductive sheets 52 with wiring patterns are formed in multiple layers (three layers in the illustrated example). In this case, the anisotropic conductive sheet of the first layer is
Anisotropic second and third layers using the anisotropic conductive sheet with conductor layers 50 having conductor layers formed on both sides, which is obtained by etching the conductor layers to form wiring patterns 62 and 62a on both sides. The conductive conductive sheet 52 is laminated by using a wiring pattern 62 formed on one surface in the same manner as described above, and thermocompression bonded to form a wiring substrate 56.

Between the two wiring patterns 62, 62a of the first-layer anisotropic conductive sheet, the wiring pattern 62a is pressed and deformed to electrically connect via the anisotropic conductive sheet 52. There is. Connection between the wiring patterns 62 of the first layer, the second layer, and the third layer is made via the bumps 61 and the anisotropic conductive sheet 52. 42, 4
2 is a photosensitive resist film (electrically insulating film), which is formed to cover the wiring patterns 62 and 62a on both surfaces,
An external connection terminal 46 such as a solder ball is formed in the through hole formed in one photosensitive resist film 42, and a wiring pattern 62 is exposed in the through hole formed in the other photosensitive resist film 42 to form an electronic component or the like. Is formed at the connection part of. The wiring patterns 62 may be formed on the anisotropic conductive sheet 52 in advance, or may be formed by etching the conductive layer each time one anisotropic conductive sheet with a conductive layer is laminated. Good.

As shown in FIG. 17, the wiring pattern 62 is formed on the insulating film 52a made of a polyimide sheet, an epoxy sheet, an anisotropic conductive sheet or the like as the first layer.
The anisotropic conductive sheet 52 having the wiring pattern 62 formed on one surface similarly to the above may be used for the second and higher layers, and laminated and thermocompression bonded. In this case 1
It is also possible to form the through holes directly in the insulating sheet 52a of the layer to form the external connection terminals 46. When the insulating film 52a is an anisotropic conductive sheet, a resist may be applied to protect the surface.

Further, in each of the above-described embodiments, the bumps 46 serving as external connection terminals are formed from the external connection terminal joint portion 40a and the peripheral edge of the through hole of the electrically insulating film 42 or the insulating sheet 41 as shown in FIG. By forming the metal layer 33 on the inner wall surface and forming the metal layer 33 on the metal layer 33, the bonding area is increased and the bonding strength is improved. Although various descriptions have been given to the present invention with reference to the preferred embodiments,
The present invention is not limited to this embodiment, and it goes without saying that many modifications can be made without departing from the spirit of the invention.

[0036]

As described above, according to the semiconductor device of the present invention, the anisotropic conductive sheet and the electrically insulating film to be the interposer can be thinly formed, so that the semiconductor device can be made thin and the cost can be reduced. Can be achieved. Since the anisotropic conductive sheet and the electrically insulating film do not have a very high hardness, they also function as a buffer layer that protects the surface of the semiconductor chip and relaxes the thermal or mechanical stress generated between the semiconductor chip and the mounting board. Has the effect of doing. Also, by electrically connecting the required electrodes of multiple semiconductor chips, electrical characteristics such as signal delay prevention can be improved, and the anisotropic conductive sheet and the electrically insulating film are formed in common to manufacture. Will also be easier.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a first embodiment.

FIG. 2 is a partially enlarged view of FIG.

FIG. 3 is a partial cross-sectional view showing another embodiment.

FIG. 4 is an explanatory diagram of an anisotropic conductive sheet on which a wiring pattern is formed.

FIG. 5 is an explanatory diagram of a crimping jig that thermocompresses an anisotropic conductive sheet.

FIG. 6 is a partial cross-sectional view showing still another embodiment.

FIG. 7 is a cross-sectional view showing an example in which an anisotropic conductive sheet is multilayered.

FIG. 8 is a cross-sectional view showing an example in which a pattern for power supply or grounding is provided.

FIG. 9 is an assembly diagram showing an example in which a wiring pattern is provided on an insulating sheet.

FIG. 10 is a completed view of the semiconductor device shown in FIG.

FIG. 11 is a cross-sectional view showing an example in which an insulating sheet is multilayered.

FIG. 12 is a cross-sectional view of an anisotropic conductive sheet with a conductor layer.

FIG. 13 is a cross-sectional explanatory diagram of a wiring board.

FIG. 14 is a cross-sectional view showing another example of the wiring board.

FIG. 15 is a cross-sectional explanatory view of a wiring board in which anisotropic conductive sheets are formed in multiple layers.

FIG. 16 is a cross-sectional view showing the structure of an external connection terminal.

FIG. 17 is a partial cross-sectional view showing another embodiment of a wiring board.

FIG. 18 is a partial cross-sectional view showing still another embodiment of a wiring board.

FIG. 19 is a cross-sectional view showing an example of a conventional semiconductor device.

[Explanation of symbols]

 30 semiconductor device 32 semiconductor chip 34 passivation film 36 Al pad 37 gold bump 38 anisotropic conductive sheet 40 wiring pattern 40a external connection terminal joint 42 electrical insulation film 44 through hole 48 protective film 50 anisotropic conductive sheet with conductive layer 52 Anisotropic Conductive Sheet 54 Conductor Layer 56 Wiring Board 58 Printed Wiring Board 60 Wiring Pattern 61 Bump 62 Wiring Pattern 64 Electrical Insulation Film 66 Through Hole

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location 9169-4M H01L 21/92 604Z

Claims (15)

[Claims] 1. An anisotropic conductive sheet having a wiring pattern formed on one surface thereof is fixed to the semiconductor chip surface on which a passivation film is formed, and the wiring pattern and the electrodes of the semiconductor chip are connected to each other. It is electrically connected through an anisotropic conductive sheet, the external connection terminal joint of the wiring pattern is exposed to form an electrically insulating film, and the external connection terminal is formed at the external connection terminal joint. A semiconductor device characterized in that. 2. The semiconductor device according to claim 1, wherein the anisotropic conductive sheet is electrically connected by being pressed by the wiring pattern. 3. A bump protruding outward from the passivation film is formed on an electrode of the semiconductor chip, and the anisotropic conductive sheet is pressed by the bump to be electrically connected. Claim 1 characterized by
13. The semiconductor device according to claim 1. 4. A semiconductor in which a plurality of anisotropic conductive sheets each having a wiring pattern formed on one surface thereof are laminated and fixed, and the other surface of the anisotropic conductive sheet at the lowermost layer has a passivation film formed thereon. It is fixed to the chip surface, and the wiring patterns and the wiring pattern and the electrodes of the semiconductor chip are electrically connected through the anisotropic conductive sheet, and are formed on the anisotropic conductive sheet of the uppermost layer. A semiconductor device, wherein the external connection terminal joint portion of the wiring pattern is exposed to form an electrically insulating film, and the external connection terminal joint portion is formed with an external connection terminal. 5. The semiconductor device according to claim 4, wherein the anisotropic conductive sheet is electrically connected by being pressed by the wiring pattern. 6. A bump protruding outward from the passivation film is formed on an electrode of the semiconductor chip, and a bump is also formed on a wiring pattern formed on an anisotropic conductive sheet as an inner layer. The semiconductor device according to claim 4, wherein the anisotropic conductive sheet is electrically connected by being pressed. 7. The semiconductor device according to claim 4, wherein any one of the wiring patterns is formed as a solid pattern for power supply or grounding. 8. A plurality of the semiconductor chips are provided, the common anisotropic conductive sheet is fixed to the plurality of semiconductor chips, and required electrodes of the plurality of semiconductor chips are electrically connected by the wiring pattern. The semiconductor device according to claim 1, 2, 3, 4, 5, 6 or 7, wherein the common electrically insulating film is formed on the uppermost wiring pattern. 9. The semiconductor device according to claim 1, wherein the electrically insulating film is formed of a photosensitive solder resist film. 10. The semiconductor device according to claim 1, wherein the external connection terminals formed on the external connection terminal joint portion are bumps. . 11. An insulating sheet having a wiring pattern formed on one surface thereof is fixed to the semiconductor chip surface having a passivation film formed thereon through an anisotropic conductive sheet, and the insulating pattern is formed on the insulating sheet. The electrodes of the semiconductor chip are electrically connected via the anisotropic conductive sheet, the insulating sheet is provided with through holes to expose the external connection terminal joint portion of the wiring pattern, and A semiconductor device, wherein an external connection terminal is formed at the connection terminal joint portion. 12. A plurality of insulating sheets having a wiring pattern formed on one surface thereof are laminated and fixed, and the one surface of the lowermost insulating sheet is a semiconductor chip surface on which a passivation film is formed. The wiring is fixed through an anisotropic conductive sheet, the wiring patterns are electrically connected to each other and the wiring patterns and the electrodes of the semiconductor chip are electrically connected, and a through hole is provided in the uppermost insulating sheet. A semiconductor device, wherein the external connection terminal joint portion of the pattern is exposed, and the external connection terminal is formed on the external connection terminal joint portion. 13. The semiconductor device according to claim 11, wherein one of the wiring patterns is formed as a solid pattern for power supply or grounding. 14. A bump protruding outward from the passivation film is formed on an electrode of the semiconductor chip,
14. The semiconductor device according to claim 11, 12 or 13, wherein the bumps are electrically connected by pressing the anisotropic conductive sheet. 15. The external connection terminal formed in the external connection terminal joint portion is a bump.
The semiconductor device according to 1, 12, 13 or 14.