JPH11186883A - Level shift circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the level shift circuit with a small delay time. SOLUTION: When a control element CR1 receiving an input Vin turns on an N channel MOSFETT1 , a drain current Id flows through the MOSFETT1 . P channel MOSFET T2 , T3 configure a current mirror circuit, nearly the same current as the drain current Id flowing through the N channel MOSFETT1 flows also through a resistor R1 and a voltage V0 is produced across the resistor R1 . The V0 is given to a low pass filter F1 and a high pass filter F2 . The low pass filter F1 eliminates a noise component in the voltage V() and provides an output of a voltage V1 at the outside of the frequencies including the noise component. On the other hand, the high pass filter F2 eliminates the frequency components other than the noise frequency components and provides an output of a voltage V2 within the noise frequency only. Then a flip-flop FF provides an output of a voltage V3 that is an OR of the voltage V1 of the low pass filter F1 and the voltage V2 of the high pass filter F2 .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shift circuit for converting a signal level of an input signal and outputting the converted signal.

[0002]

2. Description of the Related Art FIG. 3 shows a circuit diagram of a conventional level shift circuit 1, and FIG. 5 shows a half bridge circuit using the level shift circuit 1. FIG. 4 shows waveforms at various parts of the level shift circuit 1. Half-bridge circuit includes a DC power source E _3, a series circuit consisting of the load L _1, L ₂ that connected across the DC power source E _3, the load L _1, L ₂ and MOSFET Q ₁ connected in parallel, and Q _2, MO
Driving elements D for driving SFETs Q ₁ and Q ₂ , respectively
R ₁ , DR ₂ and the high-side MOSFE
Driving elements DR ₁ to drive the TQ ₁ is circuit ground GN
Since it operates in a state of floating with respect to D, the level shift circuit 1 is used to transmit a drive signal from a low-side circuit to a high-side circuit.

[0003] Control device CR ₁ is connected across the DC power source E _1, and off according to the output signal V _in of the control device P. Output of the control device CR ₁ is input to the control device CR _2, the driving element DR ₂ is off the low-side MOSFET Q ₂ in accordance with the output of the control element CR _2, time to operation of the low-side MOSFET Q ₂ delay Does not occur. The low potential side of the DC power source E ₁ is connected to the ground GND of the circuit.

[0006] The level shift circuit 1 has a source
The gate is connected to the land GND and the control element is
CR₁N-type MOSFETT connected to the output terminal of₁When,
The gate and drain are short-circuited and the drain is an N-type MOS
FETT₁Connected to the drain of
DC power supply E having a potential difference with respect to land GND_TwoHigh
First P-type MOSF whose source is connected to the potential side output terminal
ETT_TwoAnd P-type MOSFETT_Two
P-type M connected to the gate and source of
OSFETT_ThreeAnd P-type MOSFETT_ThreeDrain and
DC power supply E_TwoConnected between the low-potential output terminal of
R₁And P-type MOSFETT_ThreeAnd resistance R ₁At the connection point with
Input terminal is connected, N-type MOSFETT₁High voltage switch
Resistance R at the time of switching₁Noise generated between both ends of the
Filter circuit F_ThreeAnd an N-type MOSFET T₁
Control element CR input to the gate of₁DC control signal
Power supply E_TwoThe signal level is converted and output.

Here, the high-side MOSFET Q₁But
ON, low side MOSFET Q _TwoTurns off and the output
Voltage Vs and N-type MOSFETT₁High voltage
The case where the voltage is applied will be described. Output signal of controller P
Issue V_inDepending on the control element CR₁Is N-type MOSFETT₁
When a control signal Vgs is applied between the gate and source of
MOSFETT₁Turns on and N-type MOSFETT₁To
A drain current (level shift current) Id flows. this
The drain current Id is a P-type MOSFET T_TwoConstant current circuit
Supplied from Here, P-type MOSFETT_Two, T_Three
Constitutes a current mirror circuit, so a P-type MOS
FETT_ThreeN-type MOSFETT₁Drain current I
d, the same current flows through the resistor R₁Both ends of
Voltage V between_OOccurs, and this voltage V₀Is the filter circuit F
_ThreeIs applied to At this time, the N-type MOSFET T₁Dre
Because the in-source voltage fluctuates rapidly,
The drain current Id flows rapidly due to the voltage fluctuation,
The above current flows instantaneously. Thus, this sudden overcurrent
By resistance R₁Voltage V₀Surge noise occurs
However, the filter circuit F _ThreeVoltage V₀Noise component
Can be removed. In addition, two P-type MOSFETs
TT_Two, T_ThreeIs operating in the active area,
No elongation occurs (see, for example, Japanese Patent Application Laid-Open No.
Report).

[0006]

The level shift circuit 1 having the above configuration [0005] Since there is provided a filter circuit F ₃ to the output stage, although it is possible to remove noise generated during switching of the high side MOSFET Q _1, constant large delay time in the output voltage V ₄ of the filter circuit F ₃ by the time of the filter circuit F ₃ DT ₂ is generated. Therefore, a delay in the timing of MOSFET Q ₁ of the high-side is turned off, there is a possibility MOSFET Q _1, Q ₂ is generated of both where an on state called arm short, in order to prevent such arm short, the low-side MOSFET Q _It was necessary to provide a delay circuit with a large delay time in the drive circuit for driving the ₁ . Therefore, there is a problem that the scale of the entire circuit becomes large and it is difficult to convert the present circuit into an IC. Also,
There is also a problem that an external component is required for adjusting the delay circuit.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to reduce the delay time of a high-side switching element to provide a delay circuit in a driving circuit of a low-side switching element. Is to provide a level shift circuit which eliminates the need.

[0008]

According to the present invention, in order to achieve the above object, an N-type MOS transistor is provided in which a source is connected to a circuit ground and a control signal is inputted to a gate.
ET is short-circuited between the gate and drain, and the drain is N
P-type MOSFET connected to the drain of a MOSFET and having a source connected to a high-potential output terminal of a drive power supply having a potential difference with respect to the ground of the circuit
And a second P-type MOSF whose gate and source are respectively connected to the gate and source of the first P-type MOSFET
ET, a resistor connected between the drain of the second P-type MOSFET and the low-potential output terminal of the drive power supply, a low-pass filter for removing a high-frequency component of a voltage generated between both ends of the resistor, A high-pass filter that removes a low-frequency component of a voltage generated between both ends of the resistor; and a flip-flop circuit that outputs a logical sum of output signals of the low-pass filter and the high-pass filter. Of these, the signal in the noise generating area is removed by a low-pass filter, and the signal outside the noise generating area is removed by a high-pass filter. The signal can be output and the output signal rises compared to the conventional level shift circuit. Rino time lag can be shortened.

[0009]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a level shift circuit 1 according to this embodiment.
FIG. 2 shows a waveform of each part. The level shift circuit 1 of the present embodiment, in the conventional level shift circuit 1 shown in FIG. 3, a low pass filter for removing instead of the filter circuit F _3, a high-frequency component of the voltage V ₀ generated across resistor R ₁ and F _1, a high-pass filter F ₂ to remove low-frequency component of the voltage V ₀ generated across resistor R _1, the output voltage V ₂ of the output voltage V ₁ and the high-pass filter F ₂ of the low-pass filter F ₁ It is provided a flip-flop circuit FF for outputting a voltage V ₃ of the logical OR. The configuration of the level shift circuit 1 other than the low-pass filter F ₁ , the high-pass filter F ₂ and the flip-flop circuit FF is the same as that of the conventional level shift circuit 1 shown in FIG. The reference numerals are attached and the description is omitted. The half bridge circuit using the level shift circuit 1 of the present embodiment is the same as the half bridge circuit shown in FIG. 5 described above, and the illustration and description of the half bridge circuit will be omitted.

Here, the MOSFET Q on the high side is₁
Is on, low-side MOSFET Q_TwoIs off,
Output voltage Vs and N-type MOSFETT₁To each
Is applied and the load L_TwoDC power supply E_ThreeIs applied
Will be described. Control element CR₁Is the output signal
V_inN-type MOSFETT according to₁Between gate and source
When the control signal Vgs is applied to the N-type MOSFET T₁But
Turn on, N-type MOSFETT₁The drain current Id
Flows. This drain current is the first P-type MOSFET T
_TwoIs supplied from the constant current circuit. Two first and second
P-type MOSFETT_Two, T_ThreeIs a current mirror circuit.
The P-type MOSFETT _ThreeN-type MOS
FETT₁The same current as the drain current Id flows. This
Resistance R due to the drain current Id of₁Voltage across
V_OOccurs, and this voltage V₀Is a low-pass filter F₁Passing
And high-pass filter F_TwoIs input to

At this time, the N-type MOSFET T₁Drain of
・ Because the source-to-source voltage changes rapidly, N-type MOSFE
TT₁Current Id rapidly flows through the N-type MOSF
ETT₁A current exceeding the rating flows instantaneously. This steep
Resistor R due to overcurrent₁Voltage V₀Surge noise
Occurs, but the low-pass filter F₁By the voltage V ₀
Of the low-pass filter F₁From
Voltage V outside the noise generation area₁Is output. Meanwhile, c
Ipass filter F_TwoBy the voltage V₀Other than the noise component
Of the high-pass filter F_TwoNoise from
Voltage V only in generation area_TwoIs output and the flip-flop
Circuit FF is low-pass filter F₁Output voltage V₁And high
Pass filter F_TwoOutput voltage V_TwoAnd the logical sum voltage V_Three
Is output. At this time, the low-pass filter F₁Sui by
The noise at the time of switching can be removed and
Pass filter F_TwoIs the voltage V in the noise generation region_TwoOutput
Therefore, compared to the conventional level shift circuit 1, the signal
V_inOutput voltage V from the rise of_ThreeUntil it rises
Time delay DT₁Can be shortened. Therefore,
Low-side MOSFET Q_TwoLarge delay in the drive circuit
There is no need to provide an extension circuit, which increases the overall circuit scale.
Level shift circuit 1 can be easily integrated into an IC.
It has the effect of becoming.

[0012]

As described above, according to the present invention, an N-type MOSFET whose source is connected to the ground of the circuit and a control signal is input to the gate, the gate and the drain are short-circuited, and the drain is an N-type A first P-type MOSFET connected to the drain of the MOSFET and having a source connected to the high potential side output terminal of the drive power supply having a potential difference with respect to the ground of the circuit;
A second P-type MOSFET respectively connected to the gate and the source of the P-type MOSFET, and a second P-type MOSFET
A low-pass filter that removes a high-frequency component of a voltage generated between both ends of the resistor; a resistor connected between the drain of the driving power supply and a low potential side output terminal of the driving power supply; A high-pass filter that removes low-frequency components; and a flip-flop circuit that outputs a logical sum of output signals of the low-pass filter and the high-pass filter. Since the signal outside the noise generation area is removed by the high-pass filter while filtering, the noise at the time of switching can be removed by the low-pass filter, and the signal in the noise generation area is output by the high-pass filter. This makes it possible to reduce the time delay of the rise of the output signal compared to the conventional level shift circuit. There is an effect that that. Therefore,
There is no need to provide a large delay circuit in the drive circuit of the low-side MOSFET, and the level shift circuit 1 can be easily integrated into an IC.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a level shift circuit according to an embodiment.

FIG. 2 is a waveform chart of each part of the above.

FIG. 3 is a circuit diagram showing a conventional level shift circuit.

FIG. 4 is a waveform chart of each part of the above.

FIG. 5 is a half-bridge circuit using the above level shift circuit.

[Explanation of symbols]

CR ₁ control element F ₁ lowpass filter F ₂ high pass filter FF flip-flop Id drain current R ₁ resistor T ₁ N-type MOSFET T _2, T ₃ P-type _{MOSFET V 0, V 1, V} 2, V 3, V in voltage

Claims (1)

[Claims] An N-type MOSFET having a source connected to the ground of the circuit and a control signal input to the gate.
And the gate and drain are short-circuited and the drain is N-type M
A first P-type MOSFET connected to the drain of the OSFET and having a source connected to a high-potential output terminal of a driving power supply having a potential difference with respect to the ground of the circuit; P-type MOSFETs respectively connected to the gate and source of the MOSFET
A resistor connected between a drain of the second P-type MOSFET and a low-potential output terminal of a driving power supply; a low-pass filter for removing a high-frequency component of a voltage generated between both ends of the resistor; And a flip-flop circuit for outputting a logical sum of output signals of the low-pass filter and the high-pass filter.