JPH11186884A - Level shift circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the level shift circuit with a small delay time. SOLUTION: When a control element CR1 receiving an input Vin turns on an N channel MOSFETT1 , a drain current Id flows through the MOSFETT1 . P channel MOSFET T2 , T3 configure a current mirror circuit, nearly the same current as the drain current Id flowing through the N channel MOSFETT1 flows also through a resistor R1 and a voltage V0 is produced across the resistor R1 . The V0 is given to a low pass filter F and the low pass filter F eliminates a noise component produced at switching. An output of a voltage V1 of the filter circuit F is given to a trigger switching circuit ST. When the voltage V1 is more than or less than a trigger level, an output voltage V2 of the trigger switching circuit ST rises or falls down. The trigger switching circuit ST selects properly the input trigger level to reduce a time delay of the output voltage V2 .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shift circuit for converting an input signal level and outputting the converted signal level.

[0002]

2. Description of the Related Art FIG. 3 shows a circuit diagram of a conventional level shift circuit 1, and FIG. 5 shows a half bridge circuit using the level shift circuit 1. FIG. 4 shows waveforms at various parts of the level shift circuit 1. Half-bridge circuit includes a DC power source E _3, a series circuit consisting of the load L _1, L ₂ that connected across the DC power source E _3, the load L _1, L ₂ and MOSFET Q ₁ connected in parallel, and Q _2, MO
Driving elements D for driving SFETs Q ₁ and Q ₂ , respectively
R ₁ , DR ₂ and the high-side MOSFE
Driving elements DR ₁ to drive the TQ ₁ is circuit ground GN
Since it operates in a state of floating with respect to D, the level shift circuit 1 is used to transmit a drive signal from a low-side circuit to a high-side circuit.

[0003] Control device CR ₁ is connected across the DC power source E _1, and off according to the output voltage V _in of the control device P. Output of the control device CR ₁ is input to the control device CR _2, the driving element DR ₂ is off the low-side MOSFET Q ₂ in accordance with the output of the control element CR _2, the delay time in the operation of the low-side MOSFET Q ₂ Does not occur. The low potential side of the DC power source E ₁ is connected to the ground GND of the circuit.

[0006] The level shift circuit 1 has a source
The gate is connected to the land GND and the control element is
CR₁N-type MOSFETT connected to the output terminal of₁When,
The gate and drain are short-circuited and the drain is an N-type MOS
FETT₁Connected to the drain of
DC power supply E having a potential difference with respect to land GND_TwoHigh
First P-type MOSF whose source is connected to the potential side output terminal
ETT_TwoAnd P-type MOSFETT_Two
P-type M connected to the gate and source of
OSFETT_ThreeAnd P-type MOSFETT_ThreeDrain and
DC power supply E_TwoConnected between the low-potential output terminal of
R₁And P-type MOSFETT_ThreeAnd resistance R ₁At the connection point with
Input terminal is connected, N-type MOSFETT₁High voltage switch
Resistance R at the time of switching₁Noise generated between both ends of the
And an N-type MOSFET T₁of
Control element CR input to gate₁Control signal
Source E_TwoThe signal level is converted and output.

Here, the high-side MOSFET Q₁But
ON, low side MOSFET Q _TwoTurns off and the output
Voltage Vs and N-type MOSFETT₁High voltage
The case where the voltage is applied will be described. Output power of control device P
Pressure V_inDepending on the control element CR₁Is N-type MOSFETT₁
When a control signal Vgs is applied between the gate and source of
MOSFETT₁Turns on and N-type MOSFETT₁To
A drain current (level shift current) Id flows. this
The drain current Id is a P-type MOSFET T_TwoConstant current circuit
Supplied from Here, P-type MOSFETT_Two, T_Three
Constitutes a current mirror circuit, so a P-type MOS
FETT_ThreeN-type MOSFETT₁Drain current I
d, the same current flows through the resistor R₁Both ends of
Voltage V between_OOccurs, and this voltage V₀Is the filter circuit F
Is applied to At this time, the N-type MOSFET T₁Dray of
The source-to-source voltage fluctuates rapidly.
The drain current Id flows rapidly due to pressure fluctuation,
The above current flows instantaneously. Thus, this sudden overcurrent
Therefore, the resistance R₁Voltage V₀Generates surge noise
However, the voltage V₀Noise component
You can leave. In addition, two P-type MOSFETT
_Two, T_ThreeIs operating in the active region, so the large delay is
Does not occur (for example, see Japanese Patent Application Laid-Open No. 3-29512).
See).

[0006]

The level shift circuit 1 having the above configuration [0005] Since there is provided a filter circuit F to the output stage, although it is possible to remove noise generated during switching of the high side MOSFET Q _1, the filter A large delay time DT ₂ occurs in the output voltage V ₄ of the filter circuit F due to the time constant of the circuit F. Therefore, MOSFETQ ₁ of the high-side is a delay in the timing of turning off,
There is a possibility that a so-called arm short-circuit may occur in which both the MOSFETs Q ₁ and Q ₂ are turned on. To prevent such an arm short-circuit, a delay circuit having a large delay time is provided in a drive circuit for driving the low-side MOSFET Q _1. Needed. Therefore, there is a problem that the scale of the entire circuit becomes large and it is difficult to convert the present circuit into an IC. Another problem is that an external component is required for adjusting the delay circuit.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to reduce the delay time of a high-side switching element to provide a delay circuit in a driving circuit of a low-side switching element. Is to provide a level shift circuit which eliminates the need.

[0008]

According to the present invention, in order to achieve the above object, an N-type MOSFET having a source connected to the ground of a circuit and having a gate to which a control signal is inputted from the outside, a gate and a drain. A first P-type MOS having a source connected to a high-potential output terminal of a drive power supply having a potential difference with respect to the circuit ground, and a drain connected to the drain of the N-type MOSFET;
FET, gate and source of first P-type MOSFET
P-type M connected to the gate and source of
An input terminal connected to a connection point between the OSFET, the drain of the second P-type MOSFET and the low potential side output terminal of the driving power supply, and a connection point between the second P-type MOSFET and the resistance; A filter circuit for removing noise generated at the time of high-voltage switching of the type MOSFET, wherein the level shift circuit converts the control signal into a signal level of a driving power supply and outputs the signal. Is provided, and the trigger switching circuit switches the trigger level of the input so as to reduce the delay of the output.Before the input from the filter circuit completely rises or falls, the trigger switching circuit outputs the signal from the filter circuit. When the input is above or below the trigger level and the trigger switching circuit is triggered to generate an output, a control signal is input. The level shift circuit from when it is possible to shorten the time until generation of the output.

[0009]

Embodiments of the present invention will be described with reference to the drawings.
I will explain. FIG. 1 shows a level shift circuit 1 according to this embodiment.
FIG. 2 shows a waveform of each part. With this circuit
Is the output voltage of the filter circuit F in the circuit shown in FIG.
Pressure V₁Triggered by eg Schmitt trigger circuit
Is provided. Where
Rig switching circuit ST has its output voltage V_TwoSignal level
The input trigger level is switched according to the output voltage.
V_TwoWhen the signal level of the
Bell lower value V_L1To output V_TwoSignal level is
In the case of high level, set the input trigger level to high value V_L2To
Switching (V _L1<V_L2). The trigger switching circuit S
The configuration of the level shift circuit 1 other than the T
The same components as the level shift circuit 1
Are denoted by the same reference numerals, and description thereof is omitted. Also,
Half bridge using the level shift circuit 1 of the present embodiment
The circuit is the same as the half-bridge circuit shown in FIG.
Therefore, the half using the level shift circuit 1
Illustration and explanation of the bridge circuit are omitted.

Here, the high side of the half-bridge circuit
MOSFET Q on the side₁Is on, low side MOSF
ETQ_TwoTurns off, the output voltage Vs and the N-type MOSFET
TT ₁High potential is applied between the drain and source of
The following describes the case in which it is performed. Control element CR₁from
N-type MOSFET T by control signal Vgs₁Is on
To N-type MOSFETT₁To drain current
(Level shift current) Id flows, and the drain current Id
d is the first P-type MOSFETT_TwoSupplied by a constant current circuit
It is. Here, two first and second P-type MOSFETs
T_Two, T_ThreeConstitutes a current mirror circuit, and is a P-type
MOSFETT_ThreeN-type MOSFETT₁Drain current
The same current as the current Id flows. Thus, the resistance R₁Between both ends of
Current Id flows through the₀Occurs. this
At this time, as shown in FIG.₀Surge at rising edge
Although noise is generated, the voltage V₀To
The generated noise is removed, and the output V of the filter circuit F is reduced.₁
Changes slowly in rising or falling.

Here, the trigger switching circuit ST includes a filter
Input voltage V from circuit F₁Rise, that is, bird
Output voltage V of the gas switching circuit ST_TwoIs low level
Lower trigger level V_L1Is switched to
Input voltage V from the filter circuit F ₁Is the trigger level V_L1On
At this point, the output V of the trigger switching circuit ST_TwoRise
To Therefore, the output V of the filter circuit F₁Is completely
Before starting, the trigger switching circuit ST is triggered.
And the output V of the trigger switching circuit ST_TwoRises and this
Output V_TwoIs the driving element DR of the half-bridge circuit_TwoOutput to
Voltage V₀Output V_TwoStanding
Until it rises, that is, MOSFET Q on the high side₁
Delay time DT until is turned on₁Can be shortened
You.

On the other hand, the trigger switching circuit ST includes a filter circuit.
Input voltage V from path F₁Falling, ie trigger
Output voltage V of switching circuit ST_TwoIs high when
Riga level high value V_L2Is switched to
Input voltage V from the₁Is the trigger level V_L2Below
The output V of the trigger switching circuit ST_TwoFall
You. Therefore, the output V of the filter circuit F₁Is completely standing
Before falling, the trigger switching circuit ST is triggered,
Output V of trigger switching circuit ST_TwoFalls and this output
V_TwoIs the driving element DR of the half-bridge circuit_TwoOutput to
Therefore, the voltage V ₀Output V from the falling edge of_TwoFall
Until it is, that is, the MOSFET Q on the high side₁But
Delay time DT₁Can be shortened.

Therefore, in this circuit, the conventional level shifter is used.
The delay time of the level shift circuit 1 is shorter than that of the shift circuit 1.
Because it can be shortened, the low side MOSFE
TQ _TwoIt is not necessary to provide a delay circuit of
The entire circuit does not become large, and the level shift circuit 1
It is easy to convert to C. In this embodiment, the trigger is turned off.
Although a Schmitt trigger circuit is used for the conversion circuit ST,
The purpose of limiting the rigger switching circuit ST to a Schmitt trigger circuit
Input so that the output delay is small.
Circuit that switches the trigger level of
Circuits other than trigger circuits, such as comparison circuits with hysteresis
Needless to say, the trigger switching circuit ST may be configured by
Nor.

[0014]

As described above, according to the present invention, an N-type MOSFET whose source is connected to the ground of the circuit and whose gate receives a control signal from the outside is short-circuited between the gate and drain, and the drain is A first P-type MOSFET connected to the drain of the N-type MOSFET and having a source connected to the high-potential output terminal of the drive power supply having a potential difference with respect to the ground of the circuit; A second P-type MOSFET connected to the gate and the source of the second type MOSFET, respectively, and a second P-type MOSFET.
A resistor connected between the drain of the SFET and the low-potential-side output terminal of the drive power supply, and an input terminal connected to a connection point between the second P-type MOSFET and the resistor, generated during high-voltage switching of the N-type MOSFET A filter circuit for converting the control signal into a signal level of a driving power supply and outputting the signal, wherein a trigger switching circuit for generating an output triggered by an input signal from the filter circuit is provided. Since the trigger switching circuit switches the trigger level of the input so as to reduce the output delay, whether the input from the filter circuit exceeds the trigger level before the input from the filter circuit completely rises or falls. Or below, the trigger switching circuit is triggered to generate an output, so the level shift is performed after the control signal is input. There is an effect that can shorten the time until the circuit generates an output. Therefore, it is not necessary to provide a large delay circuit in the drive circuit of the MOSFET on the low side, and the entire circuit does not become large, so that the level shift circuit can be easily made into an IC.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a level shift circuit according to an embodiment.

FIG. 2 is a waveform chart of each part of the above.

FIG. 3 is a circuit diagram showing a conventional level shift circuit.

FIG. 4 is a waveform chart of each part of the above.

FIG. 5 is a half-bridge circuit using the above level shift circuit.

[Explanation of symbols]

CR ₁ control element F filter circuit Id drain current R ₁ resistor ST triggers switching circuit T ₁ N-type MOSFET T _2, T ₃ P-type _{MOSFET V 0, V 1, V} 2, V in voltage

Claims (1)

[Claims] An N-type MO having a source connected to the ground of the circuit and a control signal input to the gate from the outside.
The SFET and the gate and drain are short-circuited, and the drain is connected to the drain of the N-type MOSFET.
A first P-type MOSFET having a source connected to a high-potential output terminal of a driving power supply having a potential difference with respect to the ground of the circuit;
T, and a second P-type MOS whose gate and source are connected to the gate and source of the first P-type MOSFET, respectively.
An FET, a resistor connected between the drain of the second P-type MOSFET and the low-potential output terminal of the driving power supply, and an input terminal connected to a connection point between the second P-type MOSFET and the resistor; A filter circuit for removing noise generated at the time of high-voltage switching of the type MOSFET, wherein the level shift circuit converts the control signal into a signal level of a driving power supply and outputs the signal. A trigger switching circuit for generating
A trigger shift circuit for switching an input trigger level so as to reduce an output delay.