JPH11186408A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) Abstract: Provided is a method of manufacturing a semiconductor device having a MOS transistor as a constituent element in which a threshold voltage and a punch-through breakdown voltage are prevented from lowering and frequency characteristics are improved. SOLUTION: After forming source / drain layers 22 and 24 by an ion implantation method, ion implantation using SiF ions is performed to amorphize the surfaces of the source / drain layers 22 and 24, and then a Co film is deposited by a sputtering method. Source / drain layer 2 by two-stage heat treatment
Low resistance CoSi ₂ films 26 and 27 on the surfaces of the polysilicon gate electrodes 14 of the gate electrode portions 3 and 4
And 28 and 29 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having as a constituent element a MOS transistor for forming a refractory metal silicide film on the surface of a source / drain layer.

[0002]

2. Description of the Related Art In recent years, with high integration and high speed of semiconductor devices, semiconductor devices such as fine processing technology, flattening technology, multilayer wiring technology, wiring technology using low-resistance material, and technology for lowering the dielectric constant of an interlayer insulating film, etc. The development of process technology is being actively pursued. In particular, in a highly integrated semiconductor device including a MOS transistor as a constituent element, the minimum processing dimension of the MOS transistor design has become smaller than a quarter micron. For example, a threshold voltage characteristic, a withstand voltage characteristic between a source and a drain and between a drain and a substrate, a resistance characteristic of a diffusion layer of a source / drain portion, and the like.
It has become difficult to secure the desired characteristics, and the structure of the MOS transistor itself has been developed along with the development of fine processing technology.

Here, a conventional dual gate CMOS including a PMOS transistor and an NMOS transistor is described.
An example of a method for manufacturing a die-type highly integrated semiconductor device will be described with reference to FIGS. First, as shown in FIG. 5A, the N well 12 of the PMOS transistor portion 1 is formed.
And LOCOS (Local Oxid)
An SiO ₂ film is formed on the surface of the semiconductor substrate 11 on which the film 13 and the like are formed by a thermal oxidation method, and then a polysilicon film not doped with impurities is deposited by a low pressure CVD method or the like. Then, the above-mentioned polysilicon film and SiO ₂ film are patterned to form gate electrode portions 3 and 4 composed of polysilicon gate electrode 14 and gate oxide film 15.

Next, using a photoresist (not shown) patterned so as to cover the NMOS transistor section 2 as a mask, the pocket diffusion layer 16 of the PMOS transistor section 1 is formed by a large tilt ion implantation method. Perform ion implantation with ions to be N-type impurities,
Subsequently, the LDD (Light) of the PMOS transistor unit 1 is
In order to form the (ly doped drain) layer 17, ion implantation using ions serving as P-type impurities is performed.
Next, in the same manner as described above, ion implantation for forming the pocket diffusion layer 18 and the LDD layer 19 of the NMOS transistor section 2 is performed. After that, heat treatment is performed, and the semiconductor substrate 1
The ion implanted in 1 is activated.

Next, as shown in FIG. 5B, after depositing a CVD SiO ₂ film by the CVD method,
The O ₂ film is etched back by an anisotropic plasma etching method to form a sidewall insulating film 20 on the side walls of the gate electrode portions 3 and 4. Next, a photoresist 21 is applied, the photoresist 21 is patterned, and P
The photoresist 21 of the MOS transistor portion 1 is removed, and the photoresist 2 is removed from the NMOS transistor portion 2 and the like.
1 is left.

Next, ion implantation for forming the source / drain layer 22 in the source / drain section 5 of the PMOS transistor section 1 is performed using BF ₂ ions by ion implantation. At this time, the BF ₂ ions are not only implanted into the source / drain portions 5 of the PMOS transistor portion 1 but also implanted into the polysilicon gate electrode 14 of the gate electrode portion 3 of the PMOS transistor portion 1, and after a heat treatment described later, Becomes a P-type conductive low-resistance polysilicon gate electrode 14.

Next, as shown in FIG. 5C, after removing the photoresist 21, a new photoresist 23 is applied, and the photoresist 23 is patterned to
The photoresist 22 of the MOS transistor unit 2 is removed, and the photoresist 2 is removed from the PMOS transistor unit 1 and the like.
3 is left. Next, the source / drain portion 6 of the NMOS transistor portion 2 is formed by ion implantation.
Next, ion implantation for forming the source / drain layers 24 is performed using As ions.

Next, as shown in FIG. 6D, after the photoresist 23 is removed, activation of B ions or As ions implanted into the source / drain portions 5 and 6 or the formation of an amorphous source A heat treatment also serving as recrystallization or the like of the surface portions of the semiconductor substrate 11 of the drain portions 5 and 6 is performed to form source / drain layers 22 and 24 in which implanted ions are activated. Thereafter, Si ions are implanted into the surfaces of the source / drain layers 22 and 24 of the PMOS transistor section 1 and the NMOS transistor section 2 by ion implantation, and the source
The surfaces of the drain layers 22 and 24 are made amorphous.

Next, as shown in FIG. 6E, a Co film 25, which is a high melting point metal film, is deposited by a sputtering method.

[0010] Next, as shown in FIG. 6 (f), a relatively low-temperature heat treatment is first performed to make the surfaces of the source / drain layers 22, 24 of the source / drain portions 5, 6 and the gate electrode portion 3,
4 on the surface of the polysilicon gate electrode 14 and C
the source / drain layers 22, 2
A CoSi ₂ film including a CoSi film as a refractory metal silicide film is formed on the surface of the polysilicon gate electrode 14 and the surface of the polysilicon gate electrode 14. The resistivity of the CoSi film formed at this stage is:
This is a high-resistance CoSi film that does not have the expected low resistivity yet.

Next, a Co film 25, which is not reacted with the insulating film by the above-described heat treatment at a relatively low temperature, deposited on the LOCOS film 13, the sidewall insulating film 20, etc. Remove with liquid. Thereafter, a high-temperature heat treatment is performed to convert the high-resistance CoSi film on the surface of the source / drain layers 22 and 24 and the surface of the polysilicon gate electrode 14 of the gate electrode portions 3 and 4 to an expected low resistivity,
CoSi ₂ films 26, 27 and 28, which are low-resistance refractory metal silicide films, are formed on the surfaces of the drain layers 22 and 24 and the surfaces of the polysilicon gate electrodes 14 of the gate electrode portions 3 and 4.
9 is formed. According to the above-described method, the low-resistance CoSi film is self-aligned on the surface of the source / drain layers 22 and 24 and the surface of the polysilicon gate electrode 14 of the gate electrode portions 3 and 4.
_The source / drain layers 22, 24 are formed by a process of forming the _two films 26, 27 and 28, 29, a so-called salicide process.
The resistance of the diffusion layer is reduced, and the resistance of the gate electrode is reduced by the polysilicon gate electrode 14 of the gate electrode part 3 and the CoSi ₂ films 28 and 29 which are the refractory metal silicide films.

Thereafter, although not shown in the drawings, deposition of an interlayer insulating film, formation of contact holes such as source / drain portions 5, 6 and the like, formation of wiring, deposition of a passivation film, and opening of a pad portion are performed by a manufacturing method according to a conventional method. A semiconductor device is manufactured by performing formation and the like.

In the above-described method of manufacturing a highly integrated semiconductor device of the dual gate CMOS type, the pre-amorphous ion implantation using Si ions is performed to control the silicidation reaction and to form the source / drain layer 22. , 24
Although low-resistance CoSi ₂ films 26 and 27 are formed on the surface, during the high-temperature heat treatment in the subsequent salicide step, the increase in B caused by the formation of pairs between interstitial Si and ion-implanted B occurs. An increase in the junction depth of the source / drain layer 22 of the PMOS transistor portion 1 due to diffusion cannot be suppressed, and a decrease in the concentration of the pocket diffusion layer 18 in the NMOS transistor portion 2 due to the accelerated diffusion of B cannot be suppressed. Therefore, there is a possibility that the threshold voltage may be lowered or the punch-through withstand voltage between the source and the drain may be lowered.

The low-resistance CoSi ₂ films 26 and 27 of the source / drain layers 22 and 24 of the PMOS transistor portion 1 and the NMOS transistor portion 2 formed by the above-described semiconductor device manufacturing method are used in the salicide process. Due to the reaction between the Co film 25 and the silicon of the underlying source / drain layers 22 and 24, there is a possibility that a problem that the range of lowering resistance is insufficient and a MOS transistor with good frequency characteristics cannot be obtained.

[0015]

SUMMARY OF THE INVENTION In the method of manufacturing a semiconductor device having the conventional MOS transistor as a constituent element, after the ion implantation for forming the source / drain layers,
In the pre-amorphization ion implantation using Si ions, the junction depth of the source / drain layers of the PMOS transistor may be increased, and the concentration of the pocket diffusion layer in the NMOS transistor may be reduced.
There has been a problem that the threshold voltage of the OS transistor or the NMOS transistor may be reduced, and the punch-through breakdown voltage between the source and the drain may be reduced. Further, CoSi which is a refractory metal silicide film of a source / drain portion formed in a salicide process in a manufacturing process of a semiconductor device.
₂ Film is a MOS with an inadequate reaction range and good frequency characteristics
There is a possibility that a problem that a transistor cannot be obtained may occur. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device having, as a constituent element, a MOS transistor in which a decrease in threshold voltage or punch-through withstand voltage is suppressed and a frequency characteristic is improved. It is to provide a manufacturing method.

[0016]

SUMMARY OF THE INVENTION A method of manufacturing a semiconductor device according to the present invention is proposed to solve the above-mentioned problem, and forms a refractory metal silicide film on the surface of a source / drain layer of a MOS transistor. In a method for manufacturing a semiconductor device having a step, a step of forming a source / drain layer by an ion implantation method and, after forming the source / drain layer, an ion implantation using a compound ion of a group IV atom and a group VII atom, Amorphizing the source / drain layer surface, depositing one of the refractory metal films and the composite film in which the refractory metal nitride film is laminated on the refractory metal film, Forming a refractory metal silicide film on the source / drain layer surface by reacting the refractory metal film with silicon of the source / drain layer. It is characterized in that.

According to the present invention, after the source / drain layers are formed by ion implantation, ion implantation is performed using compound ions of group IV atoms and group VII atoms, for example, SiF ions, and the surfaces of the source / drain layers are formed. By making it amorphous, the resistance of the refractory metal silicide film formed on the source / drain layer surface can be easily reduced, and at the same time, the boron of the source / drain layer during the heat treatment for forming the refractory metal silicide film. (B) shows interstitial Si
The enhanced diffusion phenomenon that pairs and diffuses with the implanted Si
Since the effect of inhibiting the formation of pairs of interstitial Si and B by F atoms in F ions can be suppressed, the junction depth of the source / drain layers of the PMOS transistor increases,
A decrease in the concentration of the pocket diffusion layer of the transistor can be suppressed. Accordingly, a decrease in the threshold voltage and the punch-through breakdown voltage is suppressed, and a semiconductor device having a MOS transistor with improved frequency characteristics as a constituent element can be manufactured.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described with reference to the accompanying drawings. The same components as those in FIGS. 5 and 6 referred to in the description of the related art are denoted by the same reference numerals.

Embodiment 1 This embodiment is an example in which the present invention is applied to a method of manufacturing a highly integrated semiconductor device of a dual gate CMOS type including a PMOS transistor and an NMOS transistor. This will be described with reference to FIGS. First, as shown in FIG. 1A, for example, the N well 12 of the PMOS transistor unit 1 or the LOCOS
A SiO ₂ film having a thickness of about 4 nm is formed on the surface of the P-type semiconductor substrate 11 on which the film 13 and the like are formed by a thermal oxidation method. Then, the polysilicon film and the SiO ₂ film are patterned to form gate electrode portions 3 and 4 composed of a polysilicon gate electrode 14 and a gate oxide film 15. .

Next, using a photoresist (not shown) patterned so as to cover the NMOS transistor portion 2 as a mask, the pocket diffusion layer 16 of the PMOS transistor portion 1 is formed by large-angle ion implantation.
Ion implantation using ions serving as N-type impurities, for example, As
Ions are implanted using ions at an implantation energy of 150 keV and a dose of about 8E12 / cm ² . After that, the LDD (Lightl
y DopedDrain) layer 17,
Ion implantation using ions serving as P-type impurities, for example, BF
_{Using two} ions, ion implantation is performed at an implantation energy of 10 keV and a dose of about 1E14 / cm ² .

Next, using a photoresist (not shown) patterned so as to cover the PMOS transistor portion 1 as a mask, the pocket diffusion layer 18 of the NMOS transistor portion 2 is formed by large-angle ion implantation.
Ion implantation with ions serving as P-type impurities, for example, using B ions, is performed at an implantation energy of 30 keV and a dose of about 4E12 / cm ² . afterwards,
For forming the LDD layer 19 of the NMOS transistor section 2, ion implantation with ions serving as N-type impurities, for example, using As ions, implantation energy of 10 keV,
Ion implantation is performed at a dose of about 4E13 / cm ² .
Next, after removing the photoresist (not shown), a heat treatment for activating the ions implanted into the semiconductor substrate 11 is performed.

Next, as shown in FIG. 1B, after depositing a CVD SiO ₂ film having a thickness of about 300 nm by the CVD method, the CVD SiO ₂ film is etched back by the anisotropic plasma etching method. And the gate electrode part 3,
A sidewall insulating film 20 is formed on the four side walls. next,
A photoresist 21 is applied, and the photoresist 21
Is patterned to remove the photoresist 21 of the PMOS transistor portion 1 and leave the photoresist 21 in the NMOS transistor portion 2 and the like.

Next, ion implantation for forming the source / drain layer 22 in the source / drain portion 5 of the PMOS transistor portion 1 is performed by ion implantation, for example, BF ₂ ions are used, implantation energy is 20 keV, and dose is 3E15 / Ion implantation is performed at about cm ² . On this occasion,
BF ₂ ions are also implanted into the polysilicon gate electrode 14 of the gate electrode part 3 of the PMOS transistor part 1,
Polysilicon gate electrode 1 of PMOS transistor section 1
Reference numeral 4 denotes a polysilicon gate electrode 14 containing a P-type impurity.

Next, as shown in FIG. 1 (c), after removing the photoresist 21, a new photoresist 23 is applied, and the photoresist 23 is patterned to
The photoresist 23 of the MOS transistor section 2 is removed, and the photoresist 2 of the PMOS transistor section 1 and the like is removed.
3 is left. Next, the source / drain layers 2 of the NMOS transistor portion 2 are formed by ion implantation.
Ion implantation, for example, using As ions, implantation energy of 50 keV, and dose of 3E15
/ Cm ^{2 is} implanted. At this time, NMOS
As ions are also implanted into the polysilicon gate electrode 14 of the gate electrode section 4 of the transistor section 2, and the polysilicon gate electrode 14 of the NMOS transistor section 2 becomes the polysilicon gate electrode 14 containing N-type impurities.

Next, as shown in FIG. 2D, after removing the photoresist 23, a heat treatment for activating the ion-implanted B ions or As ions of the source / drain portions 5 and 6, for example, RTA (Rapid Thermal)
Annealing) method at 1000 ° C. for 10 seconds
Heat treatment of about c is performed. Next, the source / drain layers 2 of the PMOS transistor section 1 and the NMOS transistor section 2
Group IV atoms and V
Compound ions with Group II atoms, for example, SiF ions, are implanted, and the surfaces of the source / drain layers 22 and 24 are amorphized. The conditions for the implantation of the SiF ions are, for example, an implantation energy of 15 keV and a dose of 5E15 /
cm ² .

Next, as shown in FIG. 2E, a refractory metal film or a composite film in which a refractory metal nitride film is laminated on a refractory metal nitride film, for example, a Co film 25 by a sputtering method.
Is deposited to a thickness of about 10 nm.

Next, as shown in FIG. 2F, first, a heat treatment at a relatively low temperature, for example, a heat treatment at about 500 ° C. for about 60 seconds by an RTA method in an N ₂ gas atmosphere. By this heat treatment, the PMOS transistor section 1 and the NMOS
Surfaces of source / drain layers 22 and 24 of transistor portion 2 and polysilicon gate electrodes 1 of gate electrode portions 3 and 4
4 The silicon on the surface reacts with the Co film 25,
A CoSi ₂ film including a CoSi film which is a refractory metal silicide film is formed on the surfaces of the drain layers 22 and 24 and the surfaces of the polysilicon gate electrodes 14 of the gate electrode portions 3 and 4. The resistivity of this CoSi film does not become the expected low resistivity but is still in a high resistance state. Next, a Co film 25 deposited on the LOCOS film 13, the sidewall insulating film 20, or the like, which does not react with the insulating film by the heat treatment at a relatively low temperature,
The so-called unreacted Co film 25 is removed with a sulfuric acid peroxide solution.

Next, a high-temperature heat treatment, for example, a heat treatment at 800 ° C. for about 30 seconds by an RTA method in an N ₂ gas atmosphere. By this high-temperature heat treatment, the above-described high-resistance Co on the surfaces of the source / drain layers 22 and 24 and the surface of the polysilicon gate electrode 14 of the gate electrode portions 3 and 4 are formed.
The Si film is made to have a desired low resistivity, and the source / drain layer 2 is formed.
CoSi ₂ films 26, 27, 28, and 29, which are low-resistance, high-melting metal silicide films, are formed on the surfaces 2, 24 and the surfaces of the polysilicon gate electrodes 14 of the gate electrode portions 3, 4. The method described above, that is, the source / drain layers 22 and 24
A low-resistance CoSi ₂ film 26, ₂ is self-aligned on the surface or the surface of the polysilicon gate electrode 14 of the gate electrode portions 3, 4.
By forming a MOS transistor using a method of forming a refractory metal silicide film such as 7 and 28, 29, etc., a so-called salicide method, the source / drain layer 22,
The MOS transistor with good frequency characteristics is formed by reducing the resistance of the diffusion layer and the gate electrode of 24 parts.

Thereafter, although not shown in the drawings, deposition of an interlayer insulating film, formation of contact holes such as source / drain portions 5 and 6, formation of wiring, deposition of a passivation film, and opening of a pad portion are performed by a manufacturing method according to a conventional method. A semiconductor device is manufactured by performing formation and the like.

The above-described NMOS transistor and PMOS
In a method of manufacturing a highly integrated semiconductor device of a dual gate CMOS type including a transistor, after forming source / drain layers 22 and 24, ion implantation using SiF ions is performed to form source / drain layers 22 and 24. 24 and the polysilicon gate electrode 14 of the gate electrode portions 3 and 4
The surface is made amorphous, and then the surfaces of the source / drain layers 22 and 24 and the gate electrode portion 3,
CoSi ₂ film 2 on the surface of polysilicon gate electrode 14
6, CoSi ₂ films 26, 27 and 28, 29 having desired low resistivity can be obtained even in MOS transistors having a minimum processing dimension of quarter micron or less. Therefore, an NMOS transistor or a PMOS transistor having good frequency characteristics can be obtained.

In addition, F atoms in SiF ions implanted for amorphousization hinder pair formation of interstitial Si and B, and suppress high-speed diffusion of B. At the time of the heat treatment, an increase in the junction depth of the source / drain layer 22 of the PMOS transistor portion 1 is suppressed, and the effect of suppressing the short channel effect of the pocket diffusion layer 18 is maintained. Of the pocket diffusion layer 16 due to the accelerated diffusion is also suppressed, and a decrease in the short channel effect suppressing effect is suppressed. Therefore, both the PMOS transistor and the NMOS transistor can be prevented from lowering the threshold voltage and lowering the punch-through breakdown voltage.

Embodiment 2 This embodiment is an example in which the present invention is applied to a method of manufacturing a highly integrated semiconductor device of a dual gate CMOS type including a PMOS transistor and an NMOS transistor. Since the processing method for amorphization is different from that of the first embodiment, this will be described with reference to FIGS. 1 and 2 and FIG. 3 which are used in the first embodiment.

The method of manufacturing the semiconductor device of the present embodiment is similar to that of the first embodiment described with reference to FIG.
Since the process proceeds to the step shown in FIG. 1C in a state where the source / drain layers 22 and 24 of the S transistor portion 2 are formed,
The description of the manufacturing method during this time is omitted.

Next, as shown in FIG. 3 corresponding to FIG. 2D, after removing the photoresist 23 shown in FIG.
Heat treatment for activating B ions or As ions implanted into the source / drain portions 5 and 6, for example, RTA
(Rapid Thermal Annealing)
According to the method, heat treatment is performed at 1000 ° C. for about 10 seconds. Next, compound ions of group IV atoms and group VII atoms, for example, SiF ions are implanted into the surfaces of the source / drain layers 22 and 24 of the PMOS transistor unit 1 and the NMOS transistor unit 2 by a large tilt ion implantation method. Amorphizing the surfaces of the drain layers 22 and 24. The conditions for implanting SiF ions by the large-angle ion implantation method are as follows.
Ion implantation divided into ^two steps toward one side wall and the other side wall of the gate electrode portions 3 and 4 in the channel direction of the transistor, for example, under the ion implantation conditions of implantation energy of about 25 keV and dose of about 3E15 / cm ^2. Perform ion implantation twice.

When the PMOS transistors 1 and the NMOS transistors 2 of the semiconductor device are arranged so that the channel directions of the MOS transistors are orthogonal to each other, a dose amount obtained by dividing a dose amount of about 5E15 / cm ² into four equal parts. Then, ion implantation divided into four degrees is performed toward both side walls of the gate electrode portions 3 and 4.

Thereafter, the surfaces of the source / drain layers 22 and 24 and the polysilicon gate electrode 14 are formed by the same manufacturing method as described with reference to FIGS. 2E and 2F of the first embodiment. CoSi ₂ film 2 with low resistance on the surface
6, 27, 28, and 29, the description is omitted to proceed. After that, although not shown in the drawings, the deposition of an interlayer insulating film, the formation of contact holes for the source / drain portions 5, 6 and the like, the formation of wiring, the deposition of a passivation film, the formation of an opening in a pad portion, etc. To manufacture a semiconductor device.

The above-described PMOS transistor and NMOS
In the method for manufacturing a highly integrated semiconductor device of a dual gate CMOS type including a transistor, the effect of suppressing the enhanced diffusion described in the first embodiment is improved by the side wall insulating film 2.
This is more effective for values below 0, and the reduction in threshold voltage and the reduction in punch-through breakdown voltage are further suppressed. Also,
Source / drain layers 22, 24 described in the first embodiment
The effect of reducing the resistance of the diffusion layer is further improved, and the frequency characteristics of the MOS transistor are further improved. The reason for this is that the surface of the source / drain layers 22 and 24 is made amorphous by using SiF.
In the case of the first embodiment, which is performed by a method of ion implantation substantially perpendicular to the ions, the amorphized region extends to below the lower end of the sidewall insulating film 20, so that the CoSi ₂ film 26 having a reduced resistance, As shown in FIG. 4A, 27 is formed only below the lower end of the side wall insulating film 20. In this embodiment, however, the amorphization by SiF ion implantation using the large tilt ion implantation method is performed. In this case, since the amorphous region spreads toward the LDD layers 17 and 19 from below the lower end of the sidewall insulating film 20, the CoSi ₂ films 26 and 27 having reduced resistance are formed as shown in FIG. This is because it is formed to extend toward the LDD layers 17 and 19 from below the lower end of the sidewall insulating film 20. Since the main path of the current in the actual operation of the MOS transistor is near the interface of the sidewall insulating film 20, the presence of the low-resistance CoSi ₂ films 26 and 27 protruding on the surface of the source / drain layers 22 and 24 in this portion Has a greater effect on improving the frequency characteristics of the MOS transistor.

Although the present invention has been described with reference to the two embodiments, the present invention is not limited to these embodiments. For example, in the embodiment of the present invention, as a method of manufacturing a semiconductor device, a method of manufacturing a dual-gate CMOS type, highly integrated semiconductor device capable of reducing power consumption has been described as an example. It is apparent that the present invention can be applied to a method for manufacturing a highly integrated semiconductor device using a PMOS transistor as a constituent element and a method for manufacturing a highly integrated semiconductor device using a NMOS transistor having a pocket diffusion layer as a constituent element. Further, in the embodiment of the present invention, the film deposited on the source / drain layer when forming the refractory metal silicide film has been described as a Co film. However, a composite film in which a TiN film is laminated on a Co film may be used. ,
Further, it may be a Ti film, a Ni film, a composite film in which a TiN film is laminated on a Ti film or a Ni film, or the like.

Further, in the embodiment of the present invention, a method of manufacturing a semiconductor device in which a refractory metal silicide film is formed simultaneously on the source / drain layer surface and the polysilicon gate electrode surface using the salicide method has been described. But,
Manufacture of a semiconductor device in which the step of forming a gate electrode using a polysilicon gate electrode and a refractory metal silicide film, a so-called polycide gate electrode, and the step of forming a refractory metal silicide film on the surface of a source / drain layer are separate steps. Obviously, the present invention can be applied to a method. In addition, the process conditions can be appropriately changed within the scope of the technical idea of the present invention.

[0040]

As is clear from the above description, the method of manufacturing a semiconductor device according to the present invention is characterized in that the source / drain layer is formed and then the source is implanted by ion implantation using a compound ion of a group IV atom and a group VII atom.・ Since the drain layer surface is amorphized and then a high melting point metal silicide film is formed on the source / drain layer surface, even for MOS transistors with a minimum processing dimension of less than quarter microns, a low-resistance high melting point metal on the source / drain layer. At the same time as the silicide film can be easily formed, the enhanced diffusion of B by forming a pair of interstitial Si and B due to the heat treatment during the formation of the refractory metal silicide film is caused by the ion implantation into the source / drain layers.
Since it is suppressed by the group VII atom in the compound ions of the group atom and the group VII atom, an increase in the junction depth of the source / drain layers of the PMOS transistor and a decrease in the concentration of the pocket diffusion layer of the NMOS transistor can be suppressed. Accordingly, a decrease in the threshold voltage and the punch-through breakdown voltage is suppressed, and a semiconductor device having a MOS transistor with improved frequency characteristics as a constituent element can be manufactured.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a semiconductor device, illustrating the first half of the steps of a first embodiment of the present invention in the order of steps;
(A) shows a state in which a pocket diffusion layer and an LDD layer are formed, (b) shows a state in which BF ₂ ions for forming a source / drain layer of a PMOS transistor portion are implanted,
(C) shows a state in which As ions for forming the source / drain layers of the NMOS transistor portion are ion-implanted.

FIG. 2 is a schematic cross-sectional view of a semiconductor device, illustrating the latter half of the steps of the first embodiment to which the present invention is applied, in the order of steps;
(D) is a state in which SiF ions are implanted for amorphizing the surface of the source / drain layer, (e) is a state in which a Co film as a refractory metal film is deposited, and (f) is a surface of the source / drain layer. And a state in which a low-resistance CoSi ₂ film is formed on the surface of the polysilicon gate electrode.

FIG. 3 is a schematic cross-sectional view of a semiconductor device illustrating a process of a second embodiment corresponding to FIG. 2D of the first embodiment in the second embodiment of the present invention,・
This is a state in which SiF ions are ion-implanted by a large tilt ion implantation method for making the surface of the drain layer amorphous.

FIG. 4 shows that when the surface of the source / drain layer is made amorphous, the CoS on the source / drain layer surface is changed due to the difference in the amorphized region depending on the ion implantation angle of SiF ions.
FIG. 4A is a diagram showing the difference in the formation region of the i ₂ film, FIG. 4A is an enlarged view near the bottom of the sidewall insulating film when SiF ions are implanted substantially perpendicularly to a normal semiconductor substrate, and FIG. FIG. 5 is an enlarged view near the bottom of a sidewall insulating film when SiF ions are implanted by an implantation method.

FIGS. 5A and 5B are schematic cross-sectional views of a semiconductor device, illustrating the first half of the steps of a conventional method of manufacturing a semiconductor device in the order of steps; FIG. 5A shows a state in which a pocket diffusion layer and an LDD layer are formed;
FIG. 3B shows a state in which BF ₂ ions are implanted for forming source / drain layers in the PMOS transistor section, and FIG. 4C shows a state in which As ions are implanted for forming source / drain layers in the NMOS transistor section.

FIG. 6 is a schematic cross-sectional view of the semiconductor device, illustrating the latter half of the process of the conventional method of manufacturing a semiconductor device in the order of steps.
(E) a Co film as a high melting point metal film deposited, (f) a low resistance CoSi ₂ film formed on the source / drain layer surface and the polysilicon gate electrode surface. State.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... PMOS transistor part, 2 ... NMOS transistor part, 3,4 ... Gate electrode part, 5,6 ... Source / drain part, 11 ... Semiconductor substrate, 12 ... N well, 13 ... LO
COS film, 14: polysilicon gate electrode, 15: gate oxide film, 16, 18: pocket diffusion layer, 17, 19 ...
LDD layer, 20 ... sidewall insulating film, 21, 23 ...
Photoresist, 22, 24 ... source / drain layer, 2
5 Co film, 26, 27, 28, 29 CoSi ₂ film

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device, comprising: forming a refractory metal silicide film on the surface of a source / drain layer of a MOS transistor; forming the source / drain layer by an ion implantation method; -After formation of the drain layer, group IV atoms and VII
The step of amorphizing the surface of the source / drain layer by ion implantation using a compound ion with a group atom; and a high melting point metal film and a composite film in which a high melting point metal nitride film is laminated on the high melting point metal film. Depositing either one of the films, and forming a high-melting metal silicide film on the source / drain layer surface by reacting the high-melting metal film with silicon of the source / drain layer by heat treatment. A method for manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the ion implantation of the group IV atom and the group VII atom using the compound ion is an ion implantation by a large tilt ion implantation method. Method. 3. The method of manufacturing a semiconductor device according to claim 1, wherein said compound ions of Group IV atoms and Group VII atoms are SiF ions. 4. The method according to claim 1, wherein the high melting point metal film is one of a Co film, a Ti film, and a Ni film. 5. The semiconductor device according to claim 1, wherein said refractory metal nitride film of said composite film in which a refractory metal nitride film is laminated on a refractory metal film is a TiN film. Production method.