JP2001160621A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device for simplifying the control of the profile of the impurity of a pocket area, and for obtaining satisfactory transistor characteristics. SOLUTION: This method for manufacturing a semiconductor device comprises a process for forming a gate insulating film on the surface of a first conductive semiconductor substrate, a process for forming a gate electrode on the gate insulating film, a process for forming an amorphous layer at least on the surface of the semiconductor substrate, a process for forming a pocket area by introducing first conductive impurity into the surface of the semiconductor substrate, and a process for forming a source drain area by introducing second conductive impurity into the surface of the semiconductor substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a transistor.

[0002]

2. Description of the Related Art With the miniaturization of transistors, the short channel effect of transistors becomes a serious problem. In order to suppress the short channel effect, it is important to control an impurity profile in a well and a source / drain (hereinafter, SD) region. As one of the methods for controlling the impurity profile of the SD region, in the conventional method of manufacturing a semiconductor device, a method of introducing an impurity of a conductivity type opposite to that of the impurity in the SD region so as to surround the SD region is employed. It has been. It has been expected that the impurity in the pocket region formed in this way suppresses diffusion of the impurity in the SD region in the channel length direction, and as a result, functions to suppress the short channel effect.

[0003]

However, in the above-mentioned conventional method for manufacturing a semiconductor device, there is a problem that the impurity in the pocket region is likely to be redistributed into SD under the influence of the electric field of the SD impurity. . This phenomenon is caused by the sharp profile of As (arsenic), Sn
This phenomenon was particularly prominent in NMOS in which SD was formed by (antimony) or the like. Therefore, there is a problem that the effect of suppressing the short channel effect in the NMOS in particular is reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of such problems in the prior art, and is intended to provide a semiconductor device capable of easily controlling a profile of impurities in a pocket region and obtaining excellent transistor characteristics. It is intended to provide a manufacturing method.

[0005]

According to a first aspect of the present invention for solving the above-mentioned problems, there is provided a step of forming a gate insulating film on a surface of a semiconductor substrate of a first conductivity type, and forming a gate electrode on the gate insulating film. Forming an amorphous layer on at least the semiconductor substrate surface, introducing a first conductive type impurity into the semiconductor substrate surface to form a pocket region, and forming a second pocket region on the semiconductor substrate surface. Forming a source / drain region by introducing impurities of a conductivity type. As described above, according to the method for manufacturing a semiconductor device of the first invention of the present application, an amorphous layer is formed in a pocket region before the pocket region is formed. As a result, impurities in the pocket region are attracted to the amorphous / Si (silicon) interface, so that impurities in the pocket region are reduced to SD.
It becomes possible to suppress the phenomenon of redistribution inside. Therefore, it is possible to easily control the profile of the impurity in the pocket region and to obtain good transistor characteristics.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect of the present invention, the step of forming the amorphous layer is performed by introducing Ge (germanium). And in this way,
According to the method of manufacturing a semiconductor device of the second invention of the present application, G
The amorphous layer is formed by introducing e. Therefore, the activation rate of the SD impurity can be improved, and the resistance of the SD can be reduced.
Therefore, there is an advantage that good transistor characteristics can be obtained.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the second aspect of the present invention, the step of forming the pocket region is performed by introducing In (indium). And That is, according to the semiconductor device manufacturing method of the third invention of the present application, an amorphous layer is formed by introducing Ge,
To form a pocket region. As described above, according to the method of manufacturing a semiconductor device of the third invention of the present application, although the short channel effect is highly suppressed, when the pocket region is formed of In which is likely to be redistributed into SD, In Before the introduction of Ge, Ge is introduced to form an amorphous layer. Therefore, since the phenomenon of redistribution of In into SD can be suppressed, it is possible to obtain good transistor characteristics with a small short-channel effect. Further, variation in characteristics of the transistor due to temperature can be reduced.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the first to third aspects of the present invention, the step of forming the amorphous layer is performed by an ion implantation method. It is characterized by. Thus, according to the method for manufacturing a semiconductor device of the fourth invention of the present application, the amorphous layer is formed by an ion implantation method in which the surface of the semiconductor substrate is likely to be amorphized. Therefore, the effect of attracting impurities in the pocket region to the amorphous / Si interface can be enhanced, and the effect of suppressing the phenomenon in which the impurities in the pocket region are redistributed in SD increases. Therefore, control of the profile of the impurity in the pocket region is further facilitated, and good transistor characteristics can be obtained.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the first to fourth aspects of the present invention, the step of forming the amorphous layer is performed by implanting Ge by ion implantation at 5E13 cm−. It is characterized by being implemented by introducing at an implantation dose of two or more. According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the first to fifth aspects of the present invention, the step of forming the amorphous layer includes the step of forming Ge by ion implantation at 5k.
It is characterized by being implemented by introducing with an implantation energy of eV or more. As described above, according to the method of manufacturing a semiconductor device of the fifth or sixth invention of the present application, the amorphous layer has an implantation dose of 5E13 cm−2 or more, or 5 keV or more, in which the surface of the semiconductor substrate tends to be amorphized. It is formed by ion implantation under the condition of implantation energy. Therefore, the effect of attracting impurities in the pocket region to the amorphous / Si interface can be enhanced, and the effect of suppressing the phenomenon in which the impurities in the pocket region are redistributed in SD increases. Therefore, control of the profile of the impurity in the pocket region is further facilitated, and good transistor characteristics can be obtained.

[0010]

Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2 are process diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention. First, FIG.
As shown in FIG. 1, a CMP (Chemical mechanical) is formed on a semiconductor substrate 1 made of, for example, Si (silicon).
The trench element isolation 2 is formed by an electrical polishing method. Subsequently, a predetermined P
An n-well (not shown) and a p-well (not shown) are formed in the MOS region 3 and the NMOS region 4, respectively. Next, a gate insulating film 5 made of, for example, a thermal oxide film is grown to a thickness of, for example, 3 nm, and polysilicon for the gate electrode 6, for example, is deposited by CVD (Chemical Vapor Depth).
For example, it is grown to a thickness of 150 nm by the position method.
Next, a resist mask (not shown) is applied on the entire surface and KR
After exposure with an F stepper, development is performed and the resist mask is patterned. Thereafter, the polysilicon is etched back by dry etching using the resist mask as a mask to form a gate electrode 6.

Next, as shown in FIG.
The region 3 is covered with a resist mask 7, and an amorphous layer 8 is formed on the surface of the semiconductor substrate 1 in the NMOS region 4. The step of forming the amorphous layer 8 is desirably performed by an ion implantation method from the viewpoint of the possibility that the surface of the semiconductor substrate 1 becomes amorphous. The step of forming the amorphous layer 8 includes Ge (germanium), Si, Ar
(Argon), etc.
It is desirable to perform the process by introducing Ge from the viewpoint of improving the activation rate of source / drain (hereinafter, SD) impurities. From the above viewpoint, the step of forming the amorphous layer 8 is desirably performed by introducing Ge by an ion implantation method. At this time, the implantation energy is 5 keV or more and the implantation dose is 5E1 because the surface of the semiconductor substrate 1 is more likely to become amorphous.
It is desirably 3 cm-2 or more. In this case, for example, the implantation energy is 30 keV and the implantation dose is 5E14c.
G by ion implantation by m-2, rotation implantation at an angle of 30 degrees
e.

Subsequently, a p-type impurity is introduced into the surface of the semiconductor substrate 1 in the NMOS region 4 to form an NMOS pocket region 9. Here, the step of forming the amorphous layer 8 is G
e, and the step of forming the pocket region 9 of the NMOS region 4 is preferably performed by introducing In (indium) using an ion implantation method or the like. In has a high effect of suppressing the short channel effect, but has a feature that redistribution into SD is likely to occur. Therefore, by introducing Ge before the introduction of In to form an amorphous layer, the phenomenon of redistribution of In into SD can be suppressed, and the short channel effect of the transistor can be suppressed. . further,
Variations in transistor characteristics due to temperature can also be reduced. In this case, for example, an injection energy of 100 k
In is introduced by ion implantation by eV, implantation dose of 1E13 cm−2, and rotation implantation at an angle of 30 °. afterwards,
For example, an n-type impurity such as As (arsenic) is introduced by ion implantation at an implantation energy of 5 keV, an implantation dose of 5E14 cm−2, and an angle of 0 ° to form an NMOS SD region 10 on the surface of the semiconductor substrate 1 in the NMOS region 4. I do.

Next, as shown in FIG. 1C, the resist mask 7 is removed, and the NMOS region 4 is removed from the resist mask 1.
Cover with 1. Thereafter, for example, n (antimony) or the like
A type impurity is introduced by, for example, an ion implantation method using rotational implantation at an implantation energy of 200 keV, an implantation dose of 1E13 cm −2, and an angle of 30 ° to form a PMOS pocket region 12 on the surface of the semiconductor substrate 1 in the PMOS region 3.
Thereafter, a p-type impurity such as BF2 (boron fluoride) is implanted at an implantation energy of 5 keV and an implantation dose of 5E, for example.
14 cm-2, introduced by ion implantation at an angle of 0 degree,
A PMOS SD region 13 is formed on the surface of the semiconductor substrate 1 in the PMOS region 3.

Next, as shown in FIG. 1D, after removing the resist mask 11, an oxide film 14 is formed by, for example, a CVD method.
Is grown to 100 nm. Subsequently, as shown in FIG. 1E, etch back is performed by dry etching to form a sidewall 15. Next, as shown in FIG. 2F, the PMOS region 3 is covered with the resist mask 16 again. Thereafter, an n-type impurity such as As is introduced by, for example, ion implantation at an implantation energy of 30 keV, an implantation dose of 5E15 cm−2, and an angle of 0 °, and the NMOS Deep-SD region 17 is formed on the surface of the semiconductor substrate 1 in the NMOS region 4.
To form Next, as shown in FIG. 2G, the resist mask 16 is removed, and the NMOS region 4 is covered with a resist mask 18. Thereafter, a p-type impurity such as B (boron) is introduced by, for example, ion implantation at an implantation energy of 3 keV, an implantation dose of 5E15 cm−2, and an angle of 0 °, and a PMOSD is introduced into the surface of the semiconductor substrate 1 in the PMOS region 3.
An eep-SD region 19 is formed.

Next, as shown in FIG. 2H, after removing the resist mask 18, the gate electrode 6, the NMOS SD
Region 10, PMOSSD region 13, NMOS Deep
A heat treatment for activating impurities in each of the -SD region 17 and the PMOS Deep-SD region 19 is performed. This activation heat treatment is performed, for example, at 1000 ° C. for 10 seconds at an oxygen concentration of 1%.
RTA (Rapid Thermal Annea)
1) The method is performed. Then, for example, a 10 nm thick C
o (cobalt) is sputtered over the entire surface of the wafer. Further, a heat treatment for silicidizing Co is performed, and the gate electrode 6, the NMOS deep-SD region 17, the PMOS
Cobalt silicide 20 on Deep-SD region 19
To form Excess Co in other areas is removed by a wet process. The heat treatment for silicidation
For example, a heat treatment by an RTA method at 700 ° C. for 30 seconds and a nitrogen concentration of 100%, and a heat treatment at 750 ° C. for 30 seconds and a nitrogen concentration of 1
This is performed by sequentially performing a heat treatment by the RTA method of 00%. Thereafter, a contact is formed after growing an interlayer film by a method similar to the conventional method of manufacturing a semiconductor device,
A transistor is formed through a wiring process.

In the embodiment described above, the step of forming the amorphous layer 8 may be performed before the PMOS region 3 is covered with the resist mask 7. In this case P
An amorphous layer 8 is also formed on the surface of the semiconductor substrate 1 in the MOS region 3. The semiconductor substrate 1 includes an SOI (Silicon on Insulato) in addition to the Si substrate.
r) Substrates or epi-substrates may be used. An oxynitride film may be used for the gate insulating film 5 in addition to the thermal oxide film. In forming the NMOS pocket region 9, B,
BF2 may be used, and the PMOS pocket region 12 may be used.
In some cases, As and P (phosphorus) are used for the formation. Further, the NMOS SD region 10 and the NMOS Deep-SD
In addition to As, the region 17 may be formed by ion implantation of P, Sn, As2 (double arsenic), P2 (double phosphorus), or a mixture thereof. The PMOS SD region 13 may be formed of B. PMOS De
The ep-SD region 19 may be formed of BF2.
The sidewall 15 may have a two-layer or three-layer structure of an oxide film and a nitride film formed by a CVD method in addition to a single oxide film formed by a CVD method. It is desirable to carry out the activation heat treatment at an oxygen concentration in the range of 0.05 to 1%. Gate electrode 6, NMOS Deep-SD region 1
7. For silicidation on the PMOS Deep-SD region 19, Ti (titanium), Ni (nickel) in addition to Co are used.
May be used.

[0017]

As described above, according to the method of manufacturing a semiconductor device in the embodiment of the present invention, the following advantages can be obtained. By forming an amorphous layer in the pocket region before forming the pocket region, impurities in the pocket region are attracted to the amorphous / Si interface, so that the phenomenon of redistribution of impurities in the pocket region into SD can be suppressed. become. Therefore, the profile of the impurity in the pocket region can be easily controlled, and good transistor characteristics can be obtained. By adjusting the conditions for forming the amorphous layer so that the position of the amorphous / Si interface overlaps the position of the peak of the impurity profile in the pocket region, the peak of the impurity profile in the pocket region can be obtained. Further, there is an advantage that the profile of the impurity in the pocket region formed in this manner is hardly fluctuated even after a subsequent heat treatment or the like.

[Brief description of the drawings]

FIG. 1 is a process chart of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process chart of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

DESCRIPTION OF REFERENCE NUMERALS 1 semiconductor substrate 2 trench element isolation 3 PMOS region 4 NMOS region 5 gate insulating film 6 gate electrode 7, 11, 16, 18 resist mask 8 amorphous layer 9 NMOS pocket region 10 NMOS SD region 12 PMOS pocket region 13 PMOSSD Region 14 Oxide film 15 Sidewall 17 NMOS Deep-SD region 19 PMOS Deep-SD region 20 Cobalt silicide

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F040 DB03 DC01 EC01 EC04 EC07 EC13 EF02 EH02 EK05 EM01 EM02 EM03 FA03 FA05 FA07 FA10 FA19 FB02 FB04 FC13 FC14 FC15 FC19 5F048 AC03 BA01 BB05 BB08 BB12 BC05 DA30

Claims (6)

[Claims] 1. A step of forming a gate insulating film on a surface of a semiconductor substrate of a first conductivity type, a step of forming a gate electrode on the gate insulating film, and a step of forming an amorphous layer on at least the surface of the semiconductor substrate Forming a pocket region by introducing an impurity of a first conductivity type into the surface of the semiconductor substrate; and forming a source / drain region by introducing an impurity of a second conductivity type into the surface of the semiconductor substrate. A method for manufacturing a semiconductor device, comprising: 2. The step of forming the amorphous layer,
2. The method for manufacturing a semiconductor device according to claim 1, wherein the method is performed by introducing Ge (germanium). 3. The step of forming the pocket region comprises the steps of:
The method according to claim 2, wherein the method is performed by introducing n (indium). 4. The step of forming the amorphous layer,
4. The method of manufacturing a semiconductor device according to claim 1, wherein the method is performed by an ion implantation method. 5. The method of forming an amorphous layer according to claim 1, wherein:
5. The method according to claim 1, wherein the method is performed by introducing e by an ion implantation method at an implantation dose of 5E13 cm −2 or more. 6. 6. The step of forming the amorphous layer comprises the steps of:
6. The method of manufacturing a semiconductor device according to claim 1, wherein the method is performed by introducing e by ion implantation at an implantation energy of 5 keV or more.