JPH11163336A - Semiconductor device - Google Patents

Abstract

(57) [Summary] In a high breakdown voltage semiconductor device, a parasitic bipolar transistor operates, and the characteristics of the semiconductor device deteriorate. A medium-concentration P ⁻ -type diffusion layer is formed in a low-concentration P ⁻ -type electric field relaxation layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a structure of a semiconductor device having a high withstand voltage specification.

[0002]

2. Description of the Related Art FIG. 6 shows a sectional structure of a conventional high voltage PMOSFET. In the figure, a low-concentration N ⁻ -type well diffusion layer 6 on a P-type semiconductor substrate
⁺ -Type drain diffusion layer 1, LOCOS oxide film 2, low-concentration P ⁻ -type electric field relaxation layer 3, gate electrode 4 made of polysilicon 4, P ⁺ -type source diffusion layer 5, low-concentration N ⁻ -type well diffusion layer 6 , And a gate oxide film 9 are formed to constitute a semiconductor device.

In this structure, the breakdown voltage can be easily increased by determining the concentration and the distance of the low-concentration N ⁻ -type well diffusion layer 6 and the low-concentration P ⁻ -type electric field relaxation layer 3. . For a transistor having a maximum rating of 150 V, the distance between the low-concentration P ⁻ -type electric field relaxation layer 3, that is, the distance from the right end of the P ⁺ -type drain diffusion layer 1 to the right end of the P ⁻ -type electric field relaxation layer 3 is about 16 μm.

Generally, in order to switch a capacitive load such as a PDP driver IC or an EL driver IC, an off-state breakdown voltage is, of course, necessary. However, in addition to the on-state breakdown voltage, that is, a working voltage is applied to the gate electrode. In this condition, a withstand voltage exceeding the rating must be secured.

However, the withstand voltage in the off state of the transistor having the conventional structure is designed to have an over-margin with respect to 220 V and the target withstand voltage of 180 V. The reason is,
The withstand voltage in the ON state is as low as 160 V. When the low-concentration P ⁻ -type electric field relaxation layer distance 3 is 16 μm, the withstand voltage in the ON state is 160 V. When the MOS transistor is on, the parasitic lateral PNP bipolar transistor formed by the concentration of the P-type drain diffusion layers 1 and 3 and the low-concentration N ⁻ -type well diffusion layer 6 and the P ⁺ -type source diffusion layer 5 is turned on, and a current flows. . As a countermeasure, the distance between the low-concentration P ⁻ -type electric field relaxation layers 3 is increased to make it difficult to turn on the parasitic bipolar transistor.

[0006]

However, by increasing the distance of the low-concentration P ⁻ -type electric field relaxation layer 3, the on-resistance is increased and the size of the transistor must be increased to satisfy the required on-current. The performance deteriorated.

The present invention has been made to solve the above problems,
It is intended to suppress the bipolar action in the ON state and improve the performance of the transistor.

[0008]

According to the present invention, there is provided a semiconductor device comprising:
A first conductivity type semiconductor substrate, a gate electrode formed on the substrate via a gate oxide film, and a second conductivity type source diffusion layer and a drain diffusion layer formed on the substrate on both sides of the gate electrode. A semiconductor element comprising a second conductive type low-concentration diffusion layer for lowering the electric field reaching below the gate oxide film at a bottom portion of the drain diffusion layer; A second conductivity type medium concentration diffusion layer for electric field relaxation is formed in the diffusion layer.

[0009]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of a semiconductor chip for describing an embodiment of the present invention.

Referring to FIG. 1, a semiconductor device having a high withstand voltage specification according to the present invention includes a P ⁺ type drain diffusion layer 1, a LOCOS oxide film 2, and a P ⁺ type diffusion layer 6 formed on an N ⁻ well diffusion layer 6 on a P type semiconductor substrate 7. Low-concentration P ⁻ -type source diffusion layer 3, gate electrode 4, P ⁺ -type source diffusion layer 5, medium-concentration P ⁻ -type diffusion layer 8 formed in P ⁻ -type electric field relaxation layer 3 and gate oxide film 9 It is mainly composed of

According to the structure described above, the maximum rating is 150 V
The distance of the low-concentration P ⁻ -type electric field relaxation layer 3 in the transistor of
It is 16 μm as in the structure of the conventional example shown in FIG.
Since there is a middle concentration diffusion layer 8 having a concentration approximately one digit higher than that of the low concentration P ⁻ -type electric field relaxation layer 3, the breakdown voltage in the off state is equal to that of the conventional example.
The over-margin is reduced from 20 V to 180 V. The medium-concentration P ⁻ -type diffusion layer 8 formed in the low-concentration P ⁻ -type electric field relaxation layer 3 from the end of the P ⁺ -type drain diffusion layer 1 to 2 μm from the end of the conventional example has a breakdown voltage of 160 V from the conventional example.
It is possible to increase about 40V to 00V.

Embodiment 1 Next, the present invention will be described based on an embodiment. FIG.
P ⁺ -type drain diffusion layer 1, LOCOS oxide film 2, low-concentration P ⁻ -type electric field relaxation diffusion layer Gate electrode 4 made of polysilicon, P ⁺ -type source diffusion layer 5, N ⁻ -type well diffusion layer 6, P
1 shows a semiconductor device mainly including a semiconductor substrate 7, a medium-concentration P − -type diffusion layer 8 formed in a low-concentration P ⁻ -type electric field relaxation layer 3, and a gate oxide film 9. The low-concentration P ⁻ -type electric field relaxation layer 3 plays the same role as in the conventional example. That is, P
^The voltage applied between the ⁺ -type drain diffusion layer 1 and the source diffusion layer 5 is the N ⁻ -type well diffusion layer 6, the low-concentration P ⁻ -type electric field relaxation layer 6 and the low-concentration P ⁻ -type electric field relaxation layer 3. It is shared by the depletion layer that extends to the part. A feature of the present invention is that a medium-concentration P ⁻ -type diffusion layer 8 is provided.

The medium-concentration P ⁻ -type diffusion layer 8 is formed to suppress the bipolar action in the ON state, and the breakdown voltage in the ON state of the conventional example can be improved from 160 V to 200 V. Further, the provision of the medium-concentration P ^- type diffusion layer 8 lowers the on-resistance and improves the performance of the transistor. It is needless to say that the present invention can be applied not only to the above-mentioned P-type semiconductor substrate but also to an N-type semiconductor substrate of the opposite conductivity type. The same applies when an N-type epitaxial layer is formed on the P-type semiconductor substrate 7 instead of forming the N ^- type well diffusion layer 6.

Embodiment 2 FIG. 2 shows an N ⁺ type drain diffusion layer 10, a LOCOS oxide film 2, a low concentration N ⁻ type electric field relaxation diffusion layer 11, a gate electrode 3,
It mainly comprises an N ⁺ type source diffusion layer 12, a P type semiconductor substrate 7, a medium concentration N ⁻ type diffusion layer 13 formed in a low concentration N ⁻ type electric field relaxation layer 11, and a gate oxide film 9. 1 shows a semiconductor device according to the present invention. The low-concentration N ⁻ -type electric field relaxation layer 11 plays the same role as in the conventional example. That is, the voltage applied between the N ⁺ -type drain diffusion layer 10 and the source diffusion layer 12 is shared by the depletion layer extending to the P-type semiconductor substrate 7 and the low-concentration N ⁻ -type electric field relaxation layer 11. . A feature of the present invention is that a medium-concentration N ⁻ -type diffusion layer is provided.

The medium-concentration N ⁻ -type diffusion layer 13 is formed to suppress the bipolar action in the ON state, and it is possible to increase the breakdown voltage in the ON state from 160 V to 200 V in the conventional example. Also, the provision of the medium-concentration N ^- type diffusion layer 13 lowers the on-resistance and improves the performance of the transistor. It is needless to say that the present invention can be applied not only to the above-described P-type semiconductor substrate but also to an N-type semiconductor substrate of the opposite conductivity type.

Embodiment 3 FIG. 3 shows a P ⁺ type drain diffusion layer 1, a LOCOS oxide film 2, a low concentration P ⁻ type electric field relaxation diffusion layer 3, a gate electrode 4,
^- type source diffusion layer 5, N ^- -type well diffusion layer 6, the buried oxide film 21, P-type supporting substrate 20, a low concentration of P ^- in that formed in the mold field relaxation layer 3 concentration of P ^- -type diffusion 1 shows a semiconductor device mainly including a layer 8 and a gate oxide film 9.

The low-concentration P ⁻ -type electric field relaxation layer 3 plays the same role as in the conventional example. In the third embodiment shown here, the semiconductor substrate of the first embodiment shown in FIG. 1 is changed from a P-type semiconductor substrate to a dielectric isolation substrate having a buried oxide film 21. The operation is the same as in the first embodiment. In addition, the same effect is obtained when an N-type epitaxial layer is formed instead of the N ⁻ -type well diffusion layer 6 in the third embodiment.

Embodiment 4 FIG. 4 shows an N ⁺ type drain diffusion layer 10, a LOCOS oxide film 2, a low concentration N ⁻ type electric field relaxation diffusion layer 11, a gate electrode 4, an N ⁺ type source diffusion layer 12, a P type It mainly comprises a semiconductor substrate 7A, a buried oxide film 21, a P-type support substrate 20, a medium-concentration N ⁻ -type diffusion layer 13 formed in a low-concentration N ⁻ -type electric field relaxation layer 11, and a gate oxide film 9. 1 shows a completed semiconductor device.

The low-concentration N ⁻ -type electric field relaxation layer 11 plays the same role as in the conventional example. In the fourth embodiment shown here, the semiconductor substrate of the second embodiment shown in FIG. 2 is changed from a P-type semiconductor substrate to a dielectric isolation substrate having a buried oxide film 21.
The operation is the same as in the second embodiment.

Embodiment 5 FIG. 5 shows a P ⁺ type drain diffusion layer 1, a LOCOS oxide film 2, a low concentration P ⁻ type electric field relaxation diffusion layer 5, an N ⁻ type well diffusion layer 6, a buried oxide film 21, On a dielectric isolation substrate composed of a P-type support substrate 20, a medium-concentration P ^-- type diffusion layer 8, a gate oxide film 9, and a P-type semiconductor substrate 7A formed in a low-concentration P ^-- type electric field relaxation layer 3. 1 shows a semiconductor device produced.

The low-concentration P ⁻ -type electric field relaxation layer 3 plays the same role as in the conventional example. That is, the voltage applied between the P ⁺ -type drain diffusion layer 1 and the source diffusion layer 5 depends on the portion of the N ⁻ -type well diffusion layer 6, the portion of the low-concentration P ⁻ -type electric field relaxation layer 3, and the P-type semiconductor substrate 7A. Is shared by the depletion layer. The feature of the present invention is that the medium-concentration P ⁻ -type diffusion layer 8 is formed.
That is, The medium-concentration P ^- type diffusion layer 8 is formed to suppress the on-state bipolar action,
It is possible to increase the breakdown voltage in the ON state of the conventional example from 160 V to 200 V. Also, the provision of the medium-concentration P ⁻ -type diffusion layer 8 lowers the on-resistance and improves the performance of the transistor.

It should be noted that the present invention is not limited to the above-described P-type support substrate, but can be applied to an N-type support substrate of the opposite conductivity type.

[0023]

As described above, according to the present invention, a medium-concentration diffusion layer is formed in a low-concentration and high-breakdown-voltage electric field relaxation layer to reduce the over-margin in the off-state of the transistor, thereby reducing the on-state in the on-state. Since the bipolar action can be suppressed, the transistor breakdown voltage can be improved.

Further, by forming a medium-concentration diffusion layer in the low-concentration and high-breakdown-voltage electric field relaxation layer, the on-resistance can be reduced, and the performance of the transistor can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a transistor according to an embodiment (Example 1) of the present invention (P-channel semiconductor device).

FIG. 2 is a cross-sectional view of a transistor according to a second embodiment of the present invention (N-channel semiconductor device).

FIG. 3 is a cross-sectional view of a transistor according to a third embodiment of the present invention (a P-channel semiconductor device manufactured on a dielectric isolation substrate).

FIG. 4 is a cross-sectional view of a transistor according to a fourth embodiment of the present invention (an N-channel semiconductor device manufactured on a dielectric isolation substrate).

FIG. 5 is a sectional view of a transistor according to a fifth embodiment of the present invention (a P-channel semiconductor device manufactured on a dielectric isolation substrate).

FIG. 6 is a cross-sectional view of a transistor according to a conventional example (P-channel semiconductor device).

[Explanation of symbols]

Reference Signs List 1 P ⁺ type drain diffusion layer 2 LOCOS oxide film 3 P ⁻ type electric field relaxation diffusion layer 4 Gate electrode 5 P ⁺ type source diffusion layer 6 N ⁻ type well diffusion layer 7, 7A P type semiconductor support substrate 8 P ⁻ type diffusion Layer 9 Gate oxide film 10 N ⁺ type drain diffusion layer 11 N ⁻ type electric field relaxation layer 12 N ⁺ type source diffusion layer 13 N ⁻ type diffusion layer 20 P type support substrate 21 embedded oxide film

Claims (3)

[Claims] 1. A semiconductor substrate of a first conductivity type, a gate electrode formed on the substrate via a gate oxide film, and a source diffusion layer of a second conductivity type formed on the substrate on both sides of the gate electrode. A semiconductor element comprising: a drain diffusion layer; and a second conductivity type low-concentration diffusion layer for lowering the electric field reaching below the gate oxide film at the bottom of the drain diffusion layer. A semiconductor device, wherein a second-conductivity-type medium-concentration diffusion layer for reducing an electric field is formed in a two-conductivity-type low-concentration diffusion layer. 2. The semiconductor device according to claim 1, wherein the semiconductor element is formed on a dielectric isolation support substrate. 3. The semiconductor device according to claim 1, wherein the semiconductor element is formed on an epitaxial substrate.