JPH11160732A - TFT array substrate, liquid crystal display device using the same, and method of manufacturing TFT array substrate - Google Patents

Abstract

[PROBLEMS] To provide a liquid crystal display device having a high aperture ratio and excellent display quality at a high yield by preventing the occurrence of linear display defects caused by disconnection or short circuit of a TFT array substrate. SOLUTION: After a metal film such as Cr is formed on the surface of a glass substrate 1, patterning is performed to form a gate electrode and a wiring 2, a redundant wiring 3 and a branch-like auxiliary capacitance electrode 4 as shown in FIG. I do. At this time, after exposing with an appropriate exposure amount using a mask pattern serving as a design resist pattern, exposure is performed again using a mask pattern that is about 3 μm thicker than the design resist and with energy about 2 to 10 times the appropriate exposure amount. . According to this structure, a disconnection occurs due to a defect at the time of patterning or peeling of the resist at the time of etching.
Occurs, the signal can be transmitted through the redundant wiring 3. Even when the pattern defect 15 occurs, a short circuit does not occur unless the pattern defect 15 occurs near the tip of the auxiliary capacitance electrode 4 on the branch.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a TFT array substrate on which a thin film transistor is mounted as a switching element, a liquid crystal display device using the same, and a method of manufacturing the TFT array substrate.

[0002]

2. Description of the Related Art FIG. 13A is a plan view of a gate layer of a TFT array substrate constituting a conventional liquid crystal display device employing a common auxiliary capacitance system. In the figure, reference numeral 2 denotes a gate electrode and a wiring, 4 denotes an auxiliary capacitance electrode, and 19 denotes a common wiring. In the conventional liquid crystal display device of the common auxiliary capacitance type aiming at a high aperture ratio, the gate electrode and the wiring 2 and the common wiring 19 are alternately arranged, and the common wiring 19 is connected to the branch-shaped auxiliary capacitance electrode 4. ing. The auxiliary capacitance electrode 4 has two roles. One is to form an auxiliary capacitance in parallel with the pixel capacitance and to serve as an electrode for retaining the charge of the pixel. The second is near the source line due to poor alignment of the liquid crystal caused by the electric field from the source electrode. This is the role of preventing light leakage. The means for preventing light leakage using the auxiliary capacitance electrode 4 can use a photoengraving technique with remarkably high alignment accuracy as compared with the case of using a light-shielding film on the opposite substrate, and is effective for increasing the aperture ratio. Means. As another conventional method, as shown in FIG. 14A, an auxiliary capacitance on-gate method in which the common wiring 19 is also used by the adjacent gate electrode and wiring 2 is also used quite generally. In this case, the auxiliary capacitance electrode 4 is connected to the adjacent gate electrode and the wiring 2. This method is more advantageous in increasing the aperture ratio. FIGS. 13B and 14B are plan views of the TFT array substrate using the respective gate layer structures when the array process is completed.

[0003] A process for manufacturing a conventional TFT array substrate will be described below with reference to the drawings. FIG. 15 is a cross-sectional view showing a manufacturing process of the TFT array substrate adopting the common auxiliary capacitance method shown in FIG. First, a metal film such as a Cr film is formed as a single layer on a glass substrate 1 which is a transparent insulating substrate, resist patterning and etching of the metal film are performed, and the gate electrode and the wiring 2 and the common wiring 19 are formed. It is formed (FIG. 15A). Next, a gate insulating film 5, an amorphous silicon film 6, and an n + type amorphous silicon film 7 made of a silicon nitride film are continuously formed by a plasma CVD method or the like. Further, in order to form a channel portion of the transistor, the amorphous silicon film 6 and the n + type amorphous silicon film 7 are patterned into an island shape (FIG. 15).
(b)). Next, the pixel electrode 8 is formed from a transparent conductive film such as ITO (FIG. 15C), and the source electrode and the wiring 1 are formed.
1. A drain electrode 12 is formed (FIG. 15D). In this case, in order to improve the ohmic contact with the semiconductor layer, Cr or Ti is used as a lower layer as a barrier metal, and a lower resistance such as a pure Al film or a single layer film of an Al alloy is used as an upper layer to reduce the resistance. A two-layer film using a metal film is used. Further, in order to prevent the ITO film from being corroded by a developer during photolithography, tungsten or the like may be added as an Al alloy as an impurity. Finally, to protect the TFT,
It is covered with an insulating film 13 such as a silicon nitride film (FIG. 15E).
FIG. 15E corresponds to a cross section taken along a line AB in FIG. 13B.

[0004]

In the liquid crystal display device aiming at a high aperture ratio as described above, the signal wiring is proceeding in the direction of thinning. With the thinning of the wiring, the probability of occurrence of disconnection due to foreign matter generated in the process, poor etching due to reduced adhesion of the resist, and the like has increased.
FIG. 16 shows a disconnection 14 occurring in a normal gate layer. Further, for application to monitors, etc., the demand for larger and higher definition panels has been increasing year by year, and the length and number of signal wirings are increasing, and the panels can be mounted without generating disconnections 14. It is becoming difficult to form. Since the disconnection 14 in the gate layer is difficult to repair using the redundant wiring provided outside the image display portion, the display becomes a linear display defect and becomes a defective product. For this reason, reduction of the disconnection 14 of the gate wiring 2 has become one of the important issues for improving the manufacturing yield. In addition, as the gate wiring 2 becomes thinner and longer, the use of low-resistance materials such as Al, Al alloys, and Mo as wiring materials is increasing. Since many of these materials have weak chemical resistance, there is a problem that in addition to the disconnection due to the above-described foreign matter and a decrease in the adhesive strength of the resist, the disconnection due to corrosion occurs when the pixel electrode 8 and the source wiring 11 are formed. Was. Since the occurrence rate of these is much higher than that of the disconnection due to the above-described foreign matter and reduced adhesion, it has been difficult to manufacture them. For this reason, these low-resistance materials are not used alone, but are used with measures such as covering with an insulating film with few defects such as a metal film or an anodic oxide film to prevent film corrosion. I was

In recent years, a method as shown in FIG. 17A has been devised to solve such a problem of gate disconnection (reference: SSKim et al., SID 95 DIGEST, pp. 15).
-18). This method employs a ladder-like wiring structure in which a gate electrode and wiring 2 and a redundant wiring 3 are connected by an auxiliary capacitance electrode 4. FIG. 17B shows a plan view of the completed array process by this method. According to this method, as shown in FIG. 18, even if a disconnection 14 occurs in the gate electrode and the wiring 2, a signal flows through the auxiliary capacitance electrode 4 and the redundant wiring 3.
No linear display failure occurs. However, with this structure,
Although the disconnection 14 is effective, the probability that a short circuit occurs due to the pattern defect 15 shown in FIG. 18 increases because the gate electrode and the wiring 2 and the wiring of the redundant wiring 3 are close to each other in the entire wiring range. was there. This short-circuit is one of the important issues because it is difficult to find the short-circuited portion and it is difficult to repair it.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and prevents the occurrence of linear display defects caused by disconnection or short circuit of a TFT array substrate, thereby improving display quality with a high aperture ratio. An object of the present invention is to provide a method for manufacturing a TFT array substrate, which is capable of manufacturing the above-mentioned liquid crystal display device at a high yield, with the object of obtaining an excellent liquid crystal display device.

[0007]

SUMMARY OF THE INVENTION A TFT according to the present invention
The array substrate includes a plurality of gate wirings formed on a transparent insulating substrate, a plurality of source wirings intersecting the gate wirings, and a transparent wiring connected to a thin film transistor provided at each intersection of the gate wirings and the source wirings. A pixel electrode made of a conductive film, and an auxiliary capacitance electrode that is a branch-like electrode that extends vertically from the gate wiring for each pixel and that forms an auxiliary capacitance with an insulating film interposed between a part of the pixel electrode and A gate wiring and a source wiring, which are provided in the vicinity of an image display unit composed of a branch-like auxiliary capacitance electrode, a redundant wiring crossing inside from the tip thereof, and a pixel electrode in parallel and alternately with the gate wiring; And a connection terminal unit for inputting an external signal to the connection terminal. The tip of the branch-like auxiliary capacitance electrode is electrically separated from the redundant wiring. Further, the gate wiring, the auxiliary capacitance electrode, and the redundant wiring are each formed of the same material in the same layer.

Further, as materials of the gate wiring, Al, M
Any one of o, Cu, or an alloy containing these as a main component is used. Also, as a material for the gate wiring,
An Al-Nd alloy having an Nd composition of 0.1% or more and less than 5% is used. Furthermore, Cr, W, Ti, Ta, or the like is used as a material of a wiring for connecting a signal wiring such as a gate wiring and a source wiring to a connection terminal portion. The redundant wiring has a line width of 2 μm or more and 10 μm or less. Further, a liquid crystal display device according to the present invention is one in which liquid crystal is arranged between the TFT array substrate described in any of the above and a counter electrode substrate having a transparent electrode, a color filter and the like.

Further, in the method of manufacturing a TFT array substrate according to the present invention, in a step of forming a metal thin film on a transparent insulating substrate and forming a gate wiring, an auxiliary capacitance electrode and a redundant wiring by patterning, a resist material is used. It is manufactured using a positive resist, including a step of performing exposure with an exposure energy of 2 to 4 times the proper exposure amount. In the step of forming a metal thin film on a transparent insulating substrate and forming a gate wiring, an auxiliary capacitance electrode and a redundant wiring by patterning, a positive resist is used as a resist material, and a mask having a line width equal to the design pattern is used. After the exposure with the proper exposure amount, the area of the light-shielding portion is larger than that of the mask, that is, using a mask having a line width larger than the design pattern, and using an exposure energy of 2 to 10 times the appropriate exposure amount again. It is manufactured so as to include a step of performing exposure. Further, the manufacturing method includes a step of forming a metal thin film on a transparent insulating substrate and forming a gate wiring, an auxiliary capacitance electrode and a redundant wiring by patterning using a negative resist.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a manufacturing process of a TFT array substrate using a channel etching type amorphous silicon thin film transistor according to a first embodiment of the present invention, and FIG. 2 is a TF according to the present embodiment.
It is a top view in the gate layer of a T array substrate. In the figure, 1 is a glass substrate which is a transparent insulating substrate, 2 is a gate electrode and a wiring, 3 is a redundant wiring arranged in parallel and alternately with the gate electrode and the wiring 2, 4 is a vertical line from the gate wiring 2 for each pixel. A branch-like auxiliary capacitance electrode extending to
The redundant wiring 3 intersects with the auxiliary capacitance electrode 4 on the inner side than the tip thereof, and is electrically connected to the gate electrode and the wiring 2. Further, 5 is a gate insulating film, and 6 and 7 are T
An amorphous silicon film and an n + type amorphous silicon film constituting the FT; 8, a pixel electrode made of a transparent conductive film such as ITO; 9, a terminal electrode; 10, a contact hole; Reference numeral 12 denotes a drain electrode, and reference numeral 13 denotes an insulating film such as a silicon nitride film for protecting the TFT. The pixel electrode 8 is connected to a TFT provided at each intersection of a plurality of gate wirings 2 and source wirings 11. The auxiliary capacitance electrode 4 forms a gate insulating film 5 with a part of the pixel electrode 8. An auxiliary capacitance is formed by sandwiching it. The auxiliary capacitance electrode 4, the redundant wiring 3, the gate electrode, and the wiring 2 are formed of the same material in the same layer. Further, the gate wiring 2 and the source wiring 11 are provided around the image display unit constituted by the pixel electrodes 8.
Is provided with a terminal electrode 9 which is a connection terminal for inputting an external signal.

A manufacturing process of the TFT array substrate in the present embodiment will be described with reference to the drawings. First, a metal film such as Cr is formed on the surface of the glass substrate 1 by sputtering to a thickness of about 400 nm. Next, resist patterning is performed using a positive resist. At that time, after once exposing with an appropriate exposure amount using a mask having a line width equal to the design pattern, the area of the light-shielding portion is again larger than that of the mask, that is, a line width larger than the design pattern. In this case, using a thick mask of about 3 μm, the appropriate exposure amount is doubled.
Exposure is performed with about 10 times the exposure energy. Next, the chromium film is etched using an etching solution containing ceric ammonium nitrate and nitric acid as main components, and the gate electrode and the wiring 2 and the redundant wiring 3 as shown in FIGS.
And a branch-like auxiliary capacitance electrode 4 is formed. At this time, since the nitric acid is contained in the etching solution, the Cr film is processed into a tapered shape, and disconnection of the upper layer when the film thickness becomes 300 nm or more can be prevented. Next, a gate insulating film 5, an amorphous silicon film 6, and an n + type amorphous silicon film 7 made of a silicon nitride film are successively formed by PCVD, for example, at a thickness of about 500 nm, 200 nm, and 50 nm, respectively. Further, in order to form a channel portion of the transistor, the amorphous silicon film 6 and the n + amorphous silicon film 7 are patterned into an island shape (FIG. 1B).
). Next, an ITO film is formed to a thickness of, for example, about 100 nm by sputtering, and the pixel electrode 8 is formed by patterning.
Then, a terminal electrode 9 is formed, and further, a contact hole 10 in a terminal portion is formed (FIG. 1 (c)).

Next, the lowermost layer is made of, for example, Cr or Ti 100 nm.
%, The second layer is Al-0.2 at.
A metal film consisting of a three-layer film having a Cr thickness of about 50 nm is formed on the uppermost layer, and the source electrode, the wiring, and the drain electrode are patterned, and the three-layer film is etched. Thereafter, the n + amorphous silicon film 7 on the channel is removed by dry etching to form the source electrode, the wiring 11, and the drain electrode 12, and then the resist is removed (FIG. 1 (d)). Finally, in order to protect the TFT, the TFT is covered with an insulating film 13 such as a silicon nitride film, and the insulating film 13 on the pixel electrode 8 and the terminal electrode 9 is removed (FIG. 1 (e)). In the present embodiment, a three-layer film is used as the source and drain materials. However, if no particular problem occurs in the wiring resistance, the pixel electrode forming process, etc., a single-layer film of Mo, Cr, etc., the lower layer Cr, the upper layer It may be a two-layer film of an Al-based alloy or the like.

In this embodiment, as shown in FIG. 2, the line width of each wiring is 15 μm, the width of the gate wiring 2 being 15 μm.
The width of the redundant wiring 3 is 2 μm, and the width of the branch-like auxiliary capacitance electrode 4 is 6 μm.
m, and the center of the auxiliary capacitance electrode 4 is arranged so that the redundant wiring 3 intersects. When the gate line 2 is disconnected, the width of the redundant line 3 is a series of the resistance of the redundant line 3 and the resistance of the entire gate line 2, so that the line width may be about 1 to 2 μm. Further, since the redundant wiring 3 is a light-shielding portion, it is preferable that the redundant wiring be as thin as possible from the viewpoint of increasing the aperture ratio. However, considering the etching accuracy of about 1 to 2 μm,
The limit is about μm. Therefore, the width of the redundant wiring 3 is 2 μm.
When the thickness is 10 μm or less, it functions as the redundant wiring 3 and can increase the aperture ratio, thereby reducing display unevenness due to crosstalk and the like.

In the TFT array substrate manufactured as described above, defects such as a defect at the time of patterning and a peeling of the resist at the time of etching cause disconnection as shown in FIG.
Even when 4 occurs, the signal can be transmitted through the redundant wiring 3 because of the gate layer structure having the redundant wiring 3 and does not become a linear defect. Further, when the pattern defect 15 occurs, the auxiliary capacitance electrode 4
It does not cause a short circuit unless it occurs near the tip of the. As described above, according to the present embodiment, it is possible to reduce a failure caused by disconnection and short circuit in the gate layer, which has frequently occurred in the related art.

The size of a pattern defect generated when foreign matter enters during photolithography is many times larger than the actual size of foreign matter. Fig. 4
This will be described with reference to FIG. In general, when the resist 17 is applied on the glass substrate 1 on which the metal thin film 22 is formed in a state where the foreign matter 16 is adhered, the thickness of the resist 17 is set around the foreign matter 16 as shown in FIG. Thicker than film thickness. Here, when exposure is performed under the exposure conditions of the resist 17 having a normal thickness using the mask 18, insufficient exposure occurs near the foreign matter 16 (FIG. 4B), and the resist 17 remains (FIG. 4C).
). In the figure, hatched portions indicate the exposed resist 17a. As a result, after the etching, the pattern defect 15 having a size many times that of the foreign material 16 as shown in FIG.
Becomes When such a huge pattern defect 15 occurs, the probability of short-circuiting near the tip of the branch-like auxiliary capacitance electrode 4 increases. Therefore, the size of the pattern defect 15 can be limited to the size of the foreign substance 16 itself by performing the exposure with the exposure energy of 2 to 4 times the appropriate exposure amount.

FIG. 5 is a diagram showing the pattern defect size with respect to the additional exposure energy. By performing the additional exposure about twice, the size of the pattern defect 15 becomes substantially the same as the size of the foreign matter 16 itself. FIG. 6 is a diagram for explaining the effect of reducing the pattern defect size by the additional exposure. As shown in the drawing, by performing sufficient additional exposure, the thick resist 17 around the foreign matter 16 is completely exposed, so that the size of the pattern defect 15 is reduced, and a short circuit between wirings made of the metal thin film 22 occurs. Probability can be reduced. FIG. 7 is a diagram showing the relationship between exposure energy and pattern thinning. In the figure, A shows the relationship between irradiation energy and pattern thinning when additional exposure is performed using a mask pattern that is 3 μm thicker than the designed resist pattern, and A indicates the case where additional exposure is performed using a normal mask pattern. By performing additional exposure using a mask pattern that is about 3 μm thicker than the designed resist pattern, pattern thinning can be suppressed to 0.5 μm or less. Further, from the viewpoint of the throughput of the exposing machine, the same effect can be obtained by performing a single exposure with an exposure amount three times as large as a pattern design of about 2 μm thicker in advance in consideration of thinning of the resist.

Embodiment 2 FIG. FIG. 8 is a cross-sectional view showing a manufacturing process of a TFT array substrate using a channel etching type amorphous silicon thin film transistor according to the second embodiment of the present invention. In the drawings, the same or corresponding portions are denoted by the same reference characters and description thereof will be omitted. TF in the present embodiment
The manufacturing process of the T array substrate will be described with reference to the drawings. First,
On the surface of the glass substrate 1, a metal film such as Mo is formed to a thickness of about 400 nm by sputtering. Next, resist patterning is performed using a positive resist. At that time, after once exposing with a proper exposure amount using a mask pattern serving as a design resist pattern, using a mask pattern about 3 μm thicker than the design resist pattern again, and exposing with energy about 2 to 10 times the proper exposure amount. I do. next,
The etching of the Mo film was performed using an etching solution containing phosphoric acid, acetic acid and nitric acid as main components, and FIG.
The gate electrode and wiring 2, the redundant wiring 3 and the branch-like auxiliary capacitance electrode 4 are formed as shown in FIG. At this time, since the nitric acid is contained in the etching solution, the Mo film is processed into a tapered shape, and disconnection of the upper layer when the film thickness becomes 300 nm or more can be prevented. Further, since it is difficult to form a redundant wiring structure for the wiring connecting the signal wiring such as the gate wiring 2 to the connection terminal portion outside the pixel, a metal film such as Ti or the like is used. For example, the occurrence probability of disconnection can be reduced.

Next, a gate insulating film 5 made of a silicon nitride film, an amorphous silicon film 6, n
The + type amorphous silicon film 7 is, for example, 500
Films are continuously formed on the order of nm, 200 nm and 50 nm. Further, in order to form a channel portion of the transistor, the amorphous silicon film 6 and the n + amorphous silicon film 7 are patterned into an island shape (FIG. 8B). Next, Cr400
A metal film of about nm is formed, a source electrode, a wiring, and a drain electrode are patterned, and the metal film is etched. Thereafter, the n + amorphous silicon film 7 on the channel is removed by dry etching, so that the source electrode and wiring 11 and the drain electrode 12 are removed.
After the formation of the resist, the resist is removed (FIG. 8C). Finally, in order to protect the TFT, the TFT is covered with an insulating film 13 such as a silicon nitride film, and the insulating film 13 on the drain electrode 12 and the terminal portion is removed (FIG. 8D). Next, an ITO film is formed to a thickness of, for example, about 100 nm by sputtering, and the pixel electrode 8 and the terminal electrode 9 are formed by patterning (FIG. 8E).

According to the present embodiment, the first embodiment is described.
2 has a gate layer structure as shown in FIG. 2, so that the same effect as in the first embodiment can be obtained with respect to the disconnection 14 and the pattern defect 15 as shown in FIG. Also,
When a low-resistance material Mo is used for the gate layer, when the Cr film for forming the source electrode and the wiring 11 and the drain electrode 12 is etched, the ITO of the pixel electrode is further removed.
During etching, a common etching solution containing hydrochloric acid or nitric acid as a main component causes corrosion at a defective portion of the silicon nitride film to easily cause a disconnection 14, but in the structure of the present embodiment, a linear defect due to the disconnection 14 occurs. Since it is difficult, the effect of reducing the probability of occurrence of linear defects is further enhanced. Also in the present embodiment, when the additional exposure is performed, the first embodiment
Similarly, the probability of occurrence of a short circuit between wirings can be further reduced. When the width of the redundant wiring 3 is set to about 2 μm in the finished dimension, the aperture ratio can be increased as in the first embodiment. In this embodiment, Mo is used as the material of the gate electrode and the wiring 2. However, an Al, Mo, Cu film, an alloy containing these as a main component, or the like may be used. Further, Ti is used as a material of the wiring for connecting the signal wiring such as the gate wiring 2 and the source wiring 11 to the connection terminal portion.
r, W, Ti, Ta or the like may be used.

Embodiment 3 FIG. 9 is a cross-sectional view showing a manufacturing process of a TFT array substrate using a channel etching type amorphous silicon thin film transistor according to the third embodiment of the present invention. In the drawings, the same or corresponding portions are denoted by the same reference characters and description thereof will be omitted. TF in the present embodiment
The manufacturing process of the T array substrate will be described with reference to the drawings. First,
On the surface of the glass substrate 1, an Al—Nd composition of 0.5 at.
An Nd-based alloy film is formed to a thickness of about 200 nm by sputtering. Next, resist patterning is performed using a positive resist. At that time, after once exposing with a proper exposure amount using a mask pattern serving as a design resist pattern, using a mask pattern about 3 μm thicker than the design resist pattern again, and exposing with energy about 2 to 10 times the proper exposure amount. I do. Next, the Al-based alloy film is etched using an etching solution containing phosphoric acid, acetic acid, and nitric acid as main components, and the gate electrode and the wiring 2, the redundant wiring 3, and the like as shown in FIG. The branch-like auxiliary capacitance electrode 4 is formed. At this time, by appropriately adjusting the concentration of nitric acid in the etching solution, the Al alloy film is processed into a tapered shape, and disconnection of the upper layer when the film thickness becomes 300 nm or more can be prevented. In this embodiment, since the film thickness is 200 nm, straight etching may be used. Also,
Since it is difficult to form a redundant wiring structure for the wiring portion that leads the signal wiring to the connection terminal portion outside the pixel, use Cr or the like or cover the Al-based alloy surface layer with Cr or the like to further disconnect. The probability of occurrence can be reduced.

Next, a gate insulating film 5 made of a silicon nitride film, an amorphous silicon film 6, n
The + type amorphous silicon film 7 is, for example, 500
Films are continuously formed on the order of nm, 200 nm and 50 nm. Further, in order to form a channel portion of the transistor, the amorphous silicon film 6 and the n + amorphous silicon film 7 are patterned into an island shape (FIG. 9B). Next, an ITO film is formed to a thickness of, for example, about 100 nm by sputtering, a pixel electrode 8 and a terminal electrode 9 are formed by patterning, and a contact hole 10 in a terminal portion is formed (FIG. 9C). Next, the lowermost layer is made of, for example, Cr or Ti10.
A metal film consisting of a three-layer film having a thickness of about 0 nm, a second layer of Al-0.2 at.% Cu of about 300 nm, and an uppermost layer of about 50 nm of Cr is formed, and a source electrode, a wiring, and a drain electrode are patterned. Etch. Thereafter, the n + amorphous silicon film 7 on the channel is removed by dry etching to form the source electrode, the wiring 11, and the drain electrode 12, and then the resist is removed (FIG. 9D). Finally, in order to protect the TFT, the pixel electrode 8 is covered with an insulating film 13 such as a silicon nitride film.
And the insulating film 13 on the terminal electrode 9 is removed (FIG. 9E).
). In this embodiment, a three-layer film is used as the source and drain materials. However, if no particular problem occurs in the wiring resistance, the pixel electrode forming process, and the like, a single-layer film of Mo, Cr, or the like, the lower layer Cr, the upper layer It may be a two-layer film of an Al-based alloy or the like. Further, as a material of the gate wiring 2, an Nd composition of 0.5a is used.
% Al-Nd alloy film was used, but the Nd composition was 0.1%.
What is necessary is just 1% or more and less than 5%.

According to the present embodiment, the first embodiment is described.
Similarly to FIGS. 2 and 3, since the structure of the gate layer is used as shown in FIG.
The same effects as those of the first and second embodiments can be obtained with respect to the pattern defect 15, and it is possible to reduce a defect caused by disconnection and a short circuit in the gate layer, which has frequently occurred in the related art. Further, in the present embodiment, an Al-based alloy of a low resistance material is used as the gate layer. However, conventionally, when etching the ITO for forming the pixel electrode 8, a general hydrochloric acid or nitric acid is used as a main component. Corrosion occurs in the etching solution at the deficient portion of the silicon nitride film, and disconnection is likely to occur. Therefore, in order to prevent this, contact-type cleaning such as a brush is not performed before patterning. For this reason, pattern defects 15 are likely to occur, which is an obstacle to using an Al-based alloy film. In the present embodiment, the probability of occurrence of a linear defect due to the disconnection 14 can be further reduced, and the pattern defect 15
The probability of short circuit between wires due to
It has become possible to use an l-based alloy in a single layer.

When a general Al-based alloy such as Al-Cu or Al-Si is used, hillocks are generated on the surface of the Al-based alloy after a heat history such as a subsequent film formation. When this hillock occurs, the hillock cannot be covered with the silicon nitride film, and corrosion disconnection occurs throughout the wiring at the time of ITO etching. In such a case, even if the redundant wiring 3 as in the present invention is provided, the disconnection 14 occurs in both the gate wiring 2 and the redundant wiring 3, and the effect of the present invention is reduced. In order to prevent such disconnection 14, in the present embodiment,
Al-Nd 0.5 at.% Is used as the Al-based alloy, and no hillocks are generated on the surface. For this reason, the structure of the present invention is effective also in the case of a low-resistance Al-based alloy.
Also in this embodiment, when additional exposure is performed, the probability of occurrence of a short circuit between wirings can be further reduced as in the first and second embodiments. Further, by setting the width of the redundant wiring 3 to a finished dimension of about 2 μm, the aperture ratio can be increased as in the first and second embodiments.

Embodiment 4 Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 10 is a plan view of a gate layer of a TFT array substrate using a channel etching type amorphous silicon thin film transistor according to a fourth embodiment of the present invention, and FIG. 11 is a cross-sectional view taken along a line AB in FIG. In the drawings, the same or corresponding parts have the same reference characters allotted, and description thereof will not be repeated. In the TFT array substrate according to the present embodiment, the tip of the branch-like auxiliary capacitance electrode 4 is connected to the redundant wiring 3.
And is electrically separated from the above.

The manufacturing process of the TFT array substrate according to the present embodiment will be described. First, a metal film such as Cr is formed on the surface of the glass substrate 1 by sputtering to a thickness of about 400 nm. Next, resist patterning is performed using a positive resist. Next, the chromium film is etched using an etching solution containing ceric ammonium nitrate and nitric acid as main components, and as shown in FIGS. 10 and 11, the gate electrode and the wiring 2, the redundant wiring 3, and the branch-like auxiliary Capacitive electrode 4
To form In the present embodiment, the branch-like auxiliary capacitance electrode 4
3 μm so that the tip of
The structure is such that a gap of about m is provided. At the time of etching, since nitric acid is contained in the etching solution, the Cr film is processed into a tapered shape, and disconnection of the upper layer when the film thickness becomes 300 nm or more can be prevented. Although a Cr film is used as a gate material in this embodiment, similar effects can be obtained by using a low-resistance material such as Mo or an Al-based alloy as in the second and third embodiments. Next, a gate insulating film 5, an amorphous silicon film 6, and an n + type amorphous silicon film 7 made of a silicon nitride film by PCVD.
Are continuously formed, and the subsequent steps are the same as in the first embodiment.

According to the present embodiment, when the disconnection 14 as shown in FIG. 12 occurs, a signal can be transmitted through the redundant wiring 3 because the gate layer structure having the redundant wiring 3 is employed. It does not result in a shape defect. Further, a pattern defect 15 is generated at the tip of the auxiliary capacitance electrode 4 in a branch shape, and the tip of the auxiliary capacitance electrode 4 is connected to the gate electrode and the wiring 2.
Is electrically isolated from the redundant wiring 3 even if the short circuit is electrically short-circuited, it does not become a linear display defect. As described above, according to the present embodiment, it is possible to reduce failures due to disconnection and short circuit in the gate layer, which frequently occur in the related art.

In the first to fourth embodiments, the TFT
Although a positive resist, which is often used in the manufacture of an array substrate, is used, the use of a negative resist only in the gate step hardly causes a resist residue. In the case of a negative resist, a short circuit occurs only when the foreign matter 16 itself acts as a mask and etching residue occurs. Also in this case, since the size of the pattern defect 15 is small, the probability of occurrence of a short circuit between wirings can be reduced. In the first to fourth embodiments, the TFT array substrate using the channel etching type amorphous silicon thin film transistor has been described. However, the same effect can be obtained when the channel protection film type amorphous silicon thin film transistor is used. it can. Further, by arranging liquid crystal between the TFT array substrate according to Embodiments 1 to 4 and a counter electrode substrate having a transparent electrode and a color filter, a liquid crystal display device having a high aperture ratio and excellent display quality is provided. It can be manufactured with a high yield.

[0028]

As described above, according to the present invention, a branch-like auxiliary capacitance electrode extending vertically from a gate line for each pixel and a branch-like auxiliary capacitance arranged in parallel and alternately with the gate line are provided. The redundant wiring that intersects the electrode and the inside of the tip is provided, so even if the gate wiring is disconnected due to a defect at the time of patterning or peeling of the resist at the time of etching, the signal will be redundant wiring. In addition, even if a pattern defect occurs in the gate wiring, a short circuit does not occur unless it occurs near the tip of the auxiliary capacitance electrode on the branch. A linear display defect can be prevented, and a liquid crystal display device having a high aperture ratio and excellent display quality can be obtained.

According to the method of manufacturing a TFT array substrate according to the present invention, after exposing with a proper exposure amount using a mask having a line width equal to the design pattern, the area of the light shielding portion is larger than that of the mask. Using a mask with a line width wider than the design pattern, and performing exposure again with an exposure energy of 2 to 10 times the appropriate exposure amount,
Since the size of the pattern defect can be suppressed to the size of the foreign substance itself without causing insufficient exposure of the resist around the foreign substance adhering to the substrate which is mixed in the manufacturing process, the probability of occurrence of a short circuit between wirings is further increased. It can be reduced, and the production yield is improved.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a TFT array substrate according to a first embodiment of the present invention.

FIG. 2 is a plan view showing a gate layer of the TFT array substrate according to the first embodiment of the present invention.

FIG. 3 is a plan view illustrating an operation of the TFT array substrate according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating a pattern defect generation mechanism in a TFT array substrate.

FIG. 5 is a diagram showing a pattern defect size with respect to additional exposure energy.

FIG. 6 is a diagram illustrating the effect of reducing the size of a pattern defect by additional exposure.

FIG. 7 is a diagram showing a relationship between exposure energy and pattern thinning.

FIG. 8 is a cross-sectional view illustrating a method for manufacturing the TFT array substrate according to the second embodiment of the present invention.

FIG. 9 is a cross-sectional view illustrating a method for manufacturing a TFT array substrate according to Embodiment 3 of the present invention.

FIG. 10 is a plan view of a gate layer of a TFT array substrate according to a fourth embodiment of the present invention.

FIG. 11 is a sectional view taken along the line AB in the gate layer of the TFT array substrate according to the fourth embodiment of the present invention.

FIG. 12 is a plan view illustrating an operation of the TFT array substrate according to the fourth embodiment of the present invention.

13A is a plan view of a gate layer of a conventional TFT array substrate of a common storage capacitor type, and FIG. 13B is a plan view of a completed array process.

FIG. 14A shows a conventional storage capacitor on-gate T
FIG. 3B is a plan view of the gate layer of the FT array substrate, and FIG.

FIG. 15 is a cross-sectional view illustrating a conventional method of manufacturing a TFT array substrate of a common auxiliary capacitance type.

FIG. 16 is a diagram illustrating a problem of a conventional TFT array substrate.

17A is a plan view of a gate layer of a TFT array substrate using a conventional redundant wiring, and FIG. 17B is a plan view of a completed TFT array process.

FIG. 18 is a diagram illustrating the operation and problems of a conventional TFT array substrate using redundant wiring.

[Explanation of symbols]

Reference Signs List 1 glass substrate, 2 gate electrode and wiring, 3 redundant wiring, 4 auxiliary capacitance electrode, 5 gate insulating film, 6 amorphous silicon film, 7 n + type amorphous silicon film, 8 pixel electrode, 9 terminal electrode, 10 contact hole, 11 source Electrode and wiring, 12 drain electrode, 13 insulating film, 14 disconnection, 15 pattern defect,
16 foreign matter, 17 resist, 17a exposed resist, 18 mask, 19 common wiring, 22 metal thin film.

Claims (11)

[Claims] A plurality of gate wirings formed on a transparent insulating substrate, a plurality of source wirings intersecting the gate wirings, and thin film transistors provided at respective intersections of the gate wirings and the source wirings. A pixel electrode made of a transparent conductive film, a branch electrode vertically extending from the gate wiring for each pixel, and an auxiliary capacitance forming an auxiliary capacitance with an insulating film interposed between the pixel electrode and a part of the pixel electrode An electrode, a redundant wiring that is arranged in parallel and alternately with the gate wiring, intersects the branch-shaped auxiliary capacitance electrode inside the tip of the auxiliary storage capacitance electrode, and is provided around an image display unit including the pixel electrode; A TFT array substrate comprising a connection terminal portion for inputting an external signal to a wiring and a source wiring. 2. The device according to claim 1, wherein the tip of the branch-like auxiliary capacitance electrode is electrically separated from the redundant wiring.
The TFT array substrate as described in the above. 3. The TFT array substrate according to claim 1, wherein the gate wiring, the auxiliary capacitance electrode, and the redundant wiring are formed of the same material in the same layer. 4. A gate wiring material comprising Al, Mo,
4. The TFT array substrate according to claim 1, wherein one of Cu and an alloy containing these as a main component is used. 5. 5. An Nd composition having a Nd composition of 0.5 as a material of a gate wiring.
5. The TFT array substrate according to claim 4, wherein 1% or more and less than 5% of an Al-Nd alloy is used. 6. A material for connecting a signal wiring such as a gate wiring and a source wiring to a connection terminal portion, the material being Cr,
6. The TFT array substrate according to claim 4, wherein W, Ti, Ta, or the like is used. 7. The TFT array substrate according to claim 1, wherein the redundant wiring has a line width of 2 μm or more and 10 μm or less. 8. A liquid crystal is disposed between the TFT array substrate according to claim 1 and a counter electrode substrate having a transparent electrode, a color filter, and the like. Liquid crystal display device. 9. A metal thin film is formed on a transparent insulating substrate,
The step of forming a gate wiring, an auxiliary capacitance electrode, and a redundant wiring by patterning includes a step of using a positive resist as a resist material and performing exposure with an exposure energy of 2 to 4 times an appropriate exposure amount. A method for manufacturing a TFT array substrate. 10. In a step of forming a metal thin film on a transparent insulating substrate and forming a gate wiring, an auxiliary capacitance electrode and a redundant wiring by patterning, a positive resist is used as a resist material and a line width equal to the design pattern is obtained. After exposing at an appropriate exposure dose using a mask, the area of the light-shielding portion is larger than that of the mask, that is, using a mask having a line width larger than the design pattern, and at least twice the appropriate exposure dose.
A method for manufacturing a TFT array substrate, comprising a step of performing exposure again with exposure energy of 0 times or less. 11. A method of manufacturing a TFT array substrate, comprising: forming a metal thin film on a transparent insulating substrate, and forming a gate wiring, an auxiliary capacitance electrode, and a redundant wiring by patterning using a negative resist. Method.