JPH11122097A - Clock frequency dividing circuit and logic circuit device - Google Patents

Abstract

(57) [Problem] To provide a clock frequency dividing circuit capable of completely synchronizing clock edges between clock waveforms having different frequencies. SOLUTION: A count value holding unit is constituted by n (positive integer) sequential circuits each latching data at an edge of a common input clock, and the count value holding unit is set to 0 according to the input clock.
And a counter circuit having an n-bit width for counting a binary number between 2 ⁿ -1 and 2 ⁿ -1.
From the count value holding unit, １ ／ of the input clock
In a clock divider circuit for outputting a clock waveform having a frequency of (0 ≦ m <n), the count value holding unit latches data at both rising and falling edges of the input clock. It consisted of.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock frequency dividing circuit for generating a plurality of clock frequencies from an input clock, and to a logic circuit device operating synchronously at a plurality of clock frequencies.

[0002]

2. Description of the Related Art In sequential logic circuits including clock driving circuits such as latches and flip-flops (hereinafter simply referred to as FFs) driven by clock signals, edges of clock signals supplied to each clock driving circuit are strictly synchronized. Is required.

Here, as shown in FIG. 7A, two FFs respectively driven by clock signals CKi and CKj are used.
A case where a combinational circuit 103 is connected between 101 and 102 will be described as an example.

As a phase relationship between two clock signals CKi and CKj, FIG. 1B shows a clock waveform when the clock signal CKj is ahead of the clock signal CKi (positive skew), and FIG. Is the clock signal CKj
The clock waveform when the clock signal CKi is further advanced (negative skew) is shown.

If the delay from the clock supply source to CKi, CKj is TCi, TCj, the skew Tskewi, j between both clocks can be expressed by the following equation.

Tskewi, j = TCi−TCj (1) Clock waveforms in the cases of Tskewi, j> 0 and Tskewi, j <0 are shown in FIGS. 7B and 7C. FF10
Assuming that the bus delay between the blocks 1 and 102 is TPD, the constraint required for clock skew is:

(Equation 1) Becomes Here, fmax is the maximum frequency of the clock for driving the FFs 101 and 102.

As is apparent from this equation, there is an allowable range of skew in both positive and negative directions. Positive skew is
Since it has the effect of lowering the maximum operating frequency of the circuit, in order to guarantee the operating frequency of the circuit when the skew increases, the delay of the combinational logic circuit connected between the sequential circuits, the delay of the sequential circuit, and the order The circuit setup time had to be reduced. Positive skew increases the proportion of the clock cycle time when the operating frequency increases, so that the effect of deteriorating the maximum operating frequency becomes more significant.

On the other hand, the negative skew means that the data output from the preceding-stage sequential circuit should be latched by the next-stage sequential circuit one clock cycle later, but is latched one clock cycle earlier and the immediately preceding data , Causing a so-called "data slip-through" phenomenon.

This becomes more serious when the bus delay TPD between the sequential circuits is small, as shown in equation (2). In addition, in the case of positive skew, the logic malfunction of the circuit can be avoided by lowering the operating frequency of the circuit, whereas the logic malfunction in the case of "data skipping" due to negative skew lowers the operating frequency of the circuit. It has the characteristic that it does not disappear even if it is.

Further, in recent years, the scale of LSI has been increased, and integrated circuits in which circuits operating at different frequencies coexist on the same chip have appeared. As described above, even in a circuit using a plurality of clock frequencies as operating frequencies, if a skew occurs at a clock edge to be synchronized between clocks, the above-described skew problem occurs exactly in the same manner. It is very important to keep the skew small.

Conventionally, PLL (Phase Locked)
When a clock signal is supplied to a logic circuit that uses a clock from a clock supply source such as Loop (Loop) and a clock obtained by ^dividing the clock by 2 ⁿ (n = 1, 2, 3,...) Single edge trigger that latches data only at one of the rising and falling edges of the waveform
triggered FF (hereinafter, referred to as Sgl-FF)
Was used to constitute a frequency divider.

FIG. 8 shows a circuit example of an Sgl-FF that latches data at the rising edge of a clock. This S
In the gl-FF 201, two level-sensitive latches 301 and 302 of a master / slave are connected in series.

FIG. 9A shows a clock frequency dividing circuit composed of n Sgl-FFs (first conventional example). This clock divider circuit is composed of n Sgl-FF2s.
, 201-n are serially connected in series, and the input clock CLK (frequency f) supplied from the PLL is 2 ⁿ as shown in the timing diagram of FIG. It can be divided.

However, as shown in FIG. 1B, a difference in clock edge occurs even if any two clock signals are compared. That is, in this circuit, Sgl
Since the data output of -FF becomes the clock input of the next stage Sgl-FF and the trigger to the next stage FF sequentially propagates, the clock waveform having a larger frequency division ratio (lower frequency) changes later.

The clock frequency dividing circuit shown in FIG. 10A (second conventional example) has n Sgl-FFs 201-1 and 201-2.
, 201-n. In this clock frequency dividing circuit, each S
As the driving clocks of the gl-FFs 201-1 to 201-n, the input clock CLK supplied from the PLL is supplied in common, and the outputs of the respective Sgl-FFs are simultaneously triggered. Does not occur.

However, when it is desired to use the input clock itself (frequency f) input to the frequency dividing circuit as a clock signal to the sequential circuit section, the clock after frequency division is Sgl.
Since there is a delay of one stage of the FF (from the clock edge to the output change), as shown in the timing chart of FIG. 10B, a skew of this delay time occurs between the input clock / divided clock. Will happen.

The clock divider circuit (third conventional example) shown in FIG. 11A has (n + 1) Sgl-FFs 201-.
It comprises a (n + 1) -bit subtraction counter using 0 to 201-n. The structure and operation of this circuit are exactly the same as those of the second conventional example, except that the bit width is increased by one and the frequency of the input clock CLK to the frequency divider is doubled ( f × 2). With such a configuration, a clock signal having a frequency f can be extracted as an output of the first stage of the counter.
/ 2,..., F / ²ⁿ , a plurality of clocks having clock edges completely synchronized can be obtained.

[0018]

However, the conventional clock frequency dividing circuit has the following problems. In the first and second conventional examples, a positive or negative skew occurs between edges of clock waveforms having different frequencies, causing a decrease in the maximum operating frequency and a phenomenon of data skipping.

In the third conventional example, the frequency of the input clock CLK supplied to the frequency dividing circuit is set to twice the frequency actually required by the circuit. There is a problem that power consumption in the clock wiring and the buffering element for transmission increases.
Further, as the circuit speed has increased, the clock frequency has been increased to GHz.
In the case of the order, the inductance component (increased in proportion to the frequency) parasitic on the clock wiring cannot be ignored, and there is a problem that not only the power consumption is increased but also the design of the clock tree becomes complicated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a clock frequency dividing circuit capable of completely synchronizing clock edges between clock waveforms having different frequencies. The purpose is to provide. Another object of the present invention is to provide a clock frequency dividing circuit capable of reducing power consumed in a clock tree unit. Further, it is an object of the present invention to provide a logic circuit device capable of avoiding a decrease in operating frequency and a phenomenon of data skipping and capable of suppressing power consumption.

[0021]

In order to achieve the above object, a clock divider circuit according to the first invention is characterized in that the clock divider circuit latches data at edges of a common input clock.
A count value holding unit is constituted by (positive integer) number of sequential circuits, and comprises an n-bit width counter circuit for counting a binary number between 0 and 2 ⁿ -1 according to the input clock. A clock divider circuit that outputs a clock waveform having a frequency of の of the input clock (an integer satisfying 0 ≦ m <n) from the count value holding unit, wherein the count value holding unit includes: It is constituted by a sequential circuit that latches data at both rising and falling edges.

According to the first aspect, the sequential circuit forming the count value holding unit is configured so that the count value of the input clock rises / decreases.
Data is latched at both falling edges and the count value is held. The clock waveforms output from the count value holding unit are exactly the same output from the sequential circuits. Since these sequential circuits are driven by a common input clock, clock edges between clock waveforms of different frequencies are completely completed. Can be synchronized. Furthermore, PLL
The frequency of the input clock supplied from the clock supply source to the frequency dividing circuit can be １ ／ of that of the conventional example.

According to a second aspect of the present invention, in the clock frequency dividing circuit according to the first aspect, the counter circuit includes a down counter.

According to the second aspect, the circuit of the first aspect operates simply and accurately.

The features of the logic circuit device according to the third invention are as follows.
2. A clock divider according to claim 1, a clock supply source for supplying an input clock to said clock divider, and a plurality of orders driven by a plurality of clock signals of different frequencies generated by said clock divider. And transferring data between the sequential circuits.

According to the third aspect, the skew is eliminated between clock waveforms having different frequencies, so that a decrease in operating frequency and data skipping can be avoided. Further, a clock signal having the same frequency as the input clock and having no skew with the divided clock can be output, so that power consumption between the clock supply source and the clock dividing circuit is suppressed.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a clock frequency dividing circuit according to an embodiment of the present invention. FIG. 2 and FIG.
FIG. 3 is a circuit diagram showing an example of an FF used in the clock frequency dividing circuit of FIG.

F used in the clock frequency dividing circuit of the present invention
F is capable of latching data at both rising and falling edges of the drive clock, so-called double edge triggered.
(registered) FF (hereinafter referred to as Dbl-FF)
It consists of. As one example, the FF shown in FIG. 2 has a structure in which the conventional master / slave level-sensitive latches shown in FIG. 8 are connected in parallel, and the output is connected by a 2-1 multiplexer constituted by a transfer gate. .

More specifically, a circuit provided with an output transfer gate that opens and closes in a clock phase opposite to that of the input transfer gate is connected in parallel to the output stage of the level-sensitive latch that becomes the master / slave of the clock. I have. Here, reference numeral 21 denotes a transfer gate for input on the master side, and reference numeral 22 denotes a data holding circuit 23 on the master side.
Is an output transfer gate on the master side. 3
1 is an input transfer gate on the slave side, 32 is a data holding circuit 32 on the slave side, and 33 is an output transfer gate on the slave side. CKB is an inverted signal of the clock CK. In the circuit having this configuration, the input data D is latched at both rising and falling edges of the clock CK, and the data Q is output from the inverter 41.

In the FF shown in FIG. 3, the transfer gates 21, 23, 31, 33 used in FIG. 2 are all clocked inverters 21a, 23a,
Although the structure replaced with 31a and 33a is shown, the function is completely equivalent to the FF shown in FIG.

In both cases, a master / slave pair of level-sensitive latches connected in series in the conventional example of FIG. 8 are connected in parallel, and a transfer gate or a clocked inverter is used to prevent the output logic value from colliding. 2-1 multi-plexer is provided on the output side.

The clock frequency dividing circuit according to the present embodiment has (n +
1) Dbl-FF shown in FIG. 2 or FIG. 3 is used as a component of the bit subtraction counter. That is, using the Dbl-FF that can latch data at both the rising and falling edges of the driving clock (n
A +1) -bit subtraction counter circuit is configured.

As shown in FIG. 1, the clock frequency dividing circuit according to the present embodiment is composed of the Sgl− of the count value holding unit in the conventional (n + 1) -bit subtraction counter shown in FIG.
The structure is such that FF is replaced with Dbl-FF.

Specifically, as shown in FIG. 1, n + 1 Dbl-FFs 10-0, 10-1,..., 10-n are arranged, and a clock supply line 11 is connected to a clock terminal CK. I have. Furthermore, each Dbl-FF 10-0 to 1
ExclusiveNOR of 2 inputs corresponding to 0-n
(Exclusive NOR, hereinafter referred to as ExNOR) 12-
, 12-n, and their outputs are supplied to the data D terminals of the Dbl-FFs 10-0 to 10-n, respectively.

The output data from the output terminal Q of the Dbl-FF 10-0 to 10-n is supplied to the inverters 13-0 and 13-n.
ExNOR 12-0 to 12- through 1, ..., 13-n
n is one of the inputs. A fixed potential is applied to the other input of the first stage ExNOR 12-0, and the second stage ExNOR1-0
The other input of 2-1 receives the output from the first-stage inverter 13-0.

The inverters 14, 15 and the two-input N
The circuit composed of the OR gate 16 is a second stage ExN
The two inputs of the ExNOR of the preceding stage are provided between the inverters 14 and 15, respectively, and the inverted signals are input to the two-input NOR gate 16. The output of the NOR gate 16 is the ExNOR 12-2,.
2-n is the other input.

As described above, by configuring the count value holding unit in the (n + 1) -bit subtraction counter by Dbl-FF, the clock edge at which the operation of the counter is triggered becomes both rising and falling, and at the same time, the PLL is activated. The frequency of the input clock CLK from the
Of the third conventional example, the clock frequency of each stage of the counter output becomes equal to that of the counter circuit of FIG. Moreover, in this case, similar to the circuit of FIG.
Since the clock signal of the counter output is an output signal from the same FF, no skew occurs between the clock edges (see the timing chart of FIG. 4).

As described above, since the Dbl-FF can latch the value at both the rising and falling edges of the driving clock, the output of each stage of the counter using the FF is as shown in FIG. The conventional Sgl-F shown in FIG.
The clock waveform has a frequency half that of the output clock signal of the corresponding stage of the counter composed of F. Paying particular attention to the output of the first stage of the counter, a clock waveform having the same frequency as the input clock frequency f of the frequency dividing circuit is obtained.
, F / ²ⁿ , the same clock frequency output as that of the conventional example, and a clock waveform completely synchronized between edges can be obtained.

Next, advantages of the present embodiment will be described in comparison with the above-mentioned three conventional examples. When the frequency divider circuits shown in the first and second conventional examples are used, positive or negative skew occurs at edges between clock waveforms having different frequencies. Therefore, as described in the problem of the related art, a reduction in the maximum operating frequency and a phenomenon of data skipping have occurred. On the other hand, in the clock frequency dividing circuit of the present embodiment, all the clock signal outputs are the same Dbl.
Since these Dbl-FFs are driven by a common clock signal, it is possible to completely synchronize clock edges between waveforms of different frequencies. Can be prevented from occurring.

When compared with the frequency dividing circuit shown in the third conventional example, in all the circuits, the clock edges are completely synchronized between clock signals of different frequencies, but the PLL is the same. Since the frequency of the input clock supplied from the clock supply source to the frequency divider circuit to the frequency divider circuit of the present embodiment can be halved in the frequency divider circuit of the present embodiment as compared with the conventional example, it is consumed by the clock tree unit up to the frequency divider circuit. There is a difference in the power to do.

Here, if the capacitance load from the clock supply source to the frequency dividing circuit (not including the transistor gate capacitance of the frequency dividing circuit itself) is set to CL, the power consumption becomes

P = f · CL · VDD ² (3) where P: power consumption of the clock tree section f: clock frequency VDD: power supply voltage, so that the clock frequency f becomes １ ／ Can reduce power consumption to half.

Further, as described in the third conventional example, when the clock frequency is on the order of GHz,
The effect of the inductance component of the wiring for transmitting the clock cannot be neglected, causing problems such as the power consumption due to the inductance and the complexity of the clock tree design.
From this, it can be said that the frequency dividing circuit of the present embodiment, which does not need to increase the input clock frequency supplied to the frequency dividing circuit, is more advantageous.

Next, an application example of the clock frequency dividing circuit of the present invention will be described.

FIG. 5 is an overall configuration diagram showing an example of a logic circuit device incorporating the clock frequency dividing circuit of the present invention.

This logic circuit device receives the input clock of the frequency f and outputs clocks of three kinds of frequencies f, f / 2 and f / 4.
1 and a PLL 54 which is a clock supply source for supplying the input clock having the frequency f to the clock frequency dividing circuit 51, and a clock line 53 for transmitting the input clock to the frequency dividing circuit 51 Buffering element 52
Is provided.

A combination circuit 61c is connected between the FFs 61a and 61b driven by the clock signal of the frequency f supplied from the frequency dividing circuit 51, and the FFs 62a and 62b driven by the clock signal of the frequency f / 2. Between them, combination circuits 62c and 62d are connected. An FF 63a driven at a frequency f / 4 and the FF 61b
Between the FF 63a and the FF 62b, a combination circuit 63b is connected, and to the output side of the FF 63a, a combination circuit 63c is connected.

The paths 71, 72, 73 in the figure are
It shows a path through which data is transferred between FFs driven at different clock frequencies.

When the clock signals of the frequencies f, f / 2 and f / 4 are supplied to the FFs by using the frequency dividers of the first and second conventional examples shown in FIGS. Since a positive or negative clock skew occurs between the frequencies, a decrease in the maximum operating frequency or a data skipping phenomenon occurs as expressed by the above equation (2).

Since there is no combinational circuit in the bus 73 that causes a signal delay between the FFs, the problem of "bypass" is particularly serious. "Blank" caused by negative skew
However, there is a fatal problem that the problem cannot be solved even if the operating frequency of the circuit is lowered, and the circuit configuration itself needs to be changed. On the other hand, if the clock frequency dividing circuit of the present invention is used, there is no skew between the clocks of the frequencies f, f / 2 and f / 4 as shown in FIG. The problem of "stick-through" can be avoided.

In comparison with the third conventional example shown in FIG. 11, in the third conventional example, the input clock frequency from the PLL 54 is twice as high as f × 2. There is a problem that the power consumed by the wiring 53 and the buffering element unit 52 existing between the frequency dividing circuits is doubled as compared with the case where the frequency dividing circuit of the present invention is used. On the other hand, the clock divider circuit of the present invention has the same clock frequency as the input clock frequency,
A clock signal having no skew with the divided clocks of f / 2 and f / 4 can be output.
Therefore, power consumption between the frequency dividing circuits 51 can be suppressed.

[0051]

As described above in detail, according to the clock frequency dividing circuit of the first invention, the count value holding unit is provided with a sequence for latching data at both rising and falling edges of the input clock. Since it is constituted by a circuit, it is possible to completely synchronize clock edges between clock waveforms of different frequencies, and it is possible to suppress a decrease in the maximum operating frequency and the occurrence of data skipping. Further, since the frequency of the input clock is only half that of the conventional circuit, the power consumed in the clock tree section up to the clock frequency dividing circuit can be reduced, and the influence of the parasitic inductance on the clock wiring is reduced. This has the effect of facilitating the design of the clock tree.

According to the clock divider circuit of the second invention, in the first invention, the counter circuit is constituted by a subtraction counter, so that the circuit of the first invention can be constituted simply and accurately. Can be.

According to the logic circuit device of the third invention,
Since the clock frequency dividing circuit according to the first aspect of the present invention is mounted, it is possible to avoid a reduction in operating frequency and a phenomenon of data skipping, and to suppress power consumption between the clock supply source and the clock frequency dividing circuit. Becomes possible.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a clock frequency dividing circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of an FF used in the clock frequency dividing circuit of FIG.

FIG. 3 is a circuit diagram showing another example of the FF used in the clock frequency dividing circuit of FIG.

FIG. 4 is a timing chart showing the operation of the embodiment.

FIG. 5 is an overall configuration diagram showing an example of a logic circuit device incorporating a clock frequency dividing circuit of the present invention.

FIG. 6 is a timing chart of the clock frequency dividing circuit shown in FIG. 5;

FIG. 7 is a block diagram showing an example of a conventional logic circuit in which a combinational circuit is connected between FFs.

FIG. 8 is a circuit diagram showing an example of Sgl-FF.

FIG. 9 is a diagram showing a conventional clock frequency dividing circuit (first conventional example).

FIG. 10 is a diagram showing a conventional clock frequency dividing circuit (second conventional example).

FIG. 11 is a diagram showing a conventional clock frequency dividing circuit (third conventional example).

[Explanation of symbols]

 , 10-n Dbl-FF 11 Clock supply lines 12-0, 12-1, ..., 12-n ExNOR 13-0, 13-1, ..., 13-n Inverter 14, 15 Inverter 16 2-input NOR gate 51 Clock divider circuit 52 Buffering element 53 Clock wiring 54 PLL 61a, 61b, 62a, 62b, 63a FF 61c, 62c, 62d, 63b, 63c Combination circuit 71, 72, 73 path

Claims (3)

[Claims] 1. A count value holding unit is constituted by n (positive integer) number of sequential circuits each latching data at an edge of a common input clock, and the count value holding unit is set to 0 according to the input clock.
And a counter circuit having an n-bit width for counting a binary number between 2 ⁿ -1 and 2 ⁿ -1.
From the count value holding unit, １ ／ of the input clock
A clock divider circuit for outputting a clock waveform having a frequency of (0 ≦ m <n), wherein the count value holding unit latches data at both rising and falling edges of the input clock. A clock frequency dividing circuit comprising: 2. The clock frequency dividing circuit according to claim 1, wherein said counter circuit comprises a subtraction counter. 3. A count value holding section is constituted by n (positive integer) number of sequential circuits each latching data at an edge of a common input clock, and the count value holding section is set to 0 according to the input clock.
And a counter circuit having an n-bit width for counting a binary number between 2 ⁿ -1 and 2 ⁿ -1.
From the count value holding unit, １ ／ of the input clock
A clock waveform having a frequency of (an integer satisfying 0 ≦ m <n) is output, and the count value holding unit is configured by a sequential circuit that latches data at both rising and falling edges of the input clock. A frequency divider, a clock supply source that supplies an input clock to the clock divider, and a plurality of sequential circuits driven by clock signals of a plurality of different frequencies generated by the clock divider. A logic circuit device that transfers data between sequential circuits.