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JPH11126951A - Printed circuit board and its manufacture - Google Patents

Printed circuit board and its manufacture

Info

Publication number
JPH11126951A
JPH11126951A JP9292592A JP29259297A JPH11126951A JP H11126951 A JPH11126951 A JP H11126951A JP 9292592 A JP9292592 A JP 9292592A JP 29259297 A JP29259297 A JP 29259297A JP H11126951 A JPH11126951 A JP H11126951A
Authority
JP
Japan
Prior art keywords
circuit board
printed circuit
pattern
conductor pattern
reinforced
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9292592A
Other languages
Japanese (ja)
Inventor
Hideki Tanaka
英樹 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Machinery Ltd
Original Assignee
Murata Machinery Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Machinery Ltd filed Critical Murata Machinery Ltd
Priority to JP9292592A priority Critical patent/JPH11126951A/en
Publication of JPH11126951A publication Critical patent/JPH11126951A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0263High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3485Applying solder paste, slurry or powder

Landscapes

  • Structure Of Printed Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PROBLEM TO BE SOLVED: To electrically or mechanically reinforce a conductor pattern formed on a printed wiring board without increasing the plane occupying areas of the pattern by forming conductive reinforcing layers of solder layers or electroless plated layers on the upper surfaces of the narrow parts of the pattern. SOLUTION: A conductor pattern 2 is formed on an insulating substrate 6 clad with copper foil. After a solder resist 5 is applied to pads 3 and the parts of the pattern 2 to be reinforced so that openings 5a may be positioned, cream solder is applied from the openings 5a. Electronic parts are mounted on the pads 3 by applying the cream solder to the pads 3 also and, during the course of the formation of a printed circuit board, the formation of conductive reinforcing layers 4 and the mounting of the electronic parts are performed simultaneously. The circuit board is heated and the reinforcing layers 4 are formed on the surfaces of the parts to be reinforced of the pattern 2. Therefore, the pattern 2 can be reinforced not only electrically against the increase of electric capacity, but also mechanically against shocks, etc.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、部品実装密度が大
きく、導体パターンの幅が極度に狭い部分を有する印刷
回路基板などにおいて、特に導体パターンの平面占有面
積を増やすことなく、導体パターンの電気的、機械的強
度の補強を図ることができるようにしたものに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board having a large component mounting density and an extremely narrow width of a conductor pattern, particularly without increasing the plane occupied area of the conductor pattern. The present invention relates to a device capable of reinforcing mechanical and mechanical strength.

【0002】[0002]

【従来の技術】従来より、各種電子機器に電子部品を実
装するための印刷回路基板が使用されてきている。印刷
回路基板としては、片面板(絶縁基板の片面だけに導体
パターンを形成したもの)、両面板(絶縁基板の表裏両
面に導体パターンを形成したもの)、多層板(絶縁基板
の表裏両面だけでなく、その内層部にも導体パターンを
形成したもの)があるが、近時の電子機器の小型化・高
密度実装化に伴い、印刷回路基板の高密度化が要求され
ており、最近では、両面板、多層板が多く使用されてい
る。
2. Description of the Related Art Conventionally, printed circuit boards for mounting electronic components on various electronic devices have been used. Printed circuit boards include single-sided boards (conductor patterns formed only on one side of the insulating board), double-sided boards (conductor patterns formed on both sides of the insulating board), and multilayer boards (only on both sides of the insulating board) However, there is also a conductor pattern formed on the inner layer part), but with the recent miniaturization and high-density mounting of electronic devices, higher density of printed circuit boards is required. Double-sided boards and multilayer boards are often used.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、印刷回
路基板の高密度化に伴って、部品実装密度が増大してい
くので、それに伴い、導体パターンの幅の狭い部分も増
えてしまう。ところが、導体パターンの幅の狭い部分
は、電流経路が小さくなっているので、電流容量の増大
に対して弱く、また、幅が狭いので衝撃などに対して弱
いといった欠点があり、電気的、機械的な面で補強する
ことが望まれる。
However, as the density of printed circuit boards is increased, the component mounting density is increased. As a result, the portion of the conductor pattern having a narrow width is also increased. However, the narrow portion of the conductor pattern has a drawback that the current path is small, so that it is weak against an increase in current capacity, and because the width is narrow, it is weak against impact and the like. It is desirable to reinforce it in terms of quality.

【0004】本発明は、上記問題を解決するために提案
されるものであり、導体パターンの平面占有面積を増大
させることなく、電気的または機械的に補強することが
できる印刷回路基板と、このような印刷回路基板を製造
する方法とを提供することを目的としている。
The present invention has been proposed to solve the above-mentioned problem, and a printed circuit board which can be reinforced electrically or mechanically without increasing the plane occupied area of a conductor pattern, and a printed circuit board having the same. And a method of manufacturing such a printed circuit board.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するため
に、請求項1に記載の印刷回路基板によれば、印刷回路
基板に形成された導体パターンのうち、幅の狭い部分の
上面に、はんだ層あるいは無電解めっき層による導電補
強層を形成した構造にしたことを特徴としている。
According to a first aspect of the present invention, there is provided a printed circuit board, comprising: a conductive pattern formed on the printed circuit board; It is characterized in that it has a structure in which a conductive reinforcing layer is formed by a solder layer or an electroless plating layer.

【0006】請求項2に記載の印刷回路基板の製造方法
によれば、サブストラクティブ法によって形成された導
体パターンを有した印刷回路基板の上面にソルダレジス
トを形成し、導体パターンの一部にクリームはんだを塗
布して電子部品を実装させる際に、導体パターンの補強
すべき幅の狭い部分には開口が位置するようにソルダレ
ジストを形成し、その開口にクリームはんだを盛り付け
た後、加熱して導電補強層を形成することを特徴として
いる。
According to a second aspect of the present invention, a solder resist is formed on an upper surface of a printed circuit board having a conductive pattern formed by a subtractive method, and a cream is formed on a part of the conductive pattern. When solder is applied and electronic components are mounted, a solder resist is formed so that an opening is located in the narrow part of the conductor pattern to be reinforced, cream solder is placed in the opening, and then heated. It is characterized in that a conductive reinforcing layer is formed.

【0007】請求項3に記載の印刷回路基板の製造方法
によれば、アディティブ法によって形成された導体パタ
ーンを有した印刷回路基板に、導体パターンの補強すべ
き部分のみを開口させたソルダレジストを形成した後、
その開口に無電解めっきを施すことによって、導電補強
層を形成することを特徴としている。本発明は、表面実
装基板、挿入実装基板のいずれに対しても適用できる。
According to a third aspect of the present invention, there is provided a printed circuit board having a conductor pattern formed by an additive method, wherein a solder resist having only a portion of the conductor pattern to be reinforced is opened. After forming
The conductive reinforcement layer is formed by applying electroless plating to the opening. The present invention can be applied to both surface mounting boards and insertion mounting boards.

【0008】[0008]

【発明の実施の形態】以下に、本発明の実施の形態につ
いて、図面を用いて説明する。図1は、サブストラクテ
ィブ法によって形成した印刷回路基板の一例を示す斜視
図である。印刷回路基板1において、2は導体パター
ン、3は、電子部品を実装するためのパッド(表面実装
用電子部品を実装させるための部分)、4は、クリーム
はんだを塗布して形成された導電補強層、5は開口5a
を形成したソルダレジスト、6は絶縁基板である。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a perspective view showing an example of a printed circuit board formed by a subtractive method. In the printed circuit board 1, 2 is a conductor pattern, 3 is a pad for mounting an electronic component (a portion for mounting an electronic component for surface mounting), and 4 is a conductive reinforcement formed by applying cream solder. Layer 5, opening 5a
Is a solder resist, and 6 is an insulating substrate.

【0009】図2は、サブストラクティブ法によって作
成された印刷回路基板1の要部縦断面構造を示してお
り、5はソルダレジスト、6は絶縁基板を示している。
図において、図1に示す印刷回路基板と同一の構成要素
については、参照符号を付して説明を省略する。図3
は、サブトラクティブ法によって印刷回路基板を作成す
る際に、導電補強層を形成する場合の手順をフローチャ
ートをもって示すものである。
FIG. 2 shows a vertical cross-sectional structure of a main part of the printed circuit board 1 prepared by the subtractive method. Reference numeral 5 denotes a solder resist, and 6 denotes an insulating substrate.
In the figure, the same components as those of the printed circuit board shown in FIG. FIG.
1 is a flowchart showing a procedure for forming a conductive reinforcing layer when a printed circuit board is prepared by a subtractive method.

【0010】まず、銅箔を張り付けた絶縁基板6に導体
パターン2を形成する。すなわち、絶縁基板の銅箔の表
面上に、エッチングレジストを塗布し(ステップ10
0)、エッチングレジストを施していない残りの銅箔を
薬品を用いて化学的に腐食(エッチング)させる(ステ
ップ101)。そうすれば、エッチングレジストを施し
た部分は、銅箔が腐食(エッチング)されないので、レ
ジストを剥離すれば導体パターンが基板表面に露出し、
形成される(ステップ102)。
First, a conductor pattern 2 is formed on an insulating substrate 6 to which a copper foil is attached. That is, an etching resist is applied on the surface of the copper foil of the insulating substrate (step 10).
0), the remaining copper foil not subjected to the etching resist is chemically corroded (etched) using a chemical (step 101). Then, since the copper foil is not corroded (etched) in the portion where the etching resist has been applied, the conductor pattern is exposed on the substrate surface when the resist is removed,
It is formed (step 102).

【0011】続いて、パッド3と導体パターン2の補強
すべき部分に開口5aが位置するようにソルダレジスト
5を施し(ステップ103)、その開口5aよりクリー
ムはんだを塗布する(ステップ104)。この際、パッ
ド3にもクリームはんだを塗布して、その上に電子部品
(不図示)を実装させれば(ステップ105)、印刷回
路基板の作成段階で、導電補強層4の形成と電子部品
(不図示)の実装とが同時にできるので、時間のロスが
少なくなり、経済的にもなる。
Subsequently, a solder resist 5 is applied so that the opening 5a is located at the portion of the pad 3 and the conductor pattern 2 to be reinforced (step 103), and a cream solder is applied from the opening 5a (step 104). At this time, cream solder is also applied to the pads 3 and electronic components (not shown) are mounted thereon (step 105). At the stage of forming the printed circuit board, the formation of the conductive reinforcing layer 4 and the electronic components are performed. Since mounting (not shown) can be performed at the same time, loss of time is reduced, and it is economical.

【0012】クリームはんだを塗布する際、パッド3が
密集している箇所や、導体パターン2を補強すべき部分
がパッド3に近接している箇所では、隣接するパッド3
間、または、導体パターン2の補強したい部分とパッド
3との間でクリームはんだが跨って塗布されることがあ
るので、このような場合には、クリームはんだを塗布す
べき部分に対応して開口を形成したメタルマスクを用い
るとよい。
When the cream solder is applied, in a place where the pads 3 are dense or where a part where the conductor pattern 2 is to be reinforced is close to the pad 3,
In some cases, the cream solder is applied between the pads or between the portion of the conductor pattern 2 to be reinforced and the pad 3. In such a case, the opening corresponding to the portion to which the cream solder is to be applied is provided. It is preferable to use a metal mask on which is formed.

【0013】最後に、回路基板を加熱すれば、導体パタ
ーン2の補強したい部分の表面上に導電補強層4が形成
される(ステップ106)。図4は、アディティブ法に
よって形成された印刷回路基板1に対して適用された本
発明の他例を示し、図5はその要部縦断面構造を示す図
であり、7はめっきレジストである。
Finally, when the circuit board is heated, the conductive reinforcing layer 4 is formed on the surface of the portion of the conductor pattern 2 to be reinforced (step 106). FIG. 4 shows another example of the present invention applied to the printed circuit board 1 formed by the additive method. FIG. 5 is a view showing a longitudinal sectional structure of a main part thereof, and 7 is a plating resist.

【0014】なお、図において、図1に示す印刷回路基
板と同一の構成要素については、前例と同様、参照符号
を付して説明を省略する。この例では、絶縁基板6の上
面に形成された導体パターン2は、その先端に、スルー
ホール8aを有したランド8を形成しており、この導体
パターン2の全体は、ソルダレジスト5によってその全
体が被覆され、ソルダレジスト5の開口部5aより無電
解めっき層によって形成された導電補強層4が露出して
いる。
In the figure, the same components as those of the printed circuit board shown in FIG. 1 are denoted by the same reference numerals as in the previous example, and description thereof is omitted. In this example, the conductor pattern 2 formed on the upper surface of the insulating substrate 6 has a land 8 having a through hole 8a formed at the tip thereof, and the entire conductor pattern 2 is entirely formed by the solder resist 5. And the conductive reinforcing layer 4 formed by the electroless plating layer is exposed from the opening 5 a of the solder resist 5.

【0015】このようなアディティブ法によって形成さ
れる印刷回路基板1に、導電補強層4を形成する場合に
は、図5によって示されているように、無電解めっき層
によって形成された導電補強層4は、ソルダレジスト5
との面一に形成され、突出することがないので、見かけ
もよい上に、補強効果も高い。また、この方法によれ
ば、無電解めっき層によって形成された導体パターン2
の上面に、同じ無電解めっきを施して導電補強層4を形
成するため、電流密度が均一となる上に、物理的な接合
強度も一層高くできる。
When the conductive reinforcing layer 4 is formed on the printed circuit board 1 formed by such an additive method, as shown in FIG. 5, the conductive reinforcing layer formed by the electroless plating layer is used. 4 is a solder resist 5
Since they are formed flush with each other and do not protrude, the appearance is good and the reinforcing effect is high. Further, according to this method, the conductor pattern 2 formed by the electroless plating layer
Since the same electroless plating is performed on the upper surface of the conductive layer to form the conductive reinforcing layer 4, the current density becomes uniform and the physical bonding strength can be further increased.

【0016】図6は、アディティブ法によって印刷回路
基板を作成する際に、導電補強層を形成する場合の手順
をフローチャートでもって示すものである。まず、絶縁
基板に導体パターンを形成する。すなわち、導体パター
ンを形成すべき絶縁基板の表面上に、めっきレジストを
施し(ステップ200)、その上方より無電解めっきを
施す(ステップ201)。
FIG. 6 is a flowchart showing a procedure for forming a conductive reinforcing layer when a printed circuit board is formed by the additive method. First, a conductor pattern is formed on an insulating substrate. That is, a plating resist is applied on the surface of an insulating substrate on which a conductor pattern is to be formed (step 200), and electroless plating is applied from above (step 201).

【0017】すると、めっきレジストを施さない部分は
めっきされ、導体パターンが形成される。また、残った
めっきレジストは電気絶縁性皮膜であるので、特に剥離
する必要がなく残しておく。続いて、パッドと導体パタ
ーンの補強すべき部分に開口が位置するようにソルダレ
ジスト印刷を施す(ステップ202)。
Then, the portion not subjected to the plating resist is plated to form a conductor pattern. Since the remaining plating resist is an electrically insulating film, it does not need to be peeled off and is left. Subsequently, solder resist printing is performed so that an opening is located at a portion of the pad and the conductor pattern to be reinforced (step 202).

【0018】その後、開口に無電解めっきを施せば、そ
の開口には無電解めっき層が形成され、導電補強層が形
成できる(ステップ203)。
After that, if electroless plating is applied to the opening, an electroless plating layer is formed in the opening, and a conductive reinforcing layer can be formed (step 203).

【0019】[0019]

【発明の効果】以上の説明から理解できるように、請求
項1に記載の印刷回路基板によれば、導体パターンのう
ち、幅の狭い部分の上面に、はんだ層あるいは無電解め
っき層による導電補強層を形成しているので、導体パタ
ーンの平面占有面積を増大させることなく、電流経路を
大きくして、電流容量の増大に対しても電気的に補強で
き、更に、衝撃などに対しても機械的に補強できる。
As can be understood from the above description, according to the printed circuit board of the first aspect, the conductive pattern is strengthened by the solder layer or the electroless plating layer on the upper surface of the narrow portion of the conductive pattern. Since the layer is formed, the current path can be enlarged without increasing the plane occupied area of the conductor pattern, and it can be electrically reinforced against an increase in current capacity. Can be reinforced.

【0020】請求項2に記載の印刷回路基板の製造方法
によれば、電子部品を実装させる際に、補強すべき幅の
狭い部分には開口が位置するようにソルダレジストを形
成した後、その開口にクリームはんだを盛り付け、加熱
することによって、導電補強層の形成と電子部品の実装
とが同時にできるので、製造工程の簡略化、コストの低
減化が図れる。
According to the method of manufacturing a printed circuit board of the present invention, when mounting an electronic component, a solder resist is formed so that an opening is located in a narrow portion to be reinforced, and then the solder resist is formed. By applying cream solder to the opening and heating, the formation of the conductive reinforcing layer and the mounting of the electronic component can be performed at the same time, so that the manufacturing process can be simplified and the cost can be reduced.

【0021】請求項3に記載の印刷回路基板の製造方法
によれば、導電補強層は、導体パターンと同じく無電解
めっきで形成されているので、電流密度が均一になる上
に、接合強度も強いので、機械的な強度もより一層強く
することもできる。
According to the method of manufacturing a printed circuit board according to the third aspect, since the conductive reinforcing layer is formed by electroless plating as in the case of the conductor pattern, the current density becomes uniform and the joining strength is improved. Since it is strong, the mechanical strength can be further increased.

【図面の簡単な説明】[Brief description of the drawings]

【図1】サブストラクティブ法によって形成した印刷回
路基板の一例を示す斜視図である。
FIG. 1 is a perspective view showing an example of a printed circuit board formed by a subtractive method.

【図2】サブストラクティブ法によって作成された印刷
回路基板の要部縦断面構造を示す図である。
FIG. 2 is a diagram illustrating a vertical cross-sectional structure of a main part of a printed circuit board created by a subtractive method.

【図3】サブトラクティブ法によって印刷回路基板を作
成する際に、導電補強層を形成する場合の手順を示すフ
ローチャートである。
FIG. 3 is a flowchart showing a procedure for forming a conductive reinforcing layer when a printed circuit board is produced by a subtractive method.

【図4】アディティブ法によって形成した印刷回路基板
の一例を示す斜視図である。
FIG. 4 is a perspective view showing an example of a printed circuit board formed by an additive method.

【図5】アディティブ法によって作成された印刷回路基
板の要部縦断面構造を示す図である。
FIG. 5 is a diagram showing a vertical cross-sectional structure of a main part of a printed circuit board prepared by an additive method.

【図6】アディティブ法によって印刷回路基板を作成す
る際に、導電補強層を形成する場合の手順を示すフロー
チャートである。
FIG. 6 is a flowchart showing a procedure for forming a conductive reinforcing layer when a printed circuit board is produced by an additive method.

【符号の説明】[Explanation of symbols]

1 印刷回路基板 2 導体パターン 4 導電補強層 5 ソルダレジスト Reference Signs List 1 printed circuit board 2 conductive pattern 4 conductive reinforcing layer 5 solder resist

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】印刷回路基板に形成された導体パターンの
うち、幅の狭い部分の上面に、はんだ層あるいは無電解
めっき層による導電補強層を形成した構造にした印刷回
路基板。
1. A printed circuit board having a structure in which a conductive reinforcing layer of a solder layer or an electroless plating layer is formed on an upper surface of a narrow portion of a conductor pattern formed on the printed circuit board.
【請求項2】サブストラクティブ法によって形成された
導体パターンを有した印刷回路基板の上面にソルダレジ
ストを形成し、導体パターンの一部にクリームはんだを
塗布して電子部品を実装させる際に、導体パターンの補
強すべき幅の狭い部分には開口が位置するようにソルダ
レジストを形成し、その開口にクリームはんだを盛り付
けた後、加熱して導電補強層を形成することを特徴とす
る印刷回路基板の製造方法。
2. A method according to claim 1, wherein a solder resist is formed on an upper surface of a printed circuit board having a conductor pattern formed by a subtractive method, and a cream solder is applied to a part of the conductor pattern to mount an electronic component. A printed circuit board, wherein a solder resist is formed so that an opening is located in a narrow portion of a pattern to be reinforced, a cream solder is applied to the opening, and then heating is performed to form a conductive reinforcing layer. Manufacturing method.
【請求項3】アディティブ法によって形成された導体パ
ターンを有した印刷回路基板に、導体パターンの補強す
べき部分のみを開口させたソルダレジストを形成した
後、その開口に無電解めっきを施すことによって、導電
補強層を形成することを特徴とする印刷回路基板の製造
方法。
3. A printed circuit board having a conductor pattern formed by an additive method, wherein a solder resist having an opening only in a portion of the conductor pattern to be reinforced is formed, and then the opening is subjected to electroless plating. And a method of manufacturing a printed circuit board, comprising forming a conductive reinforcing layer.
JP9292592A 1997-10-24 1997-10-24 Printed circuit board and its manufacture Pending JPH11126951A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9292592A JPH11126951A (en) 1997-10-24 1997-10-24 Printed circuit board and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9292592A JPH11126951A (en) 1997-10-24 1997-10-24 Printed circuit board and its manufacture

Publications (1)

Publication Number Publication Date
JPH11126951A true JPH11126951A (en) 1999-05-11

Family

ID=17783784

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9292592A Pending JPH11126951A (en) 1997-10-24 1997-10-24 Printed circuit board and its manufacture

Country Status (1)

Country Link
JP (1) JPH11126951A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009054414A1 (en) * 2007-10-22 2009-04-30 Nec Corporation Semiconductor device
EP1487018A3 (en) * 2003-06-12 2010-09-01 Samsung Electronics Co., Ltd. Flexible substrate for a semiconductor package and method of manufacturing the same
EP2741591A1 (en) * 2012-12-10 2014-06-11 Robert Bosch Gmbh Method for producing a circuit board with increased conductivity
US11431830B2 (en) 2018-03-08 2022-08-30 Samsung Electronics Co., Ltd. Circuit board including conductive structure for electrically connecting wires, and electronic device including same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1487018A3 (en) * 2003-06-12 2010-09-01 Samsung Electronics Co., Ltd. Flexible substrate for a semiconductor package and method of manufacturing the same
US8110918B2 (en) 2003-06-12 2012-02-07 Samsung Electronics Co., Ltd. Flexible substrate for a semiconductor package, method of manufacturing the same, and semiconductor package including flexible substrate
US8796158B2 (en) 2003-06-12 2014-08-05 Samsung Electronics Co., Ltd. Methods for forming circuit pattern forming region in an insulating substrate
WO2009054414A1 (en) * 2007-10-22 2009-04-30 Nec Corporation Semiconductor device
US8344498B2 (en) 2007-10-22 2013-01-01 Nec Corporation Semiconductor device
JP5644107B2 (en) * 2007-10-22 2014-12-24 日本電気株式会社 Semiconductor device
EP2741591A1 (en) * 2012-12-10 2014-06-11 Robert Bosch Gmbh Method for producing a circuit board with increased conductivity
US11431830B2 (en) 2018-03-08 2022-08-30 Samsung Electronics Co., Ltd. Circuit board including conductive structure for electrically connecting wires, and electronic device including same

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