JPH033354A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH033354A JPH033354A JP1138708A JP13870889A JPH033354A JP H033354 A JPH033354 A JP H033354A JP 1138708 A JP1138708 A JP 1138708A JP 13870889 A JP13870889 A JP 13870889A JP H033354 A JPH033354 A JP H033354A
- Authority
- JP
- Japan
- Prior art keywords
- package
- outer leads
- protrude
- parallel
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- H10W90/756—
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は実装基板に対して表面実装を行う半導体装置に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device that is surface mounted on a mounting board.
従来、この種の半導体装置は、第6図にその一例を示す
ように、リードフレーム21の素子搭載部22に半導体
素子チップ23を搭載し、ボンディングワイヤ・24に
よりインナリード25に電気接続する。そして、これら
を樹脂等のパッケージ26で封止した後、アウタリード
2.7を所要形状に他げ形成している。Conventionally, in this type of semiconductor device, as shown in FIG. 6, a semiconductor element chip 23 is mounted on an element mounting portion 22 of a lead frame 21 and electrically connected to an inner lead 25 by a bonding wire 24. After these are sealed with a package 26 made of resin or the like, outer leads 2.7 are formed into a desired shape.
そして、この半導体装置は、パッケージ26の底面を接
着剤12により実装基板11に接着するとともに、アウ
タリード27を半田13により回路パターンに接続して
表面実装を行っている。This semiconductor device is surface-mounted by bonding the bottom surface of the package 26 to the mounting board 11 with the adhesive 12 and connecting the outer leads 27 to the circuit pattern with the solder 13.
上述した従来の半導体装置は、パッケージ26の外部に
おいてアウタリード27を曲げ加工しているため、この
加工精度のばらつきによってパッケージ26の底面に対
するアウタリード27の高さ位置にばらつきが生じ易く
、これが原因して好適な表面実装ができなくなるという
問題がある。In the conventional semiconductor device described above, the outer leads 27 are bent outside the package 26, so variations in the processing accuracy tend to cause variations in the height position of the outer leads 27 with respect to the bottom surface of the package 26. There is a problem that suitable surface mounting cannot be performed.
即ち、アウタリード27がパッケージ26の底面よりも
高い位置に曲げ加工されたときには、パッケージ26の
底面を接着剤12により実装基板11に接着すると、ア
ウタリード27と実装基板11の回路パターンとの隙間
が大きくなり過ぎ、半田等で接続することができなくな
る。That is, when the outer lead 27 is bent to a position higher than the bottom surface of the package 26, when the bottom surface of the package 26 is bonded to the mounting board 11 with the adhesive 12, the gap between the outer lead 27 and the circuit pattern of the mounting board 11 becomes large. If it becomes too much, it will not be possible to connect with solder, etc.
また、逆にアウタリード27がパッケージ26の底面よ
りも低い位置に曲げ加工されたときには、アウターリー
ド27が実装基板11の回路パターンに当接したときに
パッケージ26の底面と実装基板11との隙間が大きく
なり過ぎ、接着剤12による仮付けが不可能になる。On the other hand, when the outer leads 27 are bent to a position lower than the bottom surface of the package 26, when the outer leads 27 come into contact with the circuit pattern of the mounting board 11, the gap between the bottom surface of the package 26 and the mounting board 11 increases. It becomes too large and temporary attachment with adhesive 12 becomes impossible.
本発明は表面実装を確実に行うことができるように構成
した半導体装置を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device configured so that surface mounting can be performed reliably.
〔課題を解決するための手段]
本発明の半導体装置は、半導体素子チップ等を封止した
パッケージから突出されるアウタリードを、パッケージ
の底面と同一面でかつ底面と平行に突出させている。[Means for Solving the Problems] In the semiconductor device of the present invention, an outer lead protruding from a package in which a semiconductor element chip or the like is sealed is made to protrude on the same plane as and parallel to the bottom surface of the package.
この構成では、パッケージの底面とアウタリードとを実
装基板の同一面上に配設でき、パッケージの接着及びア
ウタリードの半田付けをそれぞれ確実に実行できる。With this configuration, the bottom surface of the package and the outer leads can be disposed on the same surface of the mounting board, and the bonding of the package and the soldering of the outer leads can be respectively performed reliably.
〔実施例〕 次に、本発明を図面を参照して説明する。〔Example〕 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.
図において、リードフレームlの素子搭載部2に半導体
素子チップ3を搭載し、ボンディングワイヤ4によりイ
ンナリード5に電気接続している。In the figure, a semiconductor element chip 3 is mounted on an element mounting portion 2 of a lead frame l, and is electrically connected to inner leads 5 by bonding wires 4.
そして、これらを樹脂で封止してパッケージ6を構成し
、このパッケージ6の下側周縁部から、パッケージ6の
底面と同一面でかつ底面と平行にアウタリード7を突出
形成している。These are sealed with resin to form a package 6, and an outer lead 7 is formed to protrude from the lower peripheral edge of the package 6, flush with and parallel to the bottom surface of the package 6.
第2図は第1図の半導体装置を形成するために使用する
リードフレーム1の斜視図であり、このリードフレーム
1は素子搭載部2の付近でインナリード5を階段状に曲
げ加工し、かつアウタリード7は素子搭載部2と平行に
向けている。FIG. 2 is a perspective view of the lead frame 1 used to form the semiconductor device of FIG. The outer lead 7 is oriented parallel to the element mounting section 2.
そして、このリードフレーム1の素子搭載部2に半導体
素子チップ3を搭載した後、第3図に示すように、アウ
タリード7と同一面上に離型面を有する一対の樹脂封止
金型A、 Bにてアウタリード7をクランプし、これら
の金型A、Bを用いて樹脂封止を行うことにより、第1
図のパッケージ6を形成でき、パッケージ6の底面とア
ウタリード7とを同一面上に形成できる。After mounting the semiconductor element chip 3 on the element mounting portion 2 of this lead frame 1, as shown in FIG. By clamping the outer lead 7 at B and performing resin sealing using these molds A and B, the first
The package 6 shown in the figure can be formed, and the bottom surface of the package 6 and the outer leads 7 can be formed on the same surface.
この構成の半導体装置によれば、第4図に示すように、
半導体装置を実装基板11に実装する際には、パッケー
ジ6の底面を接着剤12で接着する。すると、パッケー
ジ6の底面とアウタリード7とは同一面上であるために
、アウタリード7と実装基板11との間には常に接着剤
12の厚さに相当する寸法の隙間が構成される。実際に
は、アウタリード7は配線パターン上に位置されるため
、その隙間は極めて小さなものとなる。これにより、ア
ウタリード7を半田13により確実に接続することが可
能となる。According to the semiconductor device with this configuration, as shown in FIG.
When mounting the semiconductor device on the mounting board 11, the bottom surface of the package 6 is bonded with an adhesive 12. Then, since the bottom surface of the package 6 and the outer leads 7 are on the same plane, a gap with a size corresponding to the thickness of the adhesive 12 is always formed between the outer leads 7 and the mounting board 11. Actually, since the outer lead 7 is located on the wiring pattern, the gap therebetween is extremely small. This makes it possible to reliably connect the outer leads 7 with the solder 13.
第5図は本発明の他の実施例の断面図である。FIG. 5 is a sectional view of another embodiment of the invention.
この実施例ではパッケージ6の底面の略中央部に逆凹状
の溝6aを設けている点が前記実施例とは相違している
。This embodiment differs from the previous embodiments in that a reversely concave groove 6a is provided in the approximate center of the bottom surface of the package 6.
このように逆凹状の溝6aを設けることにより、半導体
装置を実装基板に接着する際の接着剤12を厚く塗布す
ることができるため、接着剤の塗布量の制御が容易にな
る利点がある。By providing the groove 6a in the reverse concave shape in this way, the adhesive 12 can be applied thickly when bonding the semiconductor device to the mounting board, so there is an advantage that the amount of adhesive applied can be easily controlled.
〔発明の効果]
以上説明したように本発明は、パッケージから突出され
るアウタリードを、パッケージの底面と同一面でかつ底
面と平行に突出させているので、パッケージ底面とアウ
タリードとの間の相対位置のばらつきを無くすことがで
き、実装に際してパッケージの底面とアウタリードとを
実装基板の同一面上に配設でき、パッケージの接着及び
アウタリードの半田付けをそれぞれ確実に実行できる効
果がある。[Effects of the Invention] As explained above, in the present invention, the outer leads protruding from the package are made to protrude on the same plane and parallel to the bottom surface of the package, so that the relative position between the bottom surface of the package and the outer leads is This has the effect that the bottom surface of the package and the outer leads can be disposed on the same surface of the mounting board during mounting, and that the bonding of the package and the soldering of the outer leads can be performed reliably.
また、パッケージ後にアウタリードを曲げ加工する工程
が不要となり、半導体装置を安価に製造できる効果もあ
る。Further, the process of bending the outer leads after packaging is not necessary, which has the effect of making it possible to manufacture semiconductor devices at low cost.
第1図は本発明の一実施例の断面図、第2図はリードフ
レームの斜視図、第3図はパッケージの製造方法を示す
断面図、第4図は実装状態を示す断面図、第5図は本発
明の他の実施例の断面図、第6図は従来の半導体装置の
実装状態を示す断面図である。
■10.リードフレーム、2・・・素子搭載部、3・・
・半導体素子チップ、4・・・ボンディングワイヤ、5
・・・インナリード、6・・・パッケージ、6a・・・
溝、7・・・アウタリード、11・・・実装基板、12
・・・接着剤、13・・・半田、21・・・リードフレ
ーム、22・・・素子搭載部、23・・・半導体素子チ
ップ、24・・・ボンディングワイヤ、25・・・イン
ナリード、26・・・パッケージ、27・・・アウタリ
ード。FIG. 1 is a sectional view of an embodiment of the present invention, FIG. 2 is a perspective view of a lead frame, FIG. 3 is a sectional view showing a package manufacturing method, FIG. 4 is a sectional view showing a mounting state, and FIG. This figure is a cross-sectional view of another embodiment of the present invention, and FIG. 6 is a cross-sectional view showing a mounting state of a conventional semiconductor device. ■10. Lead frame, 2... Element mounting section, 3...
・Semiconductor element chip, 4... Bonding wire, 5
...Inner lead, 6...Package, 6a...
Groove, 7... Outer lead, 11... Mounting board, 12
...Adhesive, 13...Solder, 21...Lead frame, 22...Element mounting portion, 23...Semiconductor element chip, 24...Bonding wire, 25...Inner lead, 26 ...Package, 27...Outer lead.
Claims (1)
ケージ封止し、このパッケージからアウタリードを突出
した表面実装型の半導体装置において、前記アウタリー
ドをパッケージの底面と同一面でかつ底面と平行に突出
したことを特徴とする半導体装置。1. In a surface-mounted semiconductor device in which a semiconductor element chip is mounted on a lead frame and sealed in a package, and outer leads protrude from the package, the outer leads protrude on the same plane as and parallel to the bottom surface of the package. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1138708A JPH033354A (en) | 1989-05-31 | 1989-05-31 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1138708A JPH033354A (en) | 1989-05-31 | 1989-05-31 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH033354A true JPH033354A (en) | 1991-01-09 |
Family
ID=15228272
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1138708A Pending JPH033354A (en) | 1989-05-31 | 1989-05-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH033354A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4318727A1 (en) * | 1992-06-05 | 1993-12-09 | Mitsubishi Electric Corp | Semiconductor device with LOC structure and associated manufacturing method and associated lead wire frame |
| EP0623954A1 (en) * | 1993-05-07 | 1994-11-09 | AT&T Corp. | Molded plastic packaging of electronic devices |
-
1989
- 1989-05-31 JP JP1138708A patent/JPH033354A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4318727A1 (en) * | 1992-06-05 | 1993-12-09 | Mitsubishi Electric Corp | Semiconductor device with LOC structure and associated manufacturing method and associated lead wire frame |
| US5724726A (en) * | 1992-06-05 | 1998-03-10 | Mitsubishi Denki Kabushiki Kaisha | Method of making leadframe for lead-on-chip (LOC) semiconductor device |
| DE4318727C2 (en) * | 1992-06-05 | 1998-03-12 | Mitsubishi Electric Corp | Process for the production of a semiconductor device with LOC structure and associated leadframe |
| US5900582A (en) * | 1992-06-05 | 1999-05-04 | Mitsubishi Denki Kabushiki Kaisha | Lead frame including frame-cutting slit for lead-on-chip (LOC) semiconductor device and semiconductor device incorporating the lead frame |
| EP0623954A1 (en) * | 1993-05-07 | 1994-11-09 | AT&T Corp. | Molded plastic packaging of electronic devices |
| US5548087A (en) * | 1993-05-07 | 1996-08-20 | At&T Corp. | Molded plastic packaging of electronic devices |
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