JPH031660A - Method and apparatus for processing picture - Google Patents

Abstract

PURPOSE:To easily obtain an excellent magnified picture without picture quality deterioration by providing 1st and 2nd prescribed magnification processing means and switching them depending on the arrangement state of corresponding picture element data groups. CONSTITUTION:The apparatus consists of a repetition designation circuit 30, a shift register 21, a clock changeover circuit 25, a discrimination circuit 22 and a clock oscillator 24 or the like. At first a picture data stored in a video memory 1 is read in parallel for each line and stored in the register 21. Then an output bit data and a succeeding bit data are loaded in parallel every time the data is outputted for each shift based on the shift clock from the circuit 23 and when both the data are consecutive black or white dots, the processing is stopped by one clock to apply repetitive processing of the output picture element data D2. On the other hand, when both the data are combined dots, the clock of the circuit 23 is switched by a discrimination output of the circuit 22, the 2nd readout clock is outputted and the corresponding data D2 and the succeeding picture element data D3 are read based thereon. After the end, the clock is switched into the 1st clock and the processing above is repeated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing method and apparatus for use in facsimiles, printers, image scanners, etc., which have an image enlarger unit, and in particular, relates to an image processing method and apparatus for composing an image. The present invention relates to an image processing method and apparatus for enlarging an image while repeatedly processing pixels or pixel lines (hereinafter collectively referred to as pixel data) at appropriate intervals.

``Prior Art'' Conventionally, facsimile image scanners sometimes enlarge image data read by an image sensor to a predetermined size and transmit it to the other receiver, and laser printers and other page printers also enlarge the image data read by an image sensor and transmit it to the other receiver. There are cases where the image data developed in memory is enlarged to a predetermined size and output to the print engine side, and one method for enlarging such image data to a predetermined size is, for example, by converting image data in the main scanning line direction to a predetermined pixel clock. In the device 6 that performs image processing while alternately writing and reading data into a plurality of line buffers based on frequency, pixel data located at intervals corresponding to a predetermined magnification rate of the image data is repeatedly read out during the reading process. There is a method for expanding one image data by substantially increasing the number of pixels. (Unexamined Japanese Patent Publication No. 82-24787
(No. 3 and others, hereinafter referred to as the first prior art) "Problem to be solved by the invention" However, in the first prior art.

Since the repetition interval and position can be arbitrarily set using a counter or registration means, a highly accurate enlargement ratio can be obtained. In order to perform repeated processing by thinning out the pixel data and stopping the readout of one pixel, the output time of the repeated pixel data is twice the output time of other adjacent pixel data, and as a result, only the repeated pixel data Since the $ is output in an extended state, the image distortion in that part becomes large, which tends to cause problems in image reproducibility, legibility, etc.

In order to eliminate this drawback and achieve accurate image reproducibility without image distortion, it is possible to change the frequency division ratio of the original oscillation clock in accordance with the enlargement ratio, thereby reducing the clock for writing to and reading from the storage means. Technology that changes the clock frequency ratio, in other words, uniformly expands the pixel pattern density (
There is also a second prior art (hereinafter referred to as the second prior art), but in order to obtain a finer enlargement rate, the oscillation clock must be made that much faster. In particular, the enlarged size of the image is, for example, 115% (B5
→A4) 122% (A4→84) 141% (A4→
As shown in A3), it is not possible to obtain a common greatest common divisor with a single-digit frequency division ratio, and in order to obtain a highly accurate magnification ratio, a frequency divider with a predetermined frequency division ratio for each magnification size is required. must be prepared, resulting in problems such as a complicated device configuration.

In view of the drawbacks of the prior art, the present invention provides an image processing method capable of producing 4τ enlarged images that are preferable in terms of image reproducibility and readability, without complicating the device configuration or making image distortion noticeable. The purpose is to provide such equipment.

"Means to solve problems" The progress that led to the present invention will be explained.

First, in the method of enlarging only one pixel located at the pixel interval corresponding to the enlargement ratio, as in the first prior art, only the output time of the pixel in that part is doubled, which causes image distortion. It is inevitable that it will occur.

In addition, as shown in the second conventional technique, in a method of uniformly enlarging all pixel pattern densities on one image line, it is difficult to obtain a divided clock corresponding to the enlargement rate, which causes problems in terms of enlargement accuracy. .

Therefore, in the first invention described in claim 1), although the corresponding pixel is enlarged at each pixel interval set based on the target enlargement ratio, only the negative pixels are subjected to the enlargement process. By enlarging the pixel data (number of pixels: n2) adjacent to one output pixel data located at the pixel interval, the number of processed pixels n(n2
+1), the output time of the pixel group is made to approach the output time (TI) of the normal pixel, and more specifically, the output time T is made to approximately match TIX [(1+n)/n]. By outputting the pixel data using a second read clock different from that of other pixel data, it is intended to reduce as much as possible the occurrence of image distortion caused by the difference in output time.

For example, when reading out the output pixel data and the next pixel data at each corresponding pixel interval, it is sufficient to substitute 2 for n in the above equation, so the output time T is 1.5 of the normal readout time. The output time will be close to that of a normal pixel,
In such a case, an inverted clock having the same cycle and a different phase as the normal read clock may be used as the second clock, as shown in the embodiment described later.

Therefore, in the first aspect of the present invention, since the target magnification rate is set based on the pixel spacing as in the first prior art, accurate magnification processing is possible, and the pixel data group at the spacing position is set. is simply outputted using the second readout clock.In other words, unlike the second prior art, there is no need to prepare multiple readout clocks with different frequencies corresponding to the target magnification ratio; It is sufficient to prepare a first read clock for reading out the output time and a second read clock for obtaining the output time without complicating the device configuration.

In addition, when the same pixel group is continuous as shown in FIG. 3, in other words, when black dots or white dots are continuous, even if the enlargement process is performed based on the first invention, Even if the enlargement process is performed on the first prior art, the output data states of the corresponding pixel groups remain the same, so there is no particular point in adopting the first invention.

Therefore, the invention described in claim 3) includes a first enlargement processing means for repeatedly processing the corresponding pixel data based on a specified signal output at every arbitrary pixel interval depending on the arrangement state of the corresponding pixel data group. , the second enlargement processing means for reading out one or more corresponding pixel data by switching to a second clock different from the readout clock based on the specified signal is configured to be selectively switchable. It is something.

Further, such an invention includes: temporary storage means for storing at least a plurality of pixel data before and after output while sequentially shifting based on the readout clock; a determination circuit that loads a plurality of pixel data stored in parallel and determines whether at least the output pixel data and the next pixel data are the same pixel data; The two enlargement means may be configured to be selectively switchable = "Embodiment" Hereinafter, preferred embodiments of the present invention will be described in detail by way of example with reference to the drawings. However, unless otherwise specified, the dimensions, materials, shapes, and relative arrangements of the components described in this example are not intended to limit the scope of this invention, but are merely illustrative examples. It's nothing more than that.

FIG. 1 is an overall two-dimensional diagram showing an image processing apparatus according to an embodiment of the present invention used in a laser printer. To briefly explain the configuration of the apparatus, l is a video memory, and a controller (not shown) Using a predetermined image input clock, image data corresponding to one page is enlarged in the sub-scanning direction, developed into dots, and stored.

Reference numeral 21 denotes a shift register that reads out the image data stored in the video memory 1 in parallel for each main scanning line or n bits at a time and stores it as line-shaped image data, which is selectively output from the clock switching circuit 23. It is configured to be able to serially output video while sequentially shifting stored image data based on a shift (read) clock.

Reference numeral 22 denotes a determination circuit, which outputs 2 to n bits of data DI- every time the shift clock is output to the shift register 21 side.
If the output data and the next data are consecutive black dots (1) or white dots (0) when reading out "ON" in parallel, the determination circuit 22 outputs an "O" determination output by closing 2.
It is configured so that it can be sent to the switching circuit 23 side.

A clock oscillator 24 generates a first readout clock synchronized with the image input clock, and an inverter 25 inverts the readout clock and generates an inverted clock having the same period and a different phase as the normal readout clock as a second readout clock. The signals are respectively input to the clock switching circuit 23 side.

The clock switching circuit 23 selects "O" or "1" sent from the determination circuit 22 every time the repetition designation signal generation circuit 30 outputs a designation signal at a pixel interval corresponding to the enlargement ratio.
Based on the judgment output of the clock oscillator 24 or its inverted clock by the inverter 25, the read clock is selectively switched, and the corresponding read clocks ■, ■ are changed to the shift register 2! It is configured so that it can be sent to the side.

As shown in FIG. 5, the repetition designation circuit 30 includes a latch register 301 that stores a bit pattern corresponding to the enlargement rate.
, a cyclic shift register 302 into which a bit pattern is loaded from the latch register 301 at each start of main scanning or at appropriate intervals; and a cyclic shift register 302 that is fed back by a control signal from the MPU in accordance with the bit length of the bit pattern. Selection circuit 30 for selecting bit position
3, and by supplying the shift clock SC to the shift register 302, a repetition designation signal corresponding to the bit pattern can be generated from the output terminal 302a of the shift register 302.

For example, r 1oaooooolo
oo.

By setting 00J, the repetition designation signal with a scaling factor of approximately 115% (B5→A0) at intervals of - every 7 bits is
Also, by setting r 1oololaolaJ, 2
It is possible to obtain a repetition designation signal having an enlargement rate of approximately 141% (A4→A3) at intervals of - every 3 bits.

Next, the present invention will be explained in detail.

First, the image data stored in the video memory 1 is read out in parallel for each main scanning line and transferred to the shift register 21.
After the data is stored in , it is sequentially shifted based on a shift clock selectively outputted from the clock switching circuit 23 and is serially videoed.

Then, each time the output bit data is output to the determination circuit 22 side for each shift, the output bit data and the next bit data are loaded in parallel, and if both data are continuous black dots (1) or white dots (0), “O” from the judgment circuit 22
The determination output is sent to the clock switching circuit 23 side.

As a result, the shift clock synchronized with the human input clock for the image without clock switching in the clock switching circuit 23 is sent as is to the shift register 21 side, and the repetition designation signal is sent at every bit interval corresponding to the target enlargement rate. is sent out, the output of the shift clock is stopped for one clock based on the designated signal, thereby repeatedly processing the corresponding output pixel data D2.

As a result, as shown in FIG. 4, the output time T of the output data D2 is doubled, but since the pixel data []2 is of the same type as the next pixel data D3 that is not subjected to repeated processing,
By combining the 2-bit data, the output time is suppressed to 1.5 times the normal pixel data read cycle, and image distortion does not become noticeable.

On the other hand, when the output data D2 and the next data D3 are a combination of black dots and white dots (10 or 01), the determination circuit 22 sends a determination output of "1" to the clock switching circuit 23, which causes the clock The switching circuit 23 switches the clock, and a second read clock is sent to the read control circuit 33. Based on the clock, the corresponding output pixel data [12 and the next pixel data D3 before output are read out'.

As a result, the output time T of both pixel data can be suppressed to 1.5 times the read cycle of normal pixel data without repetitive processing, as shown in FIG.

After reading the 2-bit data, the clock is switched to the first read clock based on the signal from the repetition designation circuit 30, and the same operation is repeated thereafter.

FIG. 2 shows an enlarged image when the image data for one main scan stored in the shift register 21 is temporarily stored in the temporary storage means 4, and then the image data stored in the -time storage means 4 is read out. An image processing apparatus that performs processing will be shown, and differences from the previous embodiment will be mainly explained.

The temporary storage means 4 consists of two sets of line buffers 41.42 that perform toggle operations and a pair of selectors 43.44.
The configuration is such that writing and reading to and from the line buffers 41 and 42 are performed in parallel based on switching signals from the write and read control circuits 6 and 7.

The image data read from the line buffers 41 and 42 can be output as a video via the clock control circuit 5.

The clock control circuit 5 includes a 4-bit register 50 that sequentially shifts image data and outputs video based on a shift clock from a clock switching circuit 51, and a 4-bit register 50 that outputs a video while sequentially shifting image data based on a shift clock from a clock switching circuit 51. A determination circuit 52 which reads out the data and sends out a determination output of "0" or "1" in accordance with the table shown in FIG. a clock switching circuit 5 that switches the read clock based on the judgment output sent from the judgment circuit 52;
Consists of 1.

Note that the clock oscillator 24 sends a first clock synchronized with the image input clock to the shift register 21 and the write control circuit 8, respectively, and controls writing to the line buffers 41 and 42 based on the clock. The first clock (E) and the second clock (2) inverted by the inverter 25 are sent to the clock switching circuit 51, respectively.

Similar to the previous embodiment, the repetition designation circuit 50 is configured to be able to send out a repetition designation signal having a desired magnification rate based on the signal from MPtJ.

Next, the present invention will be explained in detail.

First, the 4-bit register 50 receives a shift clock I which is synchronized with the write clock via selectors 43 and 44.
The pixel data D1 after output, the output pixel data D2, the next pixel data 03 . The 4-bit data rows 1 to D4 are loaded in parallel to the judgment circuit 52 for each shift, and the judgment circuit 52 outputs a judgment of "011" as shown in FIG. When the clock is sent to the clock switching circuit 51, there is no clock switching within the clock switching circuit 51, and the first clock is sent to the 4-bit register 50 and the readout control circuit 7 as it is.
When a repetition designation signal is sent out at each bit interval corresponding to the target enlargement ratio, the output pixel data D2 can be repeatedly processed based on the designation signal.

As a result, as shown in FIG. 4, the output time T of the output data D2 from the 4-bit register 50 is doubled and output to the print engine side, which is the same as in the previous embodiment.

On the other hand, when the judgment output of "t" is sent from the judgment circuit 52 to the clock switching circuit 51, the clock switching circuit 51
Then, the clock is switched to the second clock H, and the clock is sent to the readout control circuit 7 and the 4-bit register 50, respectively, so that the corresponding output pixel data D2 is generated based on the clock H as in the previous embodiment. Then, the next pixel data D3 before output is read out. As a result, the output time T of both pixel data can be suppressed to 1.5 times the read cycle of normal pixel data without repetitive processing, as shown in FIG.

After reading the 2-bit data, the clock is switched to the first clock based on the signal from the repetition designation circuit 50, and the same operation is repeated thereafter.

Therefore, in any of the embodiments described above, regardless of whether the judgment output from the judgment circuit 52 is "O" 1, when the output pixel data D2 and the next pixel data D3 before output are substantially combined, The output time can be substantially suppressed to 1.5 times the normal pixel data readout cycle, image distortion does not become noticeable, and according to the embodiment in Part 2, the pixel data to be determined is increased by 4 bits. - Image control with high layer accuracy is possible.

"Effects of the Invention" As described above, according to the present invention, it is possible to accurately enlarge or obtain an enlarged image corresponding to any enlargement size without complicating the device configuration, and only when a part of the pixel clock is used. It has various advantages such as 0, which can obtain an enlarged or enlarged image with high reproducibility that is extremely close to the original without becoming redundant.

[Brief explanation of drawings]

1 and 2 are overall block diagrams showing an image processing device according to each embodiment of the present invention, FIG. 5 is a block diagram showing a repetition designation circuit used in the device, and FIG. 4 is a block diagram showing a repetition designation circuit used in the device. A time chart diagram showing the readout clock output from the clock switching circuit and the output time of the corresponding pixel data;
FIG. 3 is a front view showing the arrangement of pixel data stored in a 4-bit register in the device.

Claims (1)

[Claims] 1) In an image processing method in which image data in a predetermined scanning line direction is enlarged while being serially read out using a first readout clock (output time T1), one image data located at a corresponding pixel interval is pixel data and one or more pixel data adjacent to the pixel data are output using a second readout clock different from that of other pixel data, and the output time T of the pixel data approximately matches the following formula. An image processing method characterized in that T=T1×[(1+n)/n] (n: total number of pixels of the one pixel data and one or more pixel data adjacent to the pixel data) ) 2) Prepare an inverted clock having the same period as the normal read clock and a different phase as the second read clock, and output the output pixel data and the next pixel data at each corresponding pixel interval using the clock. The image processing method according to claim 1), wherein: 3) an image processing apparatus that performs image enlargement processing of pixel data based on a specified signal output at every arbitrary pixel interval; a first enlargement processing means for repeatedly processing corresponding pixel data using a readout clock; and reading out one or more corresponding pixel data by switching to a second clock different from the readout clock based on the specified signal. 4) an image processing apparatus characterized in that the image processing apparatus comprises a second enlargement processing means that performs a temporary storage means for storing at least a plurality of pixel data before and after output while sequentially shifting the data based on the output; and a plurality of pixel data stored in the temporary storage means are loaded in parallel for each shift or for each output of the specified signal. and a determination circuit for determining whether or not the output pixel data and the next pixel data are the same pixel data, and a configuration capable of selectively switching between the two enlargement means based on the determination output from the determination circuit. The image processing device according to claim 3)