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JPH025448A - Ceramic package - Google Patents

Ceramic package

Info

Publication number
JPH025448A
JPH025448A JP63154675A JP15467588A JPH025448A JP H025448 A JPH025448 A JP H025448A JP 63154675 A JP63154675 A JP 63154675A JP 15467588 A JP15467588 A JP 15467588A JP H025448 A JPH025448 A JP H025448A
Authority
JP
Japan
Prior art keywords
resistor
capacitor
cavity
ceramic package
ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63154675A
Other languages
Japanese (ja)
Inventor
Koichiro Izumi
和泉 孝一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63154675A priority Critical patent/JPH025448A/en
Publication of JPH025448A publication Critical patent/JPH025448A/en
Pending legal-status Critical Current

Links

Classifications

    • H10W70/655
    • H10W90/754

Landscapes

  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Abstract

PURPOSE:To reduce in size a ceramic package by burying a resistor and a capacitor in a ceramic body. CONSTITUTION:In a ceramic package having a cavity 10 provided between a ceramic body 1 and a sealing cap 8, a semiconductor chip 2, a resistor 4 and a capacitor 5 contained therein, the chip 2 is placed in the cavity 10, and the resistor 4 and the capacitor 5 are buried in a low temperature sintered ceramic body 1 with a thick film material. Thus, the cavity 10 is reduced to decrease in size the package.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は半導体パッケージに関する。[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor packages.

特に、低温焼結型のセラミックパッケージに関するもの
である。
In particular, it relates to a low temperature sintered ceramic package.

[従来の技#i] 従来、この種のセラミックパッケージは、半導体チップ
、抵抗体、コンデンサ等を搭載するキャビティ部がパッ
ケージ内に設けてあった。
[Conventional Technique #i] Conventionally, this type of ceramic package has a cavity portion in which a semiconductor chip, a resistor, a capacitor, etc. are mounted.

第2図に従来のセラミックパッケージの一例を示す。FIG. 2 shows an example of a conventional ceramic package.

同図において、1はセラミック(アルミナ)本体である
In the figure, 1 is a ceramic (alumina) main body.

2は半導体チップであり、セラミック本体l上に搭載さ
れている。
2 is a semiconductor chip, which is mounted on the ceramic body l.

3a、3bは、セラミック本体lに配線された導体パタ
ーンである。
3a and 3b are conductor patterns wired on the ceramic body l.

4は厚膜抵抗体(あるいはチップ抵抗体)であり、導体
パターン3a上に設けられている。
Reference numeral 4 denotes a thick film resistor (or chip resistor), which is provided on the conductor pattern 3a.

5はコンデンサであり、導体パターン3b上に設けられ
ている。
5 is a capacitor, which is provided on the conductor pattern 3b.

6a、6bは、半導体チップ2と導体パターン3a、3
bとの接続用ポンディングワイヤである。
6a and 6b are the semiconductor chip 2 and the conductor patterns 3a and 3
This is a bonding wire for connection with b.

7a、7bは外部信号取り出し用の入出力ピン、8は封
止用キャップ、9a、9bはキャップ8の封止部である
7a and 7b are input/output pins for taking out external signals, 8 is a sealing cap, and 9a and 9b are sealing portions of the cap 8.

10はキャビティ部であり、セラミック本体lと封止用
キャップ8との間に形成されている。
Reference numeral 10 denotes a cavity portion, which is formed between the ceramic body 1 and the sealing cap 8.

以上のような従来のセラミックパッケージにおいては、
半導体チップ2.抵抗体4.およびコンデンサ5は、キ
ャビティ部10に設けられていた。
In the conventional ceramic package as described above,
Semiconductor chip 2. Resistor 4. And the capacitor 5 was provided in the cavity part 10.

[解決すべき課Jllf!] 上述した従来のセラミックパッケージでは、半導体チッ
プ2とともに、抵抗体4およびコンデンサ5をキャビテ
ィ部10に設けていたので、キャビティ部10が大きく
なり、したがってパッケージが大型化するという問題点
を有していた。
[Division to be solved Jllf! ] In the above-mentioned conventional ceramic package, since the resistor 4 and capacitor 5 are provided in the cavity 10 along with the semiconductor chip 2, there is a problem that the cavity 10 becomes large and the package becomes large. Ta.

本発明は上述した問題点にかんがみてなされたもので、
小型化を図ることのできるセラミックパッケージの提供
を目的とする。
The present invention has been made in view of the above-mentioned problems.
The purpose is to provide a ceramic package that can be made smaller.

[課題の解決手段] 上記目的を達成するために本発明は、セラミック本体と
封止用キャップとの間にキャビティ部を備え、半導体チ
ップ、抵抗体、およびコンデンサを内蔵したセラミック
パッケージにおいて、前記半導体チップを前記キャビテ
ィ部に搭載し、前記抵抗体およびコンデンサを前記セラ
ミック本体内に埋設した構成としである。
[Means for Solving the Problems] In order to achieve the above object, the present invention provides a ceramic package including a cavity portion between a ceramic body and a sealing cap, and incorporating a semiconductor chip, a resistor, and a capacitor. The chip is mounted in the cavity, and the resistor and capacitor are embedded in the ceramic body.

[実施例] 以下、本発明の一実施例について図面を参照して説明す
る。
[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

第1図は本発明に係るセラミックパッケージの一実施例
を示す縦断面図である。同図において、第2図に示した
従来のセラミックパッケージと同一または相当する部分
には同一の符号を付しである。
FIG. 1 is a longitudinal sectional view showing an embodiment of a ceramic package according to the present invention. In this figure, parts that are the same as or correspond to those of the conventional ceramic package shown in FIG. 2 are given the same reference numerals.

本実施例の特徴とする点は1図示のように、半導体チッ
プ2をキャビティ部10に搭載し、抵抗体4およびコン
デンサ5を、厚膜材料を用いて低温焼結セラミック本体
1内に埋設した点にある。
The feature of this embodiment is that, as shown in FIG. 1, a semiconductor chip 2 is mounted in a cavity 10, and a resistor 4 and a capacitor 5 are embedded in a low-temperature sintered ceramic body 1 using a thick film material. At the point.

このように構成することにより、本実施例では、キャビ
ティ部lOが小さくなっており、したがってパッケージ
が小型になっている。
With this configuration, in this embodiment, the cavity portion IO is small, and therefore the package is small.

なお、キャビティ部10が小さくなっているのに合せて
、セラミック本体lに配線された導体パターン3a、3
bも小さくなっている。
In addition, as the cavity portion 10 has become smaller, the conductor patterns 3a, 3 wired on the ceramic body l have become smaller.
b is also smaller.

[発明の効果] 以上説明したように本発明は、セラミック本体内に抵抗
体およびコンデンサを埋設することにより、セラミック
パッケージを小型化することができるとい効果がある。
[Effects of the Invention] As explained above, the present invention has the advantage that a ceramic package can be miniaturized by embedding a resistor and a capacitor within a ceramic body.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係るセラミックパッケージの一実施例
の縦断面図、第2図は従来のセラミックパッケージの縦
断面図である。 1:セラミック本体 3a、3b 6a、6b 7a、7b 9a、9b 二手導体チップ :導体パターン :抵抗体 :コンデンサ :ポンディングワイヤ :入出力ビン :封止用キャップ :封止部 :キャビティ部 代理人 弁理士 渡 辺 喜 平
FIG. 1 is a longitudinal sectional view of an embodiment of a ceramic package according to the present invention, and FIG. 2 is a longitudinal sectional view of a conventional ceramic package. 1: Ceramic body 3a, 3b 6a, 6b 7a, 7b 9a, 9b Two-handed conductor chip: Conductor pattern: Resistor: Capacitor: Bonding wire: Input/output bin: Sealing cap: Sealing part: Cavity department agent Patent attorney Kihei Watanabe

Claims (1)

【特許請求の範囲】[Claims] セラミック本体と封止用キャップとの間にキャビティ部
を備え、半導体チップ、抵抗体、およびコンデンサを内
蔵したセラミックパッケージにおいて、前記半導体チッ
プを前記キャビティ部に搭載し、前記抵抗体およびコン
デンサを前記セラミック本体内に埋設したことを特徴と
するセラミックパッケージ。
In a ceramic package that includes a cavity between a ceramic body and a sealing cap and has a built-in semiconductor chip, a resistor, and a capacitor, the semiconductor chip is mounted in the cavity, and the resistor and capacitor are mounted in the ceramic package. A ceramic package characterized by being embedded within the main body.
JP63154675A 1988-06-24 1988-06-24 Ceramic package Pending JPH025448A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63154675A JPH025448A (en) 1988-06-24 1988-06-24 Ceramic package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63154675A JPH025448A (en) 1988-06-24 1988-06-24 Ceramic package

Publications (1)

Publication Number Publication Date
JPH025448A true JPH025448A (en) 1990-01-10

Family

ID=15589449

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63154675A Pending JPH025448A (en) 1988-06-24 1988-06-24 Ceramic package

Country Status (1)

Country Link
JP (1) JPH025448A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03288463A (en) * 1990-04-05 1991-12-18 Mitsubishi Materials Corp Multilayer board with interposed resistor
JPH04123552U (en) * 1992-02-27 1992-11-09 アンリツ株式会社 Hybrid IC for ultra-high frequency
JPH0629503A (en) * 1992-07-08 1994-02-04 Sony Corp Solid-state imaging device
US7838976B2 (en) 2006-07-28 2010-11-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a semiconductor chip enclosed by a body structure and a base
US8054035B2 (en) 2006-07-28 2011-11-08 Semiconductor Energy Laboratory Co., Ltd. Power storage device including an antenna
US8232621B2 (en) 2006-07-28 2012-07-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2023006531A (en) * 2021-06-30 2023-01-18 住友電気工業株式会社 Semiconductor device and package

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61285739A (en) * 1985-06-12 1986-12-16 Sumitomo Electric Ind Ltd High-density mounting type ceramic ic package

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61285739A (en) * 1985-06-12 1986-12-16 Sumitomo Electric Ind Ltd High-density mounting type ceramic ic package

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03288463A (en) * 1990-04-05 1991-12-18 Mitsubishi Materials Corp Multilayer board with interposed resistor
JPH04123552U (en) * 1992-02-27 1992-11-09 アンリツ株式会社 Hybrid IC for ultra-high frequency
JPH0629503A (en) * 1992-07-08 1994-02-04 Sony Corp Solid-state imaging device
US7838976B2 (en) 2006-07-28 2010-11-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a semiconductor chip enclosed by a body structure and a base
US8054035B2 (en) 2006-07-28 2011-11-08 Semiconductor Energy Laboratory Co., Ltd. Power storage device including an antenna
US8232621B2 (en) 2006-07-28 2012-07-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US8378473B2 (en) 2006-07-28 2013-02-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having semiconductor chip within multilayer substrate
US8692249B2 (en) 2006-07-28 2014-04-08 Semiconductor Energy Laboratory Co., Ltd. Power storage device
US9070563B2 (en) 2006-07-28 2015-06-30 Semiconductor Energy Laboratory Co., Ltd. Power storage device
JP2023006531A (en) * 2021-06-30 2023-01-18 住友電気工業株式会社 Semiconductor device and package

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