JPH01303699A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To improve efficiency remedying a random defect bit by recognizing a defect cell at the intersection of a matrix. CONSTITUTION:Plural address inputs are inputted to row and column decoders, an output is inputted to an comparing circuit and is compare-collated with the output of a ROM programmed in advance, besides, a row decoder output drives a word line 1 not through the comparing circuit but through an amplifier, and the word line 1 is driven for the delaying portion of a compare-judging circuit. Consequently, any of a good cell A, a defect cell and a spare cell A outputs an output signal to respective bit lines 5-5'', and when the output from the respective comparing circuits of a matrix is coincident, the defect cell is selected. Then, by the output of an AND circuit 3, a column decoder output is cutoff by an NOR circuit 4, the switch of Q2 is not on, the switch of Q3 is on, a data line 2 is connected with the bit line 5'' of the spare cell A, and the defect cell is substituted by the spare cell A. Thus, the remedying efficiency of the random defect cell can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a method for efficiently repairing randomly occurring defective bits.

[Conventional technology]

Conventionally, this type of defective bit relief has generally been carried out by replacing the row or column containing the defective bit with a spare row or column for redundancy.

[Problem to be solved by the invention]

However, with this method, it is effective to repair defective bits caused by so-called dust, scratches, etc., where the number of defective bits occurs along rows or columns. The drawback is that the backup matrix required for this process is wasteful and the relief efficiency is reduced.

It also has the disadvantage that memory access time is slow due to redundant bit determination circuits for rows and columns.

[Means to solve the problem]

The redundant bit relief means of the present invention includes a spare row for redundancy;
A circuit that stores the position of a defective bit, a circuit that compares the input address of the defective bit address and outputs the result, and switches the output from the defective bit and the output from the spare bit controlled by the output of the result. It is equipped with a switch circuit.

〔Example〕

Next, the operation of the present invention will be explained with reference to the drawings.

An example configuration is shown in FIG. Its main components are each matrix decoder circuit, a redundant cell column, a cell array, a pair of comparison circuits, and a ROM section for storing defective cells.

A plurality of address inputs are input to a row and column decoder, the outputs of which are input to a comparator circuit and compared against the output of a previously programmed ROM. This ROM is previously programmed in a conventional fuse type. Furthermore, since the row decoder output drives the word line 1 through the amplifier without passing through the comparison circuit, the word line is driven faster than in the prior art by the delay of the comparison/judgment circuit. Therefore, both the defective cell A1 and the spare cell output their output signals to their respective bit lines. and,
If the outputs from each comparator circuit in the matrix match, it means that a defective cell has been selected, so the column decoder output is cut off by the AND output of 3 and the 4 OR circuits.
Switch 2 is not ONL. On the other hand, the output of the AND circuit 3 turns on the switch Q3, and the data line 2 is connected to the bit line of the spare cell. In other words, the defective cell has been replaced with a spare cell. Next, if at least one of the comparison circuits in the second row and second column does not match, the AND circuit of 3 does not output, the Ql switch is turned on, and the bit line of good cell A is connected to the data line of 2, and normal writing is performed. Alternatively, a read operation is performed. Next, when good cell B is selected, the comparison circuit on the row side does not output, so as mentioned above, the switch Q2 is ONL.The bit line of good cell B is connected to the data line 2, and the spare cell B Since the bit line Q is cut off by the switch Q, it can be operated normally.

〔Effect of the invention〕

As explained above, the present invention can efficiently eliminate random defective bits by recognizing defective cells at the intersections of matrices and columns. For example, when repairing a random 8-bit defect,
While the prior art requires eight spare rows or columns, the present invention allows for one spare row;
Moreover, the number of rescue bits is several tens in the 1M bit class.
It is possible to spread 0 bits or more without increasing the spare matrix.

At this time, the ROM section naturally increases, but by inserting a ROM into the matrix decoder output, the area can be increased by the number of spare columns.

When the present invention is applied to a high-density dynamic RAM, it is effective in relieving problems such as poor retention of memory cells due to substrate defects, and can contribute to a significant improvement in yield. In particular, even if the retention time is lengthened, there is little decrease in yield, so the power consumption of the dynamic RAM, which is determined by the refresh cycle, can be significantly reduced. This brings about the possibility of forming a new field as a low-consumption memory that takes advantage of the low cost of dynamic RAM.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a circuit according to the present invention. In Figure 1, 1 and 1' are word lines, 2 is a data line,
3 is an AND circuit, 4 and 4' are NOR circuits, Q1 to Q3
is an MO8 type FET, 5.5' and 5'' are bit lines, and 6 and 6' are inverter type amplifiers. Agent: Susumu Uchihara, patent attorney

Claims (1)

[Claims] In a semiconductor memory device having redundant bits, circuit means for specifying only defective bits at the intersections of rows and columns and replacing them in one-to-one correspondence with redundant bits prepared in spare rows or columns. A semiconductor memory device characterized by comprising: