JPH0121704B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inverter device, particularly an inverter device using field effect transistors.

Conventionally, there has been an inverter device of this type as shown in FIG. In FIG. 1, a first field effect transistor (hereinafter referred to as
A second MOSFET is connected to the source 12b of this MOSFET.
A closed circuit is formed by sequentially connecting the drain 14a of the MOSFET 14 and the source 14b of the MOSFET to the negative terminal of the power supply 10, and connecting the gate drive circuit 1 to the gates 12c and 14c of the first and second MOSFETs.
6 and 18 are connected.

When a MOSFET is used as a switching element as described above, its equivalent circuit becomes a circuit as shown in FIG. In Figure 2, drain 1
There is a capacitance 20 between the gate 2a and the gate 12c, a capacitance 22 between the gate 12c and the source 12b, and a capacitance 24 between the drain 12a and the source 12b. ON resistance 26 when MOSFET 12 turns on
is in series with a switch 28 controlled by the voltage between source 12b and gate 12c. Further, a reverse diode 30 is provided between the drain 12a and the source 12b. In addition, MOSFET1
4 has exactly the same structure, and the reference numeral 12 in FIG. 2 may be replaced with the reference numeral 14.

The operation of the circuit shown in FIG. 1 will be explained below. Now, when the first MOSFET 12 receives the output of the gate drive circuit 16 and turns on, the output terminal 100
The potential of becomes the potential V ₊ of the power supply 10, but then
When the MOSFET 12 is turned off and the second MOSFET 14 receives the output of the gate drive circuit 18 and turned on, the potential of the output terminal 100 drops from V ₊ to V _- . That is, the drain 14 of MOSFET 14
The voltage between MOSFET 12a and source 14b goes from V ₊ to 0 volts, and the voltage between drain 12a and source 12b of MOSFET 12 suddenly changes to V ₊ .

FIG. 3 is a time chart showing the operation of the circuit in FIG. 1, where a shows the switching state of MOSFET 12, b shows the switching state of MOSFET 14,
c is the potential of the output terminal 100, d is the MOSFET 12
e is the drain current of the MOSFET 14, f is the voltage between the source 12b and the gate 12c of the MOSFET 12, and g is the voltage between the source 14b and the gate 14c of the MOSFET 14.

As is clear from Figure 3e above, MOSFET1
When 4 is turned on, the capacitance 2 shown in Figure 2 above is
The current passing through MOSFET 14 flows through MOSFET 14 and an overcurrent 34 occurs. Similarly, MOSFET12 is ON
Even when this occurs, an overcurrent 32 flows, as is clear from d in the same figure. These overcurrents 32 and 34 cause voltage drops 36 and 38 in the capacitance 22 as shown in f and g in the figure.
occurs, and when this voltage drop reaches the threshold voltages 40 and 42 of MOSFETs 12 and 14, the second
Switch 28 shown in the figure turns on and MOSFET1
Create a period where 2 and 14 are turned on at the same time, and do this.
The MOSFET will short-circuit the power supply 10.

Conventional inverter devices using MOSFETs are configured as described above, so excessive current flows during switching, and the switch is turned off.
The MOSFET turns on due to the influence of the overcurrent of the turned on MOSFET, shorting the power supply. For this reason,
This would destroy the MOSFET and power supply, making it difficult to construct an inverter using MOSFETs for high voltage and high speed switching.

The present invention was made in view of the above-mentioned conventional problems, and its purpose is to provide a MOSFET with a reactor inserted into the drain or source.
The object of the present invention is to provide an inverter device that can limit MOSFET overcurrent and perform stable switching.

In order to achieve the above object, the present invention provides two field effect transistors arranged between DC power supplies and connected in series such that the source of one is connected to the drain of the other, and the two field effect transistors. means for supplying an on/off signal to the gates of the two field effect transistors to alternately turn on these two field effect transistors; means for outputting an alternating current signal from the midpoint between the two field effect transistors; A current limiting circuit and an overvoltage absorbing circuit are added to the source circuit in parallel, and the overcurrent generated when one field effect transistor is turned on is suppressed, and the other field effect transistor is protected from destruction. It is characterized by Another feature is that a ferrite core is used as the current limiting element forming the current limiting circuit, and the drain or source circuit of the field effect transistor is passed through the ferrite core.
Furthermore, the present invention is characterized in that two or more field effect transistors are connected in parallel and a current balance resistor is provided in the drain or source circuit of the field effect transistor.

Hereinafter, preferred embodiments of the present invention will be described based on the drawings. FIG. 4 is a circuit diagram showing the first embodiment of the present invention, in which the same parts as in FIG. 1 are given the same reference numerals.
4a are provided with reactors 44 and 46 in series, and overvoltage absorption circuits 48 and 50 are provided in parallel with each reactor.
This is a configuration in which the following are connected. The above-mentioned overvoltage absorption circuit 4
Reference numerals 8 and 50 each include a diode 52 and a resistor 54 connected in series, and 56 and 58 connected in series.

FIG. 5 is a time chart showing the operation of the circuit shown in FIG. 4, where a to e indicate the same as a to e in FIG.
Indicates the voltage of

In the circuit configuration shown in Figure 4 above, MOSFET12,1
The drain current of 4 is limited by the reactors 44 and 46, and the overcurrents 60 and 62 have small values as shown in FIGS. 5d and 5e. In this case, output terminal 1
Current limiting can be performed even if the load connected to 00 is capacitive. Therefore, MOSFET12,1
4 is turned off, the overvoltage absorption circuits 48 and 50 attenuate the voltage generated in the reactors 44 and 46 as shown in FIG.
This prevents overvoltage from occurring due to the current flowing through the terminal. Note that the diodes 52 and 56 of the overvoltage absorption circuits 48 and 50 are for high-speed switching, and the resistor 5
4 and 58 are good non-inductive resistors.

FIG. 6 shows a second embodiment of the present invention, in which ferrite cores 64, 66 are used in place of the reactors 44, 46 in FIG. 4. This ferrite core has a magnetic permeability of about 1000 to 3000, and can operate as a 1 to 2 μH reactor just by passing an electric wire through it. Additionally, the ferrite core has the effect of attenuating high frequencies, preventing parasitic oscillations caused by MOSFETs at high frequencies, and ensuring stable switching operation.

FIG. 7 shows a third embodiment of the present invention, in which MOSFET 6 having the same circuit configuration is placed in parallel with the series body of MOSFETs 12 and 14 of the first embodiment shown in FIG.
This is a single-phase inverter with 8 and 70 units connected in series. Drain 68 of the above MOSFET 68, 70
Reactors 72, 74 and gate 6 are installed in a and 70a.
8c, 70c have gate drive circuits 76, 78
is connected. In addition, the reactor is connected in parallel with a series body of a diode 80 and a resistor 82;
An overvoltage absorption circuit 88 consisting of 86 series bodies,
90 are connected.

In this embodiment, the inverter output voltage of the load 92 can be doubled as compared to the first embodiment. In addition, if the load 92 is an inductive load, a reverse voltage may be applied to the MOSFET, but the MOSFET itself has a reverse diode 30 (Fig. 2) and a reactor 44.
(46, 72, 74) and overvoltage absorption circuit 48
(50, 88, 90), MOSFET1
2 (14, 68, 70) will not be destroyed.
In an inverter made up of transistors, etc., a diode is connected in parallel with the transistor in the opposite direction to prevent the above-mentioned reverse voltage, but when MOSFETs are used, the above-mentioned diode can be omitted.

FIG. 8 shows a fourth embodiment of the present invention, in which MOSFETs 12, 14, 68, and 70 of the third embodiment are replaced with a transistor 110, a diode 112,
4 and 116, 118 and 120, and 122 and 124 in parallel.

FIG. 9 shows a fifth embodiment of the present invention, in which each MOSFET circuit of the third embodiment has the same configuration.
MOSFET circuit (the part with a dash after the symbol)
This is a configuration in which the two are connected in parallel. MOSFETs have variations in ON resistance 26 shown in the equivalent circuit in Figure 2, and when they are connected in parallel, each
Current does not flow evenly through the MOSFETs, and the current concentrates on MOSFETs with low resistance. Therefore,
The MOSFET where this current concentrates becomes easily destroyed.

However, in this embodiment, the balance resistors 126-132, 126'-132' are connected in series with the reactor of the drain circuit. And this balance resistance 126~132,126'
By connecting ~132' in series with the MOSFET, the resistance when the MOSFET is ON becomes the sum of the balance resistance, and the resistance when connected in parallel
It is possible to suppress current concentration due to variations in the ON resistance of each MOSFET, and prevent destruction of the MOSFET. This current balance resistor is preferably selected to have a value similar to the ON resistance of the MOSFET, generally 0.1 to 1Ω.

Fig. 10 shows ferrite cores 134-140, 134'-14 instead of the reactor shown in Fig. 9 above.
FIG. 10 is a circuit configuration diagram showing a sixth embodiment of the present invention using 0'.

Although a single-phase inverter is shown above, a multi-phase inverter can also be easily constructed by arranging the circuits of the first embodiment in three rows and using a plurality of three-phase inverters.

FIG. 11 shows the power supply 10 in each embodiment of the present invention.
This shows a configuration example in which the phases of three-phase AC R, S, and T are controlled by thyristors 142 to 152, and a constant DC voltage is obtained by a reactor 154 and a capacitor 156.

FIG. 12 shows an inverter device 158 of the present invention using a MOSFET and a silent discharge excitation laser oscillator 16.
This is an example of use as a power supply for silent discharge of 0. The output of the inverter device 158 is transferred to the step-up transformer 1
62 supplies a high voltage to electrodes 164 and 166 whose surfaces are covered with a dielectric material. A laser medium gas 1 is contained in the silent discharge excited laser oscillator 160.
68 is filled and a silent discharge 170 is generated, laser oscillation occurs between the total reflection mirror 172 and the partial transmission mirror 174 placed opposite each other, and is output as a laser beam 176. The output frequency of the inverter device 158 used as the silent discharge power source is
Since it uses 50KHz to 200KHz, it was impossible to achieve with other transistors or thyristors.
This was made possible by using MOSFETs.

As described above, the present invention adds a reactor and an overvoltage absorbing circuit in parallel to each drain or source circuit of two field effect transistors connected in series, so that overcurrent can be prevented from flowing into the MOSFET. As a result, the MOSFET that should be turned off will not turn on and short-circuit the power supply.
This has the effect that it is possible to avoid destruction of MOSFETs, etc., and to obtain an inverter device that can perform stable switching without parasitic oscillation at high frequencies.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a conventional inverter device, Figure 2 is a circuit diagram of a conventional inverter device.
The figure is an equivalent circuit diagram of the MOSFET, Figure 3 is a time chart explaining the circuit operation of Figure 1, Figure 4 is a circuit diagram showing the first embodiment of the present invention, and Figure 5 is the
A time chart explaining the circuit operation shown in Fig. 6.
The figure is a circuit diagram showing a second embodiment of the invention, FIG. 7 is a circuit diagram showing a third embodiment of the invention, FIG. 8 is a circuit diagram showing a fourth embodiment of the invention, and FIG. 9 is a circuit diagram showing a fourth embodiment of the invention. 10 is a circuit diagram showing a sixth embodiment of the present invention, FIG. 11 is a circuit diagram of a power supply applied to each of the above embodiments of the present invention, and FIG. The figure is a circuit wiring diagram used as a power source of a silent discharge pumped laser oscillator to which the inverter device of the present invention is applied. Identical parts in each figure are given the same symbols, 10 is a power supply, 12, 14, 68, 70 are MOSFETs, 1
6, 18, 76, 78 are gate drive circuits, 4
4, 46, 72, 74 are reactors, 48, 5
0, 88, 90 are overvoltage absorption circuits, 64, 66,
134 to 140 are ferrite cores.

Claims (1)

[Claims] 1. Two field effect transistors arranged between DC power supplies and connected in series such that the source of one is connected to the drain of the other, and an on/off signal applied to the gates of the two field effect transistors. means for supplying AC signal to alternately turn on these two field effect transistors; means for outputting an alternating current signal from a midpoint between the two field effect transistors; An inverter comprising: a parallel current limiting circuit and an overvoltage absorbing circuit; Device. 2. An inverter device according to claim 1, characterized in that the current limiting circuit is a current limiting element. 3. An inverter device according to claim 2, characterized in that a reactor is used as the current limiting element. 4. The inverter device according to claim 2, wherein a ferrite core is used as the current limiting element, and a drain or source circuit of a field effect transistor is passed through the ferrite core. 5. In the device according to any one of claims 2, 3, and 4, two or more field effect transistors are connected in parallel and a current balancing resistor is provided in the drain or source circuit of the field effect transistor. An inverter device featuring: