JPH01208005A - Frequency modulation circuit - Google Patents

Abstract

PURPOSE:To obtain a stable operation even in composite modulation and non- modulation by varying the loop gains and time constants of two PLL means connected in series corresponding to the ON/OFF of the input of a modulation signal. CONSTITUTION:A reference signal generating means 10 oscillates a frequency signal which becomes reference, and outputs it to a first PLL means 20. In the case of turning ON the input of the modulation signal 2 for a frequency modulation circuit 100, the loop gain of the means 20 is decreased by a control means 40, and the time constant of a loop filter is increased. Simultaneously, the means 40 increases the loop gain of a second PLL means 30, and decreases the time constant of the loop filter, thereby, runout from a synchronism holding range due to the signal 2 can be prevented from being generated. On the other hand, in the case of turning OFF the input of the signal 2, by performing reverse control as in the case of turning ON the input of the signal 2, stable oscillation output signals can be taken out from the means 20 and 30. In such a way, it is possible to prevent the runout from the synchronism holding range from being generated even in the composite modulation and also, to obtain an output signal with a high C/N in the non-modulation.

Description

[Detailed Description of the Invention] [Summary] Regarding a frequency modulation circuit in a local oscillator for complex modulation, it is possible to secure a wide frequency pull-in range and perform more stable frequency modulation, and also to achieve highly stable oscillation when no modulation is performed. A reference signal generating means for oscillating a reference frequency signal for the purpose of providing a frequency modulation circuit capable of obtaining an output;
a first phase-locked loop means that controls a free-running oscillation frequency signal using the output of the reference signal generation means as a reference input signal, and whose internal loop gain and time constant are varied; and an output of the first phase-locked loop means. In addition to controlling the free-running oscillation frequency signal using the signal as a reference input signal,
A second phase-locked loop means whose internal loop gain and time constant are variable, and a manual activation of a modulation signal that inputs the gain and loop filter time constant of the first/second phase-locked loop means from the outside. /off control means.

[Industrial application field]

The present invention relates to a frequency modulation circuit in a local oscillator for complex modulation.

For example, in wireless communication systems, in addition to the main signal consisting of a PCM signal, analog signals for meetings etc. are transmitted, and analog signals other than these main signals are frequency modulated (hereinafter referred to as local oscillator) using a local oscillator. (referred to as FM modulation), a method is used in which a main signal modulated by a predetermined method is subjected to complex modulation and then transmitted.

In order to perform the above-mentioned composite modulation, the local oscillator that creates and sends out the FM modulation signal must have a stable output and a high C(
It is required to send out an output signal of carrier)/N (noise).

[Conventional technology]

Figure 3 is a block diagram explaining a conventional example, Figure 4 is a block diagram explaining another conventional example, Figure 5 is a diagram explaining an example of the use of a local oscillator, and Figure 6 explains the operation of a PLL circuit. Figures are shown for each.

Figure 5 shows the configuration of part of a transmitter in a wireless communication system.The configuration is as follows: The main signal (PCM signal) ■ is subjected to four-phase phase modulation, and the FM modulation signal ■ is shallowly modulated and transmitted. A phase modulation unit (hereinafter referred to as PSK-MOD) 70 that performs FM modulation of the analog signal @, and a local oscillation unit (hereinafter referred to as L
The intermediate frequency amplifying section (hereinafter referred to as RF-AMP) 90 forms an intermediate frequency signal (2) from the output of the PSK-MOD 70, amplifies its power, and transmits it.

FIG. 3 and FIG. 4 show the configuration of a part of the above-mentioned LC)-0SC80. That is, FIG. 3 includes a reference signal oscillation circuit 1 that oscillates a predetermined frequency signal, and a PLL circuit 2 that outputs the output signal (2) of the reference signal oscillation circuit 1 in a stable state.

The reference signal oscillation circuit 1 uses a crystal resonator as the oscillation element 12, and modulates the output of the oscillation element 12 in FM by varying the bias of a variable capacitance diode (varactor diode) Cv using an external modulation signal. The oscillation circuit 14, which oscillates a predetermined signal, outputs an FM modulation signal (2).

The PLL circuit 2 inputs this FM modulation signal (2) as a reference signal, and sends out the FM modulated output signal (2) to the PSK-MOD 70 in a stable state.

On the other hand, FIG. 4 shows a reference signal oscillation circuit 1' that also uses a crystal resonator as the oscillation element 12, and a loop filter 4 and voltage control in a PLL circuit 2' connected to this reference signal oscillation circuit 1'. This is a method in which an external modulation signal (2) is input between an oscillator (hereinafter referred to as VCO) 5 to perform FM modulation.

The above PLL circuits 2 and 2' are used as one component of a frequency modulation circuit for outputting a stable FM modulation output signal (2), and are synchronized as shown in FIG. When in the state (locked state) BL, the VCO 5 in the PLL circuit 2.2' operates in accordance with the instantaneous frequency change of the FM modulation signal (2).

That is, the PLL circuit 2 (2') uses the reference signal ■ and the VCO 5.
A phase comparator 3 that compares the phase with the free-running oscillation frequency f0 of
and a loop filter 4 that removes high frequency components generated by the phase comparator 3 and converts the phase difference generated as a result of the phase comparison into a voltage value and sends it out; The frequency divider 6 divides the output frequency of the VCO 5 by a predetermined number of steps and sends the divided frequency to the phase comparator 3 for phase comparison.

In the above-mentioned PLL circuit 2 (2'), when the reference signal (2) is not input, the loop is in an open state. When the reference signal ■ is input from this state, the frequency and phase of the reference signal ■ do not match the output signal of ■C○5 because the synchronization state is not established at first.

Therefore, the synchronization in the PLL circuit 2 (2') is
First, as shown in FIG. 6, during the frequency pull-in process, the frequency falls within the frequency pull-in range B.

, and then completes the synchronization in the phase synchronization (lock-in) process.

In addition, when the PLL circuit 2 (2') is in a synchronized state and the frequency of the reference signal ■ is gradually moved away from the free-running oscillation frequency of the VCO 5 by 1° from the reference signal ■, the frequency at which synchronization is lost is shown in Figure 6. Assuming f,, f4, the range represented by BL = 14-f is defined as the synchronization holding range (also called lock range), and the PLL circuit 2 (2') is in an asynchronous state, and the frequency of the reference signal ■ gradually increases the free-running oscillation frequency f of VCO5
0, and the synchronized frequency is f2, respectively.
Assuming f3, the range expressed by Br=fz fz is defined as a frequency pull-in range (also referred to as a pull-in range).

In the FM modulation circuit shown in FIG. 3 using such a PLL circuit 2, the output from the reference signal oscillation circuit 1 including a varactor diode CV (non-linear element) is input as the reference signal ■, and the PI and L circuits 2 This is the method to take it out.

That is, in the reference signal oscillation circuit 1, the varactor diode Cv
The bias voltage applied to the reference signal oscillation circuit 1 (a crystal resonator is used as the oscillation element 12) is oscillated by changing the bias voltage applied to the reference signal oscillation circuit 1 (a crystal resonator is used as the oscillation element 12), for example, by changing the bias voltage applied to the external signal (modulation signal ■ is used in Fig. 3). In addition to the signal to be generated, the frequency of the signal oscillated from the reference signal oscillation circuit l generated by the mixing effect,
FM modulation is performed by converting the modulated signal (1) into an output signal (ie, a reference signal) of the sum or difference of frequencies in the oscillation circuit 14.

This reference signal ■ is sent to the PLL circuit 2 to stabilize the FM
Sends a modulated signal ■.

On the other hand, the method shown in FIG. In this method, FM modulation is performed by changing the output frequency of the PLL circuit 2' by changing the voltage) using an external modulation signal (2).

[Problem to be solved by the invention]

When performing FM modulation using the method shown in Figure 3 above, the capacitance of the varactor diode Cv changes due to changes in environmental conditions, especially changes in environmental temperature, so even when there is no modulation, the PLL
There is a possibility that the frequency of the reference signal (2) input to the circuit 2 may change.

On the other hand, in the case of the FM modulation method as shown in Fig. 4, the VC
Since the control voltage applied to the PLL circuit 2' is directly varied by the modulation signal (2), depending on the amplitude of the variation, there is a possibility that the control voltage applied to the PLL circuit 2' falls outside the period holding range BL of the PLL circuit 2'.

SUMMARY OF THE INVENTION An object of the present invention is to provide a frequency modulation circuit that can secure a wide frequency pull-in range, perform more stable frequency modulation, and provide a highly stable oscillation output when no modulation is performed.

[Means to solve the problem]

FIG. 1 shows a block diagram illustrating the invention in detail.

In the block diagram of the principle of the present invention shown in FIG. 1, 10 is a reference signal generating means for oscillating a reference frequency signal, and 20 is a free-running oscillation frequency signal which uses the output of the reference signal generating means 10 as a reference input signal. 30 is a first phase-locked loop means in which the internal loop gain and time constant are varied, and 30 generates a free-running oscillation frequency signal using the output signal of the first phase-locked loop means 2o as a reference input signal. 40 is a second phase-locked loop means 20.
It is a control means for varying the gain in 30 and the time constant of the loop filter according to the on/off of the input of the modulation signal (■) inputted from the outside, and by providing these, it is a means for solving this problem. .

[For production]

When the input of the modulation signal ■ is on, the control means 40 lowers the gain in the first phase-locked loop means 20, increases the time constant of the loop filter, and increases the gain in the second phase-locked loop means 30. By increasing the gain and decreasing the time constant of the loop filter, it becomes possible to prevent deviation from the synchronization holding range due to the modulation signal (2).

On the other hand, when the input of the modulation signal ■ is off (when no modulation is performed), the control means 40 performs the opposite control to the control when the input of the modulation signal ■ is on, thereby controlling the first/second phase-locked loop means. It becomes possible to extract a highly stable oscillation output signal ■ from 20.30.

〔Example〕

The gist of the present invention will be specifically explained below with reference to an embodiment shown in FIG.

FIG. 2 shows a block diagram illustrating the invention in detail. Note that the same reference numerals indicate the same objects throughout the figures.

The embodiment of the present invention shown in FIG. 2 uses an inverter 11. Crystal oscillator 12
．． Hasofa 13, varactor diode Cv, resistor R
1, R2, and a crystal oscillator section 1 consisting of capacitors CI and C2.
0a, the first phase-locked loop means 20 uses the output of the crystal oscillator 10a as a reference signal ■, and divides the frequency of this output by a frequency divider 211 and a phase comparator 22. Reference oscillator (base f!AO3C) with constant oscillation frequency 23. Phase comparator 2
An amplifier (AMP) that amplifies the output of 24. A PLL circuit 20a consisting of a loop filter 25, a second phase-locked loop means 30, and a phase comparator that uses the output of the crystal oscillator 10a as a reference signal (■) and compares the phase of this reference signal (■) with the free-running oscillation frequency. 31. Amplifier (AMP)
32. Loop filter 33°: PLL circuit 30a consisting of a VCO 34 that oscillates a free-running oscillation frequency and a frequency divider 35 that divides the output of the VCO 34; control: JI1 means 40 that controls the gain and loop of the amplifier (AMP) 24 in the PLL circuit 2Oa; A control circuit 41 that varies the time constant of the filter 25
and a control circuit 4 that varies the gain of the amplifier (AMP) 32 in the PLL circuit 30a and the time constant of the loop filter 33.
This is an example in which the controller 40a is composed of the controller 40a and the controller 40a.

The crystal oscillator 10a can vary its oscillation frequency by varying the bias voltage of the varactor diode Cv, and therefore the modulation signal ■ is transmitted through the resistor R1.
The bias voltage of the varactor diode C9 is varied through.

At the same time, the crystal oscillator 10a is used as a loop component of the PLL circuit 20a, and the output voltage from the loop filter 25 is similarly applied as a bias voltage to the varactor diode Cv via the resistor R1, and is varied to perform FM modulation. The output is sent out as a reference signal (2) to the next stage PLL circuit 30a.

The PLL circuit 30a takes out from the output side of the VCO 34 an output signal (2) having a free-running oscillation frequency that follows this reference signal (2).

At this time (that is, when the modulation signal ■ is being input) the control unit 4
The 0a internal control circuits 41 and 42 lower the gain of the PLL circuit 2Oa internal amplifier (AMI') 24 and control the time constant of the loop filter 25 to increase, and at the same time,
Increase the gain of the amplifier (8 MP) 32 in the PLL circuit 30a and reduce the time constant of the loop filter 33 to complete the PLL circuit.
Control is performed so that the circuit 20a and the PLL circuit 30a do not fall outside the synchronization holding range BL.

On the other hand, when the modulation signal ■ is not input (i.e., when there is no modulation)
The control circuits 41 and 42 in the control section 40a are PLL circuits 2O
The gain of the internal amplifier (AMP) 24 is increased, the time constant of the loop filter 25 is decreased, and at the same time the PLL circuit 30a is
By controlling the gain of the internal amplifier (AMP) 32 to be lowered and the time constant of the loop filter 33 to be increased, an output signal (2) with a high C/N (carrier-to-noise ratio) can be obtained from the PLL circuit 30a.

〔Effect of the invention〕

According to the present invention as described above, it is possible to provide a frequency modulation circuit that does not fall out of the synchronization holding range even during complex modulation and can obtain an output signal with a high carrier-to-noise ratio when no modulation is performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a block diagram explaining a conventional example, and FIG. 4 explains another conventional example. FIG. 5 is a diagram explaining an example of the use of a local oscillator, and FIG. 6 is a diagram explaining the operation of a PLL circuit. In the figure, 1.1' is a reference signal oscillation circuit, 2, 2', 20a, and 30a are PLL circuits, and 3.
22.31 is a phase comparator, 4.25.33 is a loop filter, 10 is a reference signal oscillation circuit, 1.0a is a crystal brother, 1
1 is an inverter, 12 is an oscillation element, 13 is a buffer, 20 is a first phase-locked loop means, and 23 is a base [
1ζ0SC124, 32 is an amplifier (AMP), 30 is a second feedback loop means, 40 is a control box,
40a is a control unit, 41.42 is a control circuit,
70 is PSK-MOD, 80 is LO-O3C19
0 is RF-AMP. are shown respectively. , -12,-611,-1,-7-m---1-1-1
,-171,-0,~,,,,,,,----,,--
--------(,-1,90-,,,,,,,-Block diagram for explaining the present invention in detail FIG. 1 (Kabeba!-Ichiri-,/-,,-1... −、、−、−、
-Block diagram explaining the conventional example, (!Jabun i table--'&)---(,-1, etc.,,-9
-9-8゜Block diagram explaining another conventional example

Claims (1)

[Claims] Frequency modulation circuit in a local oscillator for complex modulation using phase-locked loop means (20, 30)
100), a reference signal generating means (100) for oscillating a reference frequency signal;
0), and a first phase-locked loop means (20) which controls a free-running oscillation frequency signal using the output of the reference signal generating means (10) as a reference input signal, and whose internal loop gain and time constant are variable. and controlling the free-running oscillation frequency signal by using the output signal of the first phase-locked loop means (20) as a reference input signal ([1]), and controlling the second phase-locked loop means (20) whose internal loop gain and time constant are variable. phase-locked loop means (30); and the first/second phase-locked loop means (20,
Frequency modulation characterized by comprising: control means (40) for varying the gain in 30) and the time constant of the loop filter according to on/off of the input of the modulation signal ([2]) inputted from the outside. circuit.