JPH01169563A - Inter-processor synchronizing system - Google Patents

Abstract

PURPOSE:To provide a synchronizing mechanism between rapid processors by stepping up the contents of a memory at the time of connecting a counter to a data bus and accessing a specific address space area. CONSTITUTION:A processor 2a accesses an address k+a and a processor 2b accesses an address k+b. In this case, (k) indicates the leading address of an address space area assigned to a counter 4. A bus controller BCU 1 receives a bus request to the address k+a of the processor 2a, decodes the upper bit of address bus 5 and asserts the CS of a memory 3. The BCU 1 enables a driver 42, sends a value a+1 obtained by adding '1' to the contents of the address (a) to a data bus 52 and the value a+1 is read in the processor 2a. The BCU 1 asserts the CS of a memory 3 and writes an R/W signal, so that '1' is added to the contents of the address (a). Access to the address k+b of the processor 2b is similarly processed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor system, and particularly to a synchronization system between processors.

[Conventional technology]

Conventionally, in this type of multiprocessor system, synchronization between processors has been achieved using test and set instructions.

Here, the test and set instruction is an instruction that simultaneously executes a zero check and all 1 write of the contents of the memory, and as shown in FIGS. The processor that accesses the memory first reads zero and the test succeeds, and then accesses the memory L f (7"). The test is not successful because the t address has been written, and the test and set instruction is repeated until the preceding processor resets the contents of address t to zero, thereby synchronizing the processors.
In the example of Figures (a) and (b).

The two processors store data in the memory indicated by address a and update the contents of address a. Such processing is required to create a queue, which is essential in a multiprocessor environment.

If the test and set instruction is not used, MPU0 will
While reading the address and writing the updated value, the MPU
I reads address a, the po and pl values match, and the value written by MPU0.

MPUI K may be overwritten and lost.

[Problem that the invention seeks to solve]

However, the conventional inter-processor synchronization method described above requires a test-and-sent instruction, a test success determination instruction, and a clear instruction for the address to be tested and set.
When two processors execute test and set instructions almost simultaneously, there is a performance disadvantage in that one of the processors has to wait for the other processor to finish its execution.

SUMMARY OF THE INVENTION In view of the above drawbacks, it is a technical problem of the present invention to provide an inter-processor synchronization method that allows two processors to simultaneously execute test and set instructions without waiting for one processor to finish execution. It is.

[Failure to solve the problem]

According to the present invention, in a multiprocessor system having a bus controller that arbitrates bus requests from a plurality of processors, decodes addresses, and controls selection of responders, a value obtained by inputting data on a data bus and incrementing it by nine steps is used. providing a counter outputting to the data bus, accessing a word in a corresponding memory area when the bus controller accesses a word in a pre-allocated address space area, and reading an output of the counter to the processor; An inter-processor synchronization method is obtained which is characterized by controlling the data to be returned as data and writing back to the word at the read address.

In other words, the inter-processor synchronization method of the present invention includes a bus controller that determines bus requesters and responders and sends necessary control signals to the control bus, and a bus controller that inputs data and increments the value incremented by an incrementer. It has a counter that outputs data to the data bus through the counter.

〔Example〕

Next, one embodiment of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. The bus controller 1 has a control bus 53 and an address bus 5.
1 determines the bus requester and responder, and sends necessary control signals to the control bus 53. processor 2a
and processor 2b constitute a multiprocessor system that shares memory and independently executes tasks. Memory 3 stores data shared by the processors. Counter 4 inputs one word of data.

The value held by the latch 41 and incremented by 1 by the incrementer 43 is outputted through the driver 42. address bus 51
．． Data bus 52. The control bus 53 is a bus that connects the processor and memory.

Each transmits address, data, and control signals. Address outputs A of processors 2a and 2b are connected to address bus 5.
1, and data input/output is connected to a data bus 52. When the processors 2a and 2b request the bus, they assert the address strobe As and notify the bus controller 1 via the control bus 53. When the bus operation is completed, the bus controller 1 asserts the data response DTACK of the processor that accepted the bus request via the control bus 53.

The bus controller 1 decodes the upper bits of the address on the address bus 51, selects a peripheral device (not shown) or memory as the responder, and sends the device selection signal C8 of the selected device via the control bus 53. Assert. Address A of memory 3 is address bus 5
1, and data input/output is connected to a data bus 52.
connected to. The read/write designation R/W is connected via the control bus 53 to the read/write designation R/W of the processor using the bus.

The data bus 52 is connected to the latch 41 included in the counter 4, and the value incremented by 1 by the incrementer 43 is connected to the data bus 52 again via the driver 42. Latch 41. The driver 42 is controlled by the bus controller 1 via the control bus 53.

An example of operation will be explained according to FIG. processor 2ai
J' accesses address +a, and processor 2b accesses address +b. Here, k indicates the starting address of the area of the address space allocated to the counter 4. Bus controller 1 accepts a bus request for address +a from processor 2a, decodes the upper bits of address bus 51, detects that it is a counter area, and asserts CS of memory 3. Next, the bus controller 1 holds the memory cycle for one more cycle, enables the driver 42, adds the value (a) +1 to the contents of address a, and asserts DTACK of the processor 2a. The value (a) + 1 is read into the processor 2a. At the same time, the bus controller 1 asserts C8 of the memory 3 and writes the R/W signal, thereby incrementing the contents of address a by 1. Access to address +b of processor 2b is processed in the same way, and the content of address b+2 is +1 and the value (b) + 1 is the value (b) + 1 of processor 2b.
was loaded into. At the same time, the contents of address b are incremented by 1.

As shown in FIG.
If b accesses +a at the same location, b in Figure 2
By replacing ``a'' with ``a''.

It can be seen that pl=po+1, that is, it is possible to definitely give different values to the two processors.

〔Effect of the invention〕

As explained above, the present invention provides a high-speed synchronization mechanism between processors by connecting a counter to a data bus and incrementing the contents of memory when accessing a specific address space area. There is an effect that can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the inter-processor synchronization method of the present invention,
FIG. 2 is a time chart showing an example of operation, FIG. 3 is a flowchart showing an example of a synchronization program, and FIG. 4 is a flowchart showing an example of a conventional technique. 1... Bus controller, 2a, 2b... Processor. 3...Memory, 4...Counter, 41...Latch. 42...Driver, 43...Incrementer. Gloss: address latch, 51: address bus. 52...Data bus, 53...Controller no. (After successful completion of JO ■ After successful completion of MPLI I

Claims (1)

[Claims] 1. In a multiprocessor system that has a bus controller that arbitrates bus requests from multiple processors, decodes addresses, and selects and controls responders, data on a data bus is input and the incremented value is transferred to the data bus. A counter is provided for output, and when the bus controller accesses a word in a pre-assigned address space, a word in a corresponding memory area is accessed, and the output of the counter is read out to the processor and returned as data, An inter-processor synchronization method characterized by controlling writing back to the word at the address from which it was read.