JPH01169564A - Inter-processor synchronizing system - Google Patents

Abstract

PURPOSE:To provide a synchronizing mechanism between rapid processors by providing a counter and an address latch to a data bus, and at the time of accessing a specific address space area, stepping up the contents of a memory. CONSTITUTION:A processor (a) accesses an address k+a and a processor accesses an address k+b. A bus controller BCU 1 receives a bus request to the address k+a of the processor 2a, decodes the upper bit of an address bus 51, asserts the CS of a memory 3 and asserts the DTACK of the processor 2a, so that the contents (a) of the address (a) are read in the processor 2a. The BCU 1 holds an address latch 50 for another one clock, enables a driver 42, asserts the CS of the memory 3, and writes an R/W signal, so that '1' is added to the contents of the address (a). Access to the address k+b of the processor 2b is similarly processed and '1' is added to the contents of the address (b).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor system, and particularly to a synchronization system between processors.

[Conventional technology]

Conventionally, in this type of multiprocessor system, synchronization between processors has been achieved using test and set instructions.

Here, the test and set instruction is an instruction that simultaneously executes a zero check and all-one write of the contents of the memory, and as shown in FIGS. 4(a) and (b), two processors Issue a test and set command to the same address t.

The processor that accessed the memory first reads zeros and the test succeeds, while the processor that accesses the memory later has all 1s already written by the previous processor, so the test does not pass and the test succeeds. The idea is to synchronize the processors by repeating the test and set command until the processor sets the contents of address t to zero. In the example of FIGS. 4(a) and 4(b), the two processors have a memory IJK indicated by address a.
Data is stored and the contents of address a are updated. Such processing is required to create a queue, which is essential in a multiprocessor environment.

In addition, unless you use the test and set instruction.

While MPU0 reads address a and writes the updated value, MPUI reads address a and the values of pO and pl match, and the value written by MPU0 becomes M.
PUI may cause it to be overwritten and lost.

[Problem that the invention seeks to solve]

However, the conventional inter-processor synchronization method described above requires a test and set instruction, a test success determination instruction, and a clear instruction for the test and set target number M, and two processors execute the test and set instruction almost simultaneously. When executed, either processor has to wait for the other processor to finish execution, which is a drawback in terms of performance.

In view of the above drawbacks, the technical problem of the present invention is to provide an inter-processor synchronization method that allows two processors to execute a test and set instruction at the same time without waiting for one processor to finish its execution. The goal is to provide the following.

[Means for solving problems]

According to the present invention, in a multiprocessor system having a bus controller that arbitrates bus requests from a plurality of processors, decodes addresses, and controls selection of responders, a value obtained by inputting data bus data and incrementing it by nine steps is provided. A counter that outputs the address to the data bus and an address latch that holds the address to be supplied to the memory are provided.

The bus controller accesses a word in a pre-allocated address space area.

access the word in the corresponding memory area,
Hold the address latch for one more cycle and read the word at the address.

An inter-processor synchronization method is obtained, which is characterized in that the output of the counter is controlled to be written back.

In other words, the inter-processor synchronization method of the present invention includes a bus controller that determines bus requesters and responders and sends necessary control signals to the control bus, and a driver that inputs data and increments the value incremented by a counter register. It has a counter that outputs to the data bus through the memory, and an address latch that holds the address supplied to the memory.

〔Example〕

Next, nine aspects of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. The bus controller 1 has a control bus 53 and an address bus 5.
1, the bus requester and responder are determined, and necessary control signals are sent to the control bus 53. The processor 2a and the processor 2b share a memory 3 and have a multi-processor system configuration in which they independently execute tasks. Memory 3 stores data shared by the processors. The counter 4 inputs one word of data, and the counter register 41 outputs a value of ±1 to the driver 4.
Output through 2.

Address latch 50 holds an address supplied to memory 3. Address bus 51. Data bus 52 and control bus 531d These are buses that connect the processors 2a and 2b and the memory 3, respectively.

Conveys address, data and control signals. Address outputs A of the processors 2a and 2b are connected to an address bus 51, and data input/outputs are connected to a data bus 52. When processors 2a and 2b request the bus,
The address strobe AS is asserted and the bus controller 1 is notified via the control bus 53. Bus operation completed -1,! : The bus controller 1 asserts the data response input DTACK of the processor that has accepted the bus request via the control bus 53.

The bus controller 1 decodes the upper pit of the address on the address bus 51, selects a peripheral device (not shown) and memory as a responder, and sends a device selection signal C8 of the selected device via the control bus 53. Assert. The address input A of the memory 3 is connected to an address latch, and the data input/output is connected to a data bus 52. Read/write designated R/W is control bus 5
3 to the read/write designation R/W of the processor using the bus. The data bus 52 is connected to the counter register 41 included in the counter 4, and the value incremented by 1 is connected to the data bus 52 again via the driver 42. Counter register 41. The driver 42 is controlled by the bus controller 1 via the control bus 53.

Next, an example of operation will be explained according to FIG.

Processor 2a is at address +a, processor 2b is at address +b
Access the street address. Here, indicates the starting address of the area of the address space allocated to the counter 4. The bus controller 1 accepts a bus request for address '+a' from the processor 2a, and decodes the upper bits of the address bus 51.

It detects that it is a counter area and asserts C8 of memory 3. Subsequently, DTACK of the processor 2a is asserted, and the contents (a) of address a are read into the processor 2a. The bus controller 1 holds the address latch 50 for one more clock, enables the driver 42, asserts C8 of the memory 3, and increments the contents of address +a by 1 by writing the R/W signal. Access to address +b of processor 2b is processed in the same way, and after the content (b) of address b is read into processor 2b, the content of address b is incremented by +1.

As shown in FIGS. 3(a) and 3(b), the processor 2
With a.

When processor 2b accesses +a at the same location, by replacing b in FIG. 2 with a, pl=po
It can be seen that the value is +1, that is, it is possible to definitely give different values to the two processors.

〔Effect of the invention〕

As explained above, the present invention can provide a high-speed synchronization mechanism between processors by connecting a counter to a data bus and incrementing the contents of memory when accessing a specific address space area. effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the inter-processor synchronization method of the present invention,
Figure 2 is a time chart showing an example of operation, Figure 3 (a),
4(b) is a flowchart showing an example of a synchronization program, and FIGS. 4(a) and 4(b) are flowcharts showing an example of the prior art. 1... Bus controller, 2a, 2b... Processor. 3...Memory, 4...Counter. 41...Counter register, 42...Driver. Seki: Address latch, 51: Address bus. 52...Data bus, 53...Control bus. Figure 3 (α) MPUOMPU1 (b) Figure 4 (b)

Claims (1)

[Claims] 1. In a multiprocessor system that has a bus controller that arbitrates bus requests from multiple processors, decodes addresses, and selects and controls responders, data on a data bus is input and the incremented value is transferred to the data bus. and an address latch that holds an address to be supplied to the memory, so that the bus controller accesses a word in a corresponding memory area in response to an access to a word in a pre-allocated address space area. The inter-processor synchronization method is characterized in that the address latch is held for one more cycle, and the output of the counter is controlled to be written back to the word at the read address.