JPH01168031A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate the irregularity of a defective nucleus density and to improve its yield by using a wafer of single-crystal silicon doped with oxygen at a specific concentration during a Czochralski process and subjected to an intrinsic gettering process including low temperature, high temperature, and intermediate temperature annealing steps. CONSTITUTION:A wafer 1 is made of a P-type silicon single crystal doped with oxygen at 7.0X10<17>-9.0X10<17>atoms/cm<3> during a Czochralski process. After the surface of the wafer 1 so sliced that its planar orientation becomes a plane (100) is lapped, it is annealed at a low temperature for 16 hours in a nitrogen atmosphere at 700 deg.C, thereby forming defective nuclei therein. Thus, since the quantity of oxygen precipitate at the time of annealing can be accurately controlled, a high density defective region can be stably formed in the wafer, thereby effectively performing an IG effect. The low temperature annealing may be conducted before the wafer process is introduced after a polishing step. When the annealing is conducted in an oxygen atmosphere at 600-800 deg.C, the period of time may conduct for 4 hours or more.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a technology for manufacturing semiconductor devices using semiconductor wafers made of single crystal silicon, and is a technology that is effective when applied to intrinsic gettering of semiconductor wafers. It is related to.

[Conventional technology]

Intrinsic gettering is a technology that uses oxygen precipitation defects that occur inside a semiconductor wafer (hereinafter referred to as a wafer) to collect contaminant impurities in areas other than the active region of the device, and aims to eliminate their negative effects.
Gettering (hereinafter referred to as IG) is an indispensable technology for improving the characteristics and yield of semiconductor devices manufactured from the above-mentioned wafers, and its outline can be found, for example, in Yamamoto.

Etoard; “Life Time Improvement in Czochralskiy Blown Unibuzz by the Use of a Two-Step Annealing Applied Physics Letter 36.
1980) P2O3 (Yamamoto, et a
l;“Life time improvement
in Czochralski-grown 5ili
con wafers by the use of
a two-step annealing”＾ppl
, Phys, Lett, 36. (1980) P2O3)
There is a description in .

The IG process described above consists of: (1) creating a defect-free area (denuded zone; denuded z) near the surface of the wafer;

ne) high temperature annealing to form (approximately 1050 ~
(1200°C); (2) Low-temperature annealing (approximately 600-800°C) to form defect nuclei inside the wafer;

■ Medium-temperature annealing (approximately 1
000° C.), and a process in which annealing is performed in the order of high temperature, low temperature, and medium temperature, and a process in which the annealing is performed in the order of low temperature, high temperature, and medium temperature are usually employed.

In addition, the above IG may be performed in advance at a stage before the introduction of the process, or may be performed using an in-process heat treatment process, but in either case, in order to shorten the annealing time, etc. For some reason, the oxygen concentration doped during crystal growth using the Czochralski method (CZ method) is 9. It is usual to use a high oxygen concentration silicon single crystal wafer having an oxygen concentration of OX 10'' to 1. I x 10'' atoms/cut (Japan Electronics Industry Promotion Association conversion factor, hereinafter the same).

[Problem that the invention seeks to solve]

The present inventor has discovered that the conventional IG technique performed using the above-described high oxygen concentration silicon single crystal wafer has the following problems.

That is, the amount of oxygen precipitated in the crystal due to annealing depends on the oxygen concentration in the crystal, the annealing temperature, and the annealing time, but in the high oxygen concentration silicon single crystal wafer, the oxygen doped in the crystal is Since a large amount of oxygen is precipitated, it is extremely difficult to precisely control the amount of oxygen precipitated.

Moreover, in high oxygen concentration silicon single crystal wafers, the density of micro defects that occur in the crystal during crystal growth is greatly affected by the thermal history during crystal growth, so even if the annealing temperature and annealing time are constant, the number of defect nuclei is small. There is a problem that variations occur in the density and the IC effect is not effectively exhibited.

The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a technology that can effectively utilize the IC effect of a silicon single crystal wafer.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, when growing crystals using the Czochralski method, 7
．． OX 10"~9. OX 1017 atoms/c+
After doping +t oxygen into the crystal, -low temperature annealing,
A semiconductor device is manufactured using a silicon single crystal wafer that has undergone intrinsic gettering consisting of high-temperature annealing and medium-temperature annealing.

[Effect]

When we observe the relationship between the annealing time and the amount of oxygen precipitated when low-temperature annealing is performed in a nitrogen atmosphere at 650 to 800°C using the oxygen concentration doped during crystal growth as a parameter, we can see the relationship between the annealing time and the amount of oxygen precipitated, as shown in Figure 1. In the silicon wafer [A] with a high oxygen concentration, the amount of oxygen precipitated increases rapidly in the initial stage of annealing, but in the silicon wafer (B) with an oxygen concentration of 9.0 x 10" atoms/Cl11, the amount of oxygen precipitated increases. increases gradually in proportion to the annealing time, and this tendency becomes even more pronounced in silicon wafers CC) and CD) where the oxygen concentration is even lower.

In addition, a silicon wafer (B
], (C), and (D), the density of microdefects generated in the crystal is not affected much by the thermal history during crystal growth, so variations in the density of oxygen precipitation defects are less likely to occur.

For the reasons mentioned above, by using a silicon wafer with an oxygen concentration of 9.0 x 10'7 atoms/ci or lower, the amount of oxygen precipitated during annealing can be controlled with high precision, and the high-density defect region can be removed from the wafer. It becomes possible to stably form it inside, and the IG effect is effectively exhibited.

Furthermore, if the oxygen concentration in the crystal further decreases, it becomes increasingly difficult to form high-density defect regions, resulting in a decrease in the IG effect, and the wafer becomes more likely to warp. The lower limit is 7.0X10” atoms/cf
It is fl.

〔Example〕

FIGS. 2(a) to 2(d) are sectional views of essential parts of a wafer showing a method for manufacturing a semiconductor device according to an embodiment of the present invention in order of steps.

Below, CMO using wafer 1 made of silicon single crystal
A method for manufacturing a type 5 semiconductor device will be explained step by step.

Wafer 1- used in this example had 8.0×101ff atoms/CIII during crystal growth using the Czochralski method.
It consists of a p-type silicon single crystal doped with oxygen in the crystal and having a resistivity of about 100 cm.

First, the surface of a wafer 1 sliced so that the plane orientation is (100) is lapped, and then low-temperature annealing is performed for 16 hours in a nitrogen atmosphere at 700° C. to form defect nuclei inside.

The density of defect nuclei formed by this low-temperature annealing increases almost in proportion to the amount of precipitated oxygen, but in the above wafer 1, the amount of precipitated oxygen gradually increases in proportion to the annealing time. By measuring the amount of oxygen precipitated before and after low-temperature annealing using an external spectrophotometer, the density of defect nuclei can be controlled with high accuracy.

Next, after polishing the surface to a mirror finish, 5102 film 2 and S! *Na film 3
Then, arsenic (As) ions are implanted into a predetermined region opened by photoresist/etching to form an n-well region 4 (FIG. 2(a)).

Next, after removing the 3+3N4 film 3 on the surface,
When high-temperature annealing is performed for 6 hours in a nitrogen atmosphere of formed (Fig. 2 et al.)).

Next, by local oxidation method (LOCO3 method), about 1000
℃ steam oxidation for about 5 hours to form the element isolation region (field oxide film) 6 on the surface of the wafer 1, oxygen precipitates in the internal defect nuclei and a high density of defects occurs in the inner layer of the defect-free region 5. Region 7 is formed (FIG. 2(C)).

Next, after forming a gate insulating film 8 on the surface of the active region separated by the element isolation region 6, a normal CMOS
According to the process, after forming a polycrystalline Si gate 9 and sequentially implanting arsenic (As) and boron (B) to form a source region 10 and a drain region 11,
After forming a first interlayer insulating film 12a made of PSG to form a contact hole 13, and then patterning a first aluminum wiring layer 14a by vapor depositing aluminum (Aβ),
A second interlayer insulating film 12b and a second aluminum wiring layer 14b are formed in the same manner, and a protective film 15 is deposited on their surfaces (FIG. 2(d)).

After that, wafer 1 is divided into pellets by guising,
After bonding each pellet to a lead, a CMO3 type semiconductor device is obtained by sealing with a package.

As described above, according to this embodiment, the following effects can be obtained.

(1), the oxygen concentration in the crystal is 8.0×10” atoms/Cl
In the wafer 1 made of silicon single crystal No. 11, the amount of oxygen precipitated increases gradually in proportion to the annealing time, so the density of defect nuclei formed by low-temperature annealing can be controlled with high precision.

Therefore, it becomes possible to form a stable high-density defect region 7 inside the defect-free region 5, and the IG effect is effectively exhibited.

(2) As a result of (1) above, harmful heavy metal atoms attached to the surface of the wafer 1 are deposited in the high-density defect region 7 and the active region on the surface is cleaned, resulting in a reduction in leakage current of the MOS capacitor. As a result, the electrical characteristics and yield of CMO5 type semiconductor devices are improved.

As above, the invention made by the present inventor has been specifically explained based on Examples, but it should be noted that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Not even.

In the example, low-temperature annealing was performed for 16 hours in a nitrogen atmosphere after the lapping process, but the method is not limited to this.
For example, after a mirror finishing process by polishing, low temperature annealing may be performed before introducing a wafer process.

Note that when low-temperature annealing is performed in an oxygen atmosphere at 600 to 800° C., an annealing time of about 4 hours is sufficient.

Moreover, after performing high-temperature annealing together with the above-mentioned low-temperature annealing before introducing the wafer process, medium-temperature annealing may be performed using a heat treatment step during the wafer process.

Furthermore, the present invention can be applied not only to CMO3 type semiconductor devices but also to methods for manufacturing various semiconductor devices using wafers made of silicon single crystal, such as bipolar type semiconductor devices.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, when growing crystals using the Czochralski method, 7
．． Wafers made of silicon single crystal doped with 0x10" to 9.0x10" atoms/c/ of oxygen can be used to accurately control the amount of oxygen precipitated during low-temperature annealing. It becomes possible to form a high-density defect region, and the IG effect can be effectively exhibited.

Therefore, the electrical characteristics and yield of a semiconductor device in which integrated circuit elements are formed on the surface of the wafer are improved.

[Brief explanation of the drawing]

FIG. 1 is a graph showing the relationship between low-temperature annealing time and the amount of oxygen precipitated. FIG. 1... Semiconductor wafer, 2... SiO□ film, 3...
Si3N< film, 4...n well region, 5...defect-free region, 6...element isolation region, 7...high density defect region, 8...gate insulating film, 9...multiple crystal S1 gate,
10... Source region, 11... Drain region, 12
a... First interlayer insulating film, 12b... Second interlayer insulating film, 13... Contact hole, 14a... First aluminum wiring layer, 14b... Second aluminum wiring layer, 15...・
Protective film. Agent Patent Attorney Daiwa Tsutsui Figure 2

Claims (1)

[Claims] 1. During crystal growth by the Czochralski method, 7.0×10^1^7 to 9.0×10^1^7 atoms/
After doping with cm^3 of oxygen, an intrinsic process consisting of low temperature annealing, high temperature annealing and medium temperature annealing is performed.
A method for manufacturing a semiconductor device, characterized by using a semiconductor wafer made of gettered silicon and single crystal. 2. The method for manufacturing a semiconductor device according to claim 1, characterized in that low-temperature annealing is performed in a nitrogen atmosphere for 16 hours or more. 3. The method for manufacturing a semiconductor device according to claim 1, characterized in that low-temperature annealing is performed in an oxygen atmosphere for 4 hours or more. 4. The method of manufacturing a semiconductor device according to claim 1, wherein low temperature annealing is performed after the lapping step. 5. The method of manufacturing a semiconductor device according to claim 1, wherein low temperature annealing is performed after the polishing step.