JPH098294A - Insulated gate type semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [Purpose] To improve the breakdown voltage. [Constitution] In the profile of the P-type impurity concentration in the source / drain region of the PMOS transistor in the depth (Y) direction of the substrate, the differential coefficient: d (concentration) in the range from the substrate surface (Y = 0) to the PN junction. The absolute value of / dY does not monotonically increase with the depth Y, but once decreases at a position shallower than the PN junction. Therefore, the breakdown voltage is improved without deteriorating the characteristics such as the gate threshold voltage, the current driving capability, and the resistance to punch through. [Effect] The breakdown voltage is improved without deteriorating the characteristics such as resistance to punch through.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate semiconductor device suitable for a transistor forming a peripheral circuit of a flash memory and a method for manufacturing the same, and more particularly to an improvement for suppressing a punch-through and improving a breakdown voltage.

[0002]

2. Description of the Related Art In a flash memory, which is a type of non-volatile semiconductor memory device (ROM), an FN current (Fowler-Nordheu) is applied to a floating gate provided in a memory cell.
Writing and erasing are performed on the memory cell by injecting or ejecting electrons by (m tunnel current). Therefore, when writing and erasing data in the memory cell, it is necessary to apply a high voltage to the transistors forming the memory cell.

For example, reference: "Technical Report of Technical Information; Vol. 93, No. 74.
No. et al., Pp. 15-20; Onoda et al., "In memory cell transistors of flash memory, when writing, drain voltage Vd = 5-7V, control gate voltage Vcg = -7. .About.-9V, source voltage Vs = open (open; floating) is required. Further, when erasing, a drain voltage Vd = open, a control gate voltage Vcg = about 10V, and a source voltage Vs = −7 to −9V are required.

For this reason, the peripheral circuits such as the drive circuit incorporated in the semiconductor chip of the flash memory have ± 10
A transistor that can apply a bias voltage of about V is required. Therefore, transistors constituting the peripheral circuits are required to have a high breakdown voltage of 10 V or higher.

Generally, a peripheral circuit of a memory device is a CM
It is composed of an OS type transistor (hereinafter, abbreviated as “CMOS”). Among them, especially P channel type MO
Since the breakdown voltage of an S transistor (hereinafter abbreviated as “PMOS”) is generally determined by the junction between the source and drain, it has been difficult to maintain the driving capability and to increase the breakdown voltage.

FIG. 7 shows a conventional PMO forming a CMOS.
It is a front sectional view of S. In this PMOS, an N-type well (N-well) is formed on the upper surface (main surface) of the silicon semiconductor substrate.
Are selectively formed, and on the upper surface of the N-well, a pair of source / drain regions S / D containing a high concentration of P-type impurities are formed at regular intervals. The gate electrode G is opposed to the region near the upper surface of the substrate sandwiched between the pair of source / drain regions S / D, that is, the upper surface of the channel region, with the gate oxide film GOx interposed therebetween. The gate electrode G is composed of polysilicon doped with N-type impurities.

An N-type impurity is introduced into the channel region, and a P ^- layer into which the P-type impurity is introduced at a low concentration is shallowly formed on the upper layer thereof. In the PMOS in which the gate electrode G is made of N-type polysilicon, the work threshold difference between the gate electrode G and the N-well becomes small, and thus the gate threshold voltage Vth increases in the negative direction. In the PMOS of FIG. 7, a shallow P-N junction is formed in the channel region to suppress the expansion of the gate threshold voltage Vth. That is, this PMOS is an example of a so-called "embedded type" PMOS.

Although not shown in FIG. 7, source / drain electrodes (wiring) are connected to the upper surfaces of the source / drain regions S / D.

FIG. 8 is a graph showing the distribution of the impurity concentration and the potential along the line II 'of FIG. As shown by the solid line in FIG. 8 (a), a peak appears in the P-type impurity concentration corresponding to the P ⁻ layer, and N is further present in the deep portion thereof.
A peak appears in the concentration of N-type impurities corresponding to the channel region of the type. In addition, the potential curve reflecting this impurity concentration distribution descends from the deep portion of the substrate toward the upper surface as shown by the solid line in FIG. 8B, but draws a minimum in the P ⁻ layer, Turns upward to the top.

FIG. 9 is a front sectional view showing another conventional example of a PMOS forming a CMOS. This PMOS
7 is characteristically different from the PMOS of FIG. 7 in that the gate electrode G is composed of polysilicon into which a P-type impurity is introduced, and the P ⁻ layer is not provided above the N-type channel region. Since the gate electrode G is made of P-type polysilicon, the problem that the gate threshold voltage Vth is increased does not occur even if the PN junction is not formed in the channel region. That is, this PMOS is an example of a so-called "surface type" PMOS.

FIG. 10 is a graph showing the distribution of the impurity concentration and the potential along the line JJ ′ of FIG. As shown in FIG. 10A, a peak appears in the concentration of N-type impurities corresponding to the N-type channel region. Also, the potential curve monotonously decreases from the deep portion of the substrate toward the upper surface, as shown in FIG. 10B, reflecting this impurity concentration distribution.

Next, the embedded PMOS shown in FIG. 7 will be selected as a representative among these PMOSs, and the manufacturing method thereof will be described. By clarifying the manufacturing method, the location of the problem of the conventional device becomes clearer. Also,
The embedded PMOS will be described as an example, but the characteristic features of the manufacturing method are common to the surface PMOS as well because of the configuration related to the problem.

11 to 17 are manufacturing process diagrams of the embedded PMOS shown in FIG. In order to manufacture this PMOS, first, as shown in FIG. 11, on the upper surface of the semiconductor substrate, a field oxide film FLO for element isolation is formed outside the active region by using the LOCOS technique or the like.
forming x.

Next, as shown in FIG. 12, by implanting ions into the active region sandwiched by the field oxide film FLOX, a P-type channel dope layer CD, an N-type punch through stopper layer PS, and An N type isolation layer Iso is formed. When forming these layers, a resist film (not shown) is formed on the upper surface of the semiconductor substrate outside the region where the PMOS is to be formed, which corresponds to a partial region in the active region along the direction perpendicular to the paper surface of FIG. Are formed in advance to prevent these ions from being implanted outside the region where the PMOS is to be formed.

In the channel dope layer CD, ion implantation conditions are set so that desired gate threshold voltage Vth and drive current can be obtained. The channel dope layer CD has, for example, an implantation energy of 10 to 30 keV, and 1 to 8
It is formed by implanting boron with a dose of x10 ¹² cm ^-2 .

The conditions for forming the punch through stopper layer PS are set so that punch through can be suppressed as much as possible. The punch-through stopper layer PS has, for example, an implantation energy of 120 to 200 keV and a dose of 1 to 5 × 10 ¹² cm.
Formed by injecting phosphorus at ^-2 .

The isolation layer Iso has an adjacent P
It is provided to separate the MOSs. The isolation layer Iso has, for example, an implantation energy of 250 to 50.
It is formed by implanting phosphorus at 0 keV and a dose of 1-8 × 10 ¹² cm ^-2 .

Prior to the implantation of these ions, an "underlay oxide film" SOx is formed on the upper surface of the active region. This underlying oxide film SOx is provided to prevent damage to the upper surface of the active region due to ion implantation.

Implantation may be performed under the field region before forming the field oxide film FLOX.

AA 'section line in FIG. 12, and B
Fig. 1 shows the distribution of the impurity concentration along the -B 'cutting line.
3 and the graph of FIG. As shown in FIG.
In the impurity concentration distribution along the AA ′ cutting line, a peak appears in the concentration of the P-type impurity corresponding to the channel dope layer CD. Further, a peak appears in the concentration of the N-type impurity corresponding to each of the punch-through stopper layer PS and the isolation layer Iso. Also, as shown in FIG.
In the impurity concentration distribution along the BB ′ cutting line, a peak corresponding to the isolation layer Iso appears in the concentration of the N-type impurity in the deep portion of the field oxide film FLOX.

Next, after removing the underlying oxide film SOx by etching, as shown in FIG. 15, the upper surface of the active region is subjected to a process such as thermal oxidation so that the gate oxide film GOx has a desired thickness. Form. Further, a gate electrode G is formed by stacking, for example, a polysilicon layer on the region including the gate oxide film GOx and then patterning it to a desired width. The gate electrode G may have a so-called “polycide” structure in which a silicide layer is stacked on a polysilicon layer instead of being composed of polysilicon.

Next, as shown in FIG. 16, so-called sidewalls SW are formed on both sides of the gate electrode G.
The sidewall SW is formed, for example, by depositing an oxide film on the entire upper surface by using CVD or the like and then subjecting this oxide film to anisotropic etching. This sidewall SW is a so-called LDD (Lightly Dope
d Drain) is formed to have a structure.

The LDD transistor has a drain /
This is a transistor in which the electric field between the source and the drain is relaxed by lowering the impurity concentration of the portion of the source region adjacent to the channel. The LDD-structured transistor has an advantage that so-called hot carriers accelerated by the electric field between the source and the drain enter the gate oxide film GOx, thereby suppressing deterioration of the transistor life.

Next, as shown in FIG. 17, P-type ion implantation is performed in two steps in the region sandwiched between the sidewall SW and the field oxide film FLOX. At this time,
In the region sandwiched by the sidewall SW and the field oxide film FLOx, a part of the region along the direction vertical to the paper surface of FIG. By forming a resist film in advance, ions are prevented from being implanted outside the region where the PMOS is to be formed.

Boron or BF ₂ is used as P-type ions to be implanted. The first stage injection is, for example, 1
Implant energy of about 0 to 40 keV, 1 to 8 × 10 ¹³
This is achieved by injecting boron ions at a dose of about cm ⁻² and at an incident angle of about 20 to 60 ° with respect to the normal line to the upper surface of the semiconductor substrate. The implantation performed with an inclination with respect to the normal line is performed while rotating the incident direction around the normal line while keeping the incident angle constant.

The second-stage implantation to be subsequently performed is, for example, an implantation energy of 20 to 50 keV, and 1 to 5 × 10 5.
^This is achieved by injecting BF ₂ at a dose of about ¹⁵ cm ⁻² and in a direction along the normal line to the upper surface of the semiconductor substrate. When converted to the energy of boron ions, the implantation energy of the second stage is lower than the implantation energy of the first stage. Then, by applying heat treatment, the implanted ions are diffused and activated,
As a result, P-type source / drain regions S / D are formed.

First-stage injection (hereinafter referred to as "P (-) injection")
The P-type ions having a small implantation amount introduced by the above) are distributed in the upper layer portion of the source / drain region S / D.
This P (−) implantation is performed to form an LDD structure. On the other hand, the second stage injection (hereinafter referred to as “P (+) injection”)
Since the P-type ions introduced by () are widely spread by thermal diffusion due to the large amount of implantation, a deep distribution is formed so as to cover the region where the P-type ions introduced by P (-) implantation are distributed. . The P (+) implantation condition depends on the electrical resistance in the diffusion layer region from the connection (contact) of the source / drain region S / D with the source / drain electrode (wiring) to immediately below the gate electrode G. It is set to prevent deterioration.
After that, the process of forming the wiring and the like follow, but the description thereof will be omitted.

Next, the breakdown voltage of the transistor, which is the most important concept related to the background of the present invention, will be described in detail. For example, if a voltage of 10V is applied to drive a memory cell of a flash memory,
The withstand voltage of the transistor forming the drive circuit of the memory cell is required to have a withstand voltage as high as about 10% or more. Here, the breakdown voltage means that when a reverse voltage is applied only to the source or drain when the potential of the gate electrode G is set to 0 V and the transistor is turned off, the leak current has a predetermined minute level (for example, , A level of several μA). The leakage current at this time is derived from the carrier component in which the carriers generated by the Shockley lead holes are accelerated by the electric field in the PN junction and multiplied by the avalanche phenomenon.

The margin for the withstand voltage is required from the tolerance for the external power supply voltage, or in a memory having a booster circuit as a peripheral circuit in a semiconductor chip, the booster circuit has a voltage larger than the voltage to be set in the memory cell. It will be decided based on the request, etc. after taking into consideration what will happen in the company. The higher the breakdown voltage, the more flexible the circuit can be designed, which is desirable.

The withstand voltage of the PMOS described above is determined by the PN junction between the source / drain region S / D and the punch-through stopper layer PS and the isolation layer Iso. This PN junction is mainly determined by the P (+) implantation conditions and the N-type impurity implantation conditions for forming the punch-through stopper layer PS and the isolation layer Iso. This will be described below with reference to the drawings.

18 to 25 are diagrams showing the results of executing the simulation for the PMOS. This PM
In the OS, P (−) implantation is performed by implanting boron ions at an implantation energy of 30 keV, a dose of 2 × 10 ¹³ cm ⁻² , and an incident angle of 45 °, and P (+) implantation is also performed at a boron ion implantation energy of 10 keV. , Dose 4x
It is performed by implanting at 10 ¹⁵ cm ^-2 and an incident angle of 0 °. The energy of boron ions of 10 keV corresponds to the energy of BF ₂ of about 40 to 50 keV. The width of the sidewall SW is set to 0.15 μm. Further, in the heat treatment after implanting boron ions, the temperature is raised to 850 ° C. for 30 minutes.

FIG. 18 shows the concentration distribution of the P-type impurities along the front cross section of the PMOS in the region near the source / drain regions S / D by isoconcentration lines. In FIG. 18, the gate electrode G is located in a region of x (horizontal position) ≦ 1.00 μm. 19 to 22 are x = 0.95 μm, 1.00 μm, and
It shows the concentration distributions of P-type and N-type impurities along the Y (depth from the top surface of the substrate) direction at the positions of 1.05 μm and 1.32 μm.

As shown in FIGS. 19 and 20, x =
At the horizontal position of 0.95 μm or 1.00 μm, P-type impurities are distributed in a low concentration. From this, the P-type impurity distributed immediately below the gate electrode G and its vicinity is
It can be seen that it was introduced by the low dose P (−) implantation in which the oblique incidence was performed so as to penetrate directly below the sidewall SW. As described above, the electric field is relaxed by forming the regions having a low P-type impurity concentration at the ends of the source / drain regions S / D facing each other, and thus the deterioration of the lifetime of the transistor is suppressed.

On the other hand, as shown in FIG. 21, the gate electrode G
In the vicinity of x = 1.05 μm, which is a position just below the sidewall SW, which is slightly away from the end portion of P, the P-type impurity is distributed at a high concentration. From this, P of this area
It can be seen that the type impurities are mainly P-type impurities introduced by high-dose P (+) implantation and spread to just below the sidewalls SW by thermal diffusion.

Further, as shown in FIG. 22, at x = 1.32 μm (the position of the cutting line H in FIG. 18) located substantially in the center in the region sandwiched by the sidewall SW and the field oxide film FLOX. , Substrate surface (Y = 0.0
0 μm), the concentration of P-type impurities is 1.0 × 10 ²⁰
It has reached a high level exceeding cm ^-3 . The P-type impurities in this region are mainly introduced by high dose P (+) implantation. Then, as typified by FIG. 22, P on the surface of the source / drain region S / D is
Source / drain region S /
The voltage drop due to electric resistance between the connection portion (contact) between D and the source / drain electrode (wiring) and the channel region can be suppressed low.

Further, from FIG. 21 and FIG. 22, x = 1.
In the PN junction in the region of 05 μm to 1.32 μm, P
The source / drain region S / D of the type has an N-type impurity layer (N-type impurity concentration of about 1 × 10 ¹⁷ c) corresponding to the punch-through stopper layer PS or the isolation layer Iso.
It can be seen that it is in contact with m ^-3 ).

23 to 25 are diagrams showing the results of simulation concerning the distribution of the electric field when a reverse voltage of -10 V is applied to the source / drain region S / D of the PMOS. Among these, FIG. 23 shows the electric field distribution along the front cross section in the region near the source / drain regions S / D by equipotential lines. In FIG. 23, the origin of the horizontal position (x ′ = 0.00 μm) is set at the end of the gate electrode G. As shown in FIG. 23, a potential change appears in the region from the vicinity of the PN junction between the source / drain region S / D and the N-type impurity layer toward the inside of the N-type impurity layer.

FIG. 24 is a graph showing the distribution of the electric field at the horizontal position (position of the cutting line K in FIG. 23) at x '= 0.617 μm where the electric potential gradient, that is, the electric field is the strongest. Figure A 24, P (+) and the electric field distribution in the case of performing a dose of injection of 4x10 ¹⁵ cm ^-2, the half 2x10 ¹⁵ c
Both electric field distributions are shown when performed at a dose of m ^-2 . The P (+) implantation illustrated in FIG. 17 is performed at 4 × 10 ¹⁵ cm ^−2.
The maximum value of the electric field is about 0.7 MV /
cm. The maximum value determines the withstand voltage. Further, it can be seen from FIG. 24 that the depletion layer mainly extends to the N-type impurity layer.

Since the breakdown voltage is determined by the maximum value of the electric field, the breakdown voltage can be increased by relaxing the electric field in the vicinity of the maximum value. For that purpose, it is easy to imagine that the first countermeasure is to reduce the implantation dose in P (+) implantation, and the second countermeasure is to reduce the impurity concentration in the punch-through stopper layer PS. To be done.

[0040]

According to the first countermeasure, as shown in the curve in FIG. 24 when P (+) implantation is performed at a dose of ² × 10 ¹⁵ cm ^-2 , the maximum value of the electric field is certainly descend. However, from the contact to the gate electrode G
There is a problem in that the current drive capability of the transistor is reduced because the electrical resistance immediately underneath, that is, up to the channel region is increased.

The effect of the second countermeasure is shown in FIG. That is, FIG. 25 shows the electric field distribution at the horizontal position of x ′ = 0.61 μm when the N-type impurity concentration in the punch-through stopper layer PS is high (PS up) and low (PS normal). As shown in FIG. 25, when the impurity concentration in the punch-through stopper layer PS is lowered, the maximum value of the electric field certainly lowers.

However, in FIG. 8, when the impurity concentration of the punch-through stopper layer PS is lowered, the depletion layer in the channel region is reduced in order to keep the gate threshold voltage Vth at the same value, as indicated by the dotted curve. Since it expands to the deep part of the semiconductor substrate, there is a problem that punch-through easily occurs between the source and drain. This means that it is difficult to obtain a transistor having a short gate length.

As described above, the conventional device has a problem that it is difficult to increase the breakdown voltage without reducing the current driving capability and suppressing the punch through.

The present invention has been made in order to solve the above-mentioned problems in the conventional device, and it is possible to improve the withstand voltage without lowering the current driving capability and suppressing the punch through. It is an object of the present invention to provide a gate type semiconductor device, and further to provide a method suitable for manufacturing this insulated gate semiconductor device.

[0045]

According to a first aspect of the present invention, a channel region facing a gate electrode and source / drain regions sandwiching the channel region are formed on a main surface of a semiconductor substrate, and the source / drain region is formed. In an insulated gate semiconductor device in which wiring is connected to the drain region,
The absolute value of the differential coefficient of the concentration of impurities forming the conductivity type of the drain region with respect to the depth of the semiconductor substrate decreases from the increase at at least one position shallower than the PN junction as the depth increases. To turn to
The concentration is distributed.

The device of the second invention is the insulated gate semiconductor device of the first invention, wherein the source / drain regions are formed directly below the gate electrode with a lower impurity concentration than in the connection portion with the wiring. It is characterized by having invaded a part.

In the manufacturing method of the third invention, a channel region facing the gate electrode and a source / drain region sandwiching the channel region are formed on the main surface of the semiconductor substrate, and wiring is provided in the source / drain region. In the method for manufacturing a connected insulated gate semiconductor device, the step of forming the source / drain regions includes the step of forming the source / drain regions by using a first shield formed on the main surface. A lower dose and a higher dose than in the first step are used by using a first step of selectively implanting impurities forming a conductivity type into the main surface and a second shield formed on the main surface. A second step of selectively implanting the impurities into the main surface with implantation energy, and a third step of performing heat treatment after the first and second steps to diffuse and activate the impurities. And so that the impurities injected in the second step reach the vicinity of a PN junction formed by diffusing the impurities injected in the first step in the third step. By setting the implantation energy in the second step, the absolute value of the differential coefficient of the impurity concentration with respect to the depth of the semiconductor substrate is
The impurity concentration distribution in the source / drain regions is formed such that the depth / intensity is changed to increase / decrease at least at one location shallower than the PN junction. .

The manufacturing method of the fourth invention is the manufacturing method of the third invention, wherein the step of forming the source / drain regions is a third shield formed on the main surface prior to the third step. The body is used to selectively remove the impurities at a dose lower than that in the first step and higher than that in the second step, and with a higher implantation energy than the first step and lower than the second step. And a fourth step of introducing the impurity into the shallow layer near the main surface in a region where the impurity injected in the first step diffuses in the third step. Is distributed, and the impurities injected in the fourth step partially penetrate into the region directly below the gate electrode with an impurity concentration lower than the impurity concentration of the connection portion with the wiring. Wherein the steps are performed.

The manufacturing method of the fifth invention is the manufacturing method of the fourth invention, wherein a gate insulating film is formed on the main surface and the gate insulating film is formed prior to the step of forming the source / drain regions. And forming the gate electrode on the third shield, the third shield having the gate electrode as at least a part thereof, and the first and second shields.
The shields have the same shape as each other, and at least a part of the gate electrode has sidewalls added to the sidewalls, and the edge of the shield extends beyond the third shield by the amount of the sidewalls. It is characterized by

The manufacturing method of the sixth invention is the manufacturing method of the fourth invention, wherein a gate insulating film is formed on the main surface and the gate insulating film is formed prior to the step of forming the source / drain regions. A step of forming the gate electrode on the above, wherein the first to third shields have the same shape as each other, and at least a part of the gate electrode having sidewalls added to the sidewalls,
In the first and second steps, the impurity is injected by being incident in a direction along the normal to the main surface, and in the fourth step, the incident direction is inclined with respect to the normal. The impurity implantation is performed while rotating around the normal line.

[0051]

In the device of the first invention, the absolute value of the differential coefficient of the impurity concentration of the source / drain regions with respect to the depth of the semiconductor substrate increases monotonically until the PN junction is reached as the depth increases. Instead, the change is made from increase to decrease at least at one place, so that the breakdown voltage is improved without deteriorating the characteristics such as the gate threshold voltage, the drive current, and the resistance to punch through.

In the device of the second invention, the source / drain regions partially infiltrate directly below the gate electrode with a lower impurity concentration than in the connection portion with the wiring.
The electric field between the drains is relaxed.

In the manufacturing method of the third invention, the impurity is implanted into the source / drain regions in at least two steps, and moreover, in the vicinity of the PN junction formed by the impurity implanted at a high dose in the first step. To reach, a low dose impurity implant is performed in the second step. As a result, the absolute value of the differential coefficient of the impurity concentration with respect to the depth of the semiconductor substrate changes from increasing to decreasing at least at one location before reaching the PN junction as the depth increases. The impurity concentration distribution in the drain region can be obtained.

In the manufacturing method of the fourth aspect of the invention, the implantation of impurities into the source / drain regions is performed in three steps, and
The impurities implanted in the fourth step partially infiltrate into the region directly below the gate electrode with an impurity concentration lower than that of the connection portion with the wiring, so that an insulated gate semiconductor device having an electric field relaxation effect can be obtained. Moreover, since the impurities implanted in the fourth step are distributed in the shallow layer in the region where the impurities implanted in the first step are diffused, interference with the impurities implanted in the second step can be suppressed. Therefore, the impurities implanted in the second step do not significantly hinder the electric field relaxation effect.

In the manufacturing method of the fifth invention, the edges of the first and second shields used in the first step and the second step are more edged than those of the third shield used in the fourth step. The side wall provided on the side wall of the gate electrode overhangs. Therefore, the interference of the impurities implanted in the first step and the second step with the impurities implanted in the fourth step and penetrating into the region immediately below the gate electrode can be further suppressed. That is, the electric field relaxation effect appears more effectively.

In the manufacturing method of the sixth invention, all of the first to third shields have the same shape, and at least a part of the gate electrode has sidewalls added to the sidewalls, and the first step The implantation in the second step is performed by vertical incidence, and the implantation in the fourth step is performed by oblique incidence rotating around the normal line. Therefore, the impurities that are injected in the fourth step and enter the region immediately below the gate electrode are
Interference due to impurities implanted in the first step and the second step is further suppressed. That is, the electric field relaxation effect appears more effectively.

[0057]

【Example】

<1. Embodiment> A front sectional view of a PMOS of this embodiment is
It is drawn the same as in FIG. In the PMOS of this embodiment, the distribution of the P-type impurity concentration in the source / drain regions S / D is characteristically different from that of the conventional device.

FIG. 1 shows Y (depth) of the P-type impurity concentration in the source / drain region S / D of the PMOS of this embodiment.
It is a graph which shows the simulation result regarding distribution of directions. FIG. 1 shows representatively the distribution at the horizontal position corresponding to x = 1.03 μm in FIG. 18 showing the simulation result for the conventional device, and for comparison, the simulation result of FIG. 18 for the conventional device is also shown. Shows.

As shown in FIG. 1, in the conventional device, the concentration gradient in the Y direction in the P-type impurity distribution of the source / drain regions S / D, that is, the differential coefficient: d (concentration) / dY is
From the upper surface of the substrate to the PN junction, the depth (Y) increases monotonically in the negative direction as the depth (Y) increases. That is, the absolute value of the differential coefficient: d (density) / dY is monotonically increasing. On the other hand, in the apparatus of the embodiment, the absolute value of the differential coefficient: d (density) / dY is at least once,
It has started to decrease. Moreover, the decrease begins in the region where the P-type impurity concentration is 1 × 10 ¹⁷ cm ⁻³ or more.

In order to obtain such a characteristic profile with respect to the P-type impurity concentration of the source / drain regions S / D, the following manufacturing method may be executed. That is, first, after performing the manufacturing process shown in FIGS. 11 to 16, as shown in FIG. 17, P (−) implantation and P (−) implantation are performed.
(+) Perform injection. Then, as shown in the process diagram of FIG. 2, P-type ion implantation in the third stage (hereinafter abbreviated as “P ₀ implantation”) is performed. In FIG. 2, the same or corresponding parts as those of the conventional device shown in FIGS. 7 and 17 are designated by the same reference numerals, and detailed description thereof will be omitted.

This P ₀ implantation is performed by implanting P-type ions, and preferably, like P (+) implantation, implantation is performed along the normal line direction of the upper surface of the semiconductor substrate, that is, at an incident angle of 0 °. Is done. Further, the implantation energy is set so that the implanted P-type ions reach the vicinity of the PN junction formed by the P (+) implantation. Further, preferably, the implantation dose is set to be lower than the dose at the time of P (−) implantation. Note that P
The order of (−) injection, P (+) injection, and P ₀ injection may be arbitrary.

The P-type impurity concentration profile of the embodiment shown in FIG. 1 is P under the simulation conditions of FIG.
(-) Injection and P (+) injection are performed, and 50k
It concerns a PMOS obtained by performing a P ₀ implant by implanting boron with an implantation energy of eV, a dose of 5 × 10 ¹² cm ^{−2 and} an incident angle of 0 °. The curve of the conventional example of FIG. 1 is obtained by omitting the P ₀ injection and under the condition of FIG.
PM obtained by performing only P (-) injection and P (+) injection
It relates to the OS. That is, the difference between the two curves in FIG. 1 is due to the presence or absence of P ₀ injection.

The electric field distribution at the horizontal position of x '= 0.62 μm in the PMOS of the embodiment shown in FIG. 1 is shown in the graph of FIG. For comparison, FIG. 3 simultaneously shows, for comparison, curves relating to the PMOS of the conventional example, that is, the PMOS obtained by omitting P ₀ implantation and performing only P (−) implantation and P (+) implantation. It can be understood from FIG. 3 that in the PMOS of the embodiment, the maximum value of the electric field is reduced by about 20% as compared with the conventional example, and the effect of alleviating the electric field is remarkable.

FIG. 4 shows the PMO of the embodiment in which P ₀ implantation was performed.
Regarding S and the conventional PMOS that does not perform P ₀ implantation,
X = 0.95 μm, which is a horizontal position overlapping the gate electrode G
5 is a graph showing an impurity concentration distribution in FIG. The curve of the conventional example is the same as the curve of FIG. As can be seen from FIG. 4, the P ₀ -implanted PMOS of the embodiment has a slightly higher P-type impurity concentration in the region immediately below the gate electrode G than the conventional PMOS. This means
Considering only the region directly below the gate electrode G, it is equivalent to the case where the amount of implanted ions in P (−) implantation is increased as compared with the conventional example.

That is, the P ₀ implantation affects the impurity concentration in the region immediately below the gate electrode G, and as a result,
Punch through in the drain region S / D is somewhat likely to occur. However, the implantation dose for P ₀ implantation is P
It is set lower than that of (-) implantation, and the effect on punch-through is not as great as the improvement in withstand voltage. Therefore, the implantation doses of both P (−) implantation and P ₀ implantation are adjusted so that the impurity concentration directly under the gate electrode G by both P (−) implantation and P ₀ implantation becomes equal to that of the PMOS of the conventional example. If so, the withstand voltage can be improved while maintaining the same resistance to punch-through.

In order to verify the characteristics of the apparatus of the embodiment including the above, a prototype was manufactured and the characteristics were measured. The results are shown in Table 1, FIG. 5, and FIG. Table 1
In, the devices numbered 1 to 3 are conventional devices,
As the injection conditions, the P (−) injection conditions are described.
Further, the device of number 4 is the device of the embodiment, and both P (−) injection and P ₀ injection are described as injection conditions. The data regarding the device of number 3 is a predicted value obtained by interpolating from the data regarding the prototype devices of number 1 and number 2. The breakdown voltage BVds is defined by the applied voltage when a leak current of 1 μA flows when it is off.

[0067]

[Table 1]

The apparatus of the embodiment of No. 4 has the implantation energy of 35 keV, the dose of ² × 10 ¹³ cm ^-2 , the angle of incidence of 45 °, and the P (−) implantation is carried out by implanting boron. Injection energy, 5x10
^This is a device in which P ₀ implantation is performed by implanting boron at a dose of ¹² cm ^{−2 and} an incident angle of 0 °. On the other hand, the conventional device of No. 3 which is most suitable for comparison is 35k.
eV implantation energy, 3 × 10 ¹³ cm ^-2 dose, 45
By injecting boron at an incident angle of °, P (-)
The device that was injected. In the device of the embodiment, the P ₀ implantation is performed at an incident angle of 0 ° in order to reduce the influence of the P (−) implantation on the impurity concentration distribution just below the gate electrode G.

Comparing the conventional device of No. 3 with the device of the embodiment of No. 4, the gate threshold voltage Vth, the current between the source and drain regions (that is, the drive current) Ids,
Also, the minimum gate length Lmin has the same value. Moreover, the breakdown voltage BVds is higher in the device of the example of No. 4 than in the conventional device of No. 3. That is, the actual measurement results shown in Table 1 demonstrate that the device of the example can improve the withstand voltage while making the characteristics other than the withstand voltage equivalent to those of the device of the conventional example.

Similar results are obtained with respect to resistance to punch-through. This is shown in FIGS. 5 and 6. That is, FIG. 5 and FIG.
3 is a graph showing the results of actually measuring the dependence of the leak current at the time of off on the drain voltage in the conventional device of No. 2 and the device of the example of No. 4. In both the conventional device and the device of the embodiment, the gate length L is 0.55 μm and 0.60 μm.
m and 0.65 μm have been experimentally manufactured, and both the drain current Id and the source current Is have been actually measured.

For example, comparing the two devices under a normal operating condition where the drain voltage is -10.0 V, in the conventional device having the gate length L of 0.60 μm (FIG. 5), both the drain current Id and the source current Is are It is several hundred pA.
On the other hand, similarly, in the device of the embodiment (FIG. 6) having the gate length L of 0.60 μm, both the drain current Id and the source current Is are several tens pA, which is 1
It is an order of magnitude lower. Even in a device having a gate length L of 0.65 μm, it is also reduced by almost one digit, and the gate length L is 0.
In the device of 55 μm, it is almost two orders of magnitude lower.

The height of the leak current is directly related to the likelihood of punch through. As shown in Table 1, the devices of Nos. 2 and 4 have almost the same withstand voltage BVds. On the other hand, as can be seen from FIGS. 5 and 6, the resistance to punch-through is improved. This means that by optimizing the conditions of P (−) implantation and P ₀ implantation as in the device of No. 3, it is possible to improve the withstand voltage BVds while making the punch-through resistance equal. Is sufficiently predicted.

As described above, the device of this embodiment has characteristics other than the withstand voltage, in particular, the gate threshold voltage Vth and the drive current Id.
It is possible to improve the breakdown voltage BVds while maintaining the same resistance to punch-through and punch-through as the conventional device.

<2. Modifications> (1) By increasing the dose of P ₀ implantation and instead lowering the dose of P (−) implantation, or in addition, P
Even if only the P ₀ injection is performed without the (−) injection, the differential coefficient: d (concentration) / d as illustrated in FIG.
It is possible to create a region where the absolute value of Y turns to decrease. By doing so, resistance to punch through, L
The breakdown voltage can be improved while sacrificing some of the advantage of the DD structure such as long life. Even in the PMOS formed in this way, 1 without the sidewall SW.
Compared with a PMOS obtained by implanting P-type impurities at a stage, that is, a PMOS having no LDD structure, there is an advantage that the breakdown voltage is improved without deteriorating other characteristics.

(2) In the above embodiment, P (-) implantation, P (+) implantation, using the sidewall SW as a shield.
And P ₀ injection was performed respectively. However,
The P (−) implantation may be performed before forming the sidewall SW. Even if P (−) injection is performed in this way,
A PMOS with a DD structure is obtained. Also, at this time,
The P (−) implantation can also be performed at an incident angle of 0 °. Of course, if the P (−) implantation is performed by oblique incidence without the sidewall SW, the spread of the P-type impurity region immediately below the gate electrode G increases, so that the characteristics of the LDD structure become better.

In addition to P (−) implantation, P ₀ implantation can be performed before forming the sidewall SW.
Since P ₀ implantation has a higher implantation energy than P (−) implantation, the P-type impurities introduced by P ₀ implantation are mainly distributed deeper than the P-type impurities introduced by P (−) implantation. Therefore, the influence of P ₀ implantation on the P-type impurity concentration directly below the gate electrode G does not appear strongly. Moreover, by making the dose of P ₀ implantation lower than the dose of P (−) implantation,
Furthermore, the influence can be diluted.

(3) In the above embodiment, the embedded type P
Although the MOS transistor is taken as an example, the same configuration can be applied to the surface type PMOS transistor and the same effect can be obtained. Also, not limited to the PMOS transistor,
The same applies to the NMOS transistor. further,
Not only the MOS transistor but also the MO on the upper surface of the semiconductor substrate.
A semiconductor device having an S structure, that is, a general insulated gate semiconductor device including an IGBT (Insulated Gate Bipolar Transistor) and the like can have the same configuration and can also obtain the same effect.

[0078]

In the device of the first invention, the absolute value of the differential coefficient of the impurity concentration of the source / drain regions with respect to the depth of the semiconductor substrate is monotonic until the PN junction is reached as the depth increases. Since the voltage changes from increase to decrease at least at one place, the breakdown voltage is improved without deterioration of characteristics such as gate threshold voltage, drive current, and resistance to punch through.

In the device of the second invention, the source / drain region partially penetrates directly under the gate electrode with a lower impurity concentration than that at the connection portion with the wiring.
The electric field between the drains is relaxed. Therefore, the deterioration of the transistor life caused by the hot carriers accelerated by the electric field between the source and the drain entering the gate oxide film can be suppressed.

According to the manufacturing method of the third invention, the impurity is implanted into the source / drain regions in at least two steps, and moreover, in the vicinity of the PN junction formed by the impurity implanted with a high dose in the first step. To reach, a low dose impurity implant is performed in the second step. Therefore, it is possible to obtain an insulated gate semiconductor device having an increased breakdown voltage without deteriorating characteristics such as gate threshold voltage, drive current, and resistance to punch through.

In the manufacturing method of the fourth aspect of the invention, the implantation of impurities into the source / drain regions is performed in three steps, and
The impurities implanted in the fourth step partially infiltrate into the region directly below the gate electrode with an impurity concentration lower than that of the connection portion with the wiring, so that an insulated gate semiconductor device having an electric field relaxation effect can be obtained. Moreover, since the impurities implanted in the fourth step are distributed in the shallow layer in the region where the impurities implanted in the first step are diffused, the impurities implanted in the second step have a large electric field relaxation effect. Is not disturbed.

In the manufacturing method of the fifth invention, the edges of the first and second shields used in the first step and the second step are more edged than those of the third shield used in the fourth step. The side wall provided on the side wall of the gate electrode overhangs. Therefore, it is possible to further suppress the interference of the impurities implanted in the region immediately below the gate electrode with the impurities implanted in the first step and the second step. That is, since the electric field relaxation effect is more effectively exhibited, a device having a longer life can be obtained.

In the manufacturing method of the sixth invention, all of the first to third shields have the same shape, and at least a part of the gate electrode has sidewalls added to the side walls, and the first step The implantation in the second step is performed by vertical incidence, and the implantation in the fourth step is performed by oblique incidence rotating around the normal line. For this reason, the first step and the second step are carried out for impurities entering the region immediately below the gate electrode.
Interference due to impurities implanted in the process is further suppressed. That is, since the electric field relaxation effect is more effectively exhibited, a device having a longer life can be obtained.

[Brief description of drawings]

FIG. 1 is a graph showing an impurity concentration profile of an apparatus according to an example.

FIG. 2 is a manufacturing process diagram of the device of the example.

FIG. 3 is a graph showing the electric field profile of an example device.

FIG. 4 is a graph showing an impurity concentration profile of the device of the example.

FIG. 5 is a graph showing leakage current vs. applied voltage in a conventional device.

FIG. 6 is a graph showing leakage current vs. applied voltage of the device of the example.

FIG. 7 is a front sectional view of a conventional device.

FIG. 8 is a graph showing characteristics of the conventional device of FIG.

FIG. 9 is a front sectional view of another conventional device.

10 is a graph showing characteristics of the conventional device of FIG.

FIG. 11 is a manufacturing process diagram of the conventional device of FIG. 7;

FIG. 12 is a manufacturing process diagram of the conventional device of FIG. 7;

13 is a graph showing an impurity concentration profile of the conventional device of FIG.

14 is a graph showing an impurity concentration profile of the conventional device of FIG.

FIG. 15 is a manufacturing process diagram of the conventional device of FIG. 7;

16 is a manufacturing process diagram of the conventional device of FIG. 7. FIG.

17 is a manufacturing process diagram of the conventional device of FIG. 7. FIG.

18 is a diagram showing an impurity concentration distribution of the conventional device of FIG.

19 is a graph showing an impurity concentration profile of the conventional device of FIG.

20 is a graph showing an impurity concentration profile of the conventional device of FIG.

21 is a graph showing an impurity concentration profile of the conventional device of FIG.

22 is a graph showing an impurity concentration profile of the conventional device of FIG.

FIG. 23 is a diagram showing a potential distribution of the conventional device of FIG. 7.

FIG. 24 is a graph showing an electric field profile of the conventional device of FIG. 7.

25 is a graph showing an electric field profile of the conventional device of FIG.

[Explanation of symbols]

G gate electrode, SW sidewall, S / D source / drain region, GOx gate oxide film, FLOx
Field oxide film, CD channel dope layer, PS punch-through stopper layer, Iso isolation layer.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/792

Claims (6)

[Claims] 1. A channel region facing a gate electrode on a main surface of a semiconductor substrate, and a source region sandwiching the channel region.
In an insulated gate semiconductor device in which a drain region is formed and wiring is connected to the source / drain region, a differential coefficient of a concentration of impurities forming a conductivity type of the source / drain region with respect to a depth of the semiconductor substrate. In the insulated gate semiconductor device, the concentration is distributed so that the absolute value of the value changes from increase to decrease at least at one position shallower than the PN junction as the depth increases. . 2. The insulated gate semiconductor device according to claim 1, wherein the source / drain regions partially infiltrate immediately below the gate electrode with an impurity concentration lower than that in a connection portion with the wiring. An insulated gate semiconductor device characterized by the above. 3. A main surface of a semiconductor substrate, a channel region facing a gate electrode, and a source region sandwiching the channel region.
A method for manufacturing an insulated gate semiconductor device in which a drain region is formed and wiring is connected to the source / drain region, wherein the step of forming the source / drain region is formed on the main surface. A first step of selectively implanting an impurity forming a conductivity type of the source / drain regions into the main surface using the first shield, and a second shield formed on the main surface. Using the first
A second step of selectively implanting the impurities into the main surface with a lower dose and a higher implantation energy than in the step; and, after the first and second steps, heat treatment is performed to diffuse the impurities. And a third step of activating, the impurities injected in the second step up to the vicinity of a PN junction formed by diffusing the impurities injected in the first step in the third step. By setting the implantation energy in the second step so that the absolute value of the differential coefficient of the impurity concentration with respect to the depth of the semiconductor substrate increases as the depth increases. The impurity concentration distribution in the source / drain region is formed so as to change from increasing to decreasing at least at one position shallower than the junction. Method for manufacturing an insulated gate semiconductor device which. 4. The manufacturing method according to claim 3, wherein the step of forming the source / drain regions is a third step formed on the main surface prior to the third step.
Select the impurities using a shield at a lower dose than in the first step and at a higher dose in the second step, and at a higher implant energy than in the first step and lower than in the second step. 4th to be introduced
The impurity implanted in the fourth step is distributed in a shallow layer near the main surface in a region where the impurity implanted in the first step diffuses in the third step, and The fourth step is performed so that the impurities injected in the fourth step partially infiltrate into a region directly below the gate electrode with an impurity concentration lower than that of a connection portion with the wiring. A method for manufacturing an insulated gate semiconductor device, comprising: 5. The manufacturing method according to claim 4, wherein prior to the step of forming the source / drain regions,
A step of forming a gate insulating film on the main surface and forming the gate electrode on the gate insulating film, the third shield having the gate electrode as at least a part thereof, The first and second shields have the same shape as each other, at least a part of the gate electrode having sidewalls added to the side walls, and the edge of the gate electrode is larger than the third shield by the amount of the sidewalls. A method of manufacturing an insulated gate semiconductor device, wherein the insulated gate semiconductor device is characterized by being overhanging. 6. The manufacturing method according to claim 4, wherein prior to the step of forming the source / drain regions,
Forming a gate insulating film on the main surface and forming the gate electrode on the gate insulating film, wherein the first to third shields have the same shape, and The gate electrode having a sidewall added to at least a part thereof, and in the first and second steps, the impurity is injected by being incident in a direction along a normal line of the main surface, In the fourth step, the method of manufacturing an insulated gate semiconductor device, wherein the impurity implantation is performed while inclining an incident direction with respect to the normal line and rotating around the normal line.