JP2002083958A - Method for setting ion implantation conditions and method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase threshold voltage (Vth) and drive current (I)
The present inventors have found an ion implantation condition for alleviating the electric field concentration of the LDD diffusion layer while suppressing the decrease in ds), and aiming to improve the MOS transistor characteristics. SOLUTION: "Setting of initial conditions for ion implantation" S1,
"Setting of channel impurity introduction condition" S2, "Improvement of acceleration energy, setting of ion implantation condition so as to keep threshold voltage constant" S3, "Condition that matches desired transistor characteristics from the set ion implantation condition" Selection ”S
4, "selection" S5, "change of initial conditions" S6,
By performing “selection and setting of ion implantation conditions” S7, the ion implantation conditions that can effectively alleviate the electric field at the end of the LDD while suppressing the decrease in the drive current (Ids) of the MOS transistor are set as follows. The threshold voltage (Vth) is kept constant at a desired value, and conditions for high acceleration energy and low dose are set.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of setting ion implantation conditions and a method of manufacturing a semiconductor device, and more particularly to a method of setting ion implantation conditions for setting the LDD formation of a MOS transistor and its ion implantation conditions. The present invention relates to a method of manufacturing a semiconductor device in which ion implantation is performed under ion implantation conditions set by using the above setting method.

[0002]

2. Description of the Related Art A DRAM is a MOSF for switching.
It has a memory cell structure having an ET and a storage capacitor, and has been increasingly miniaturized in recent years. A method of manufacturing a memory cell transistor is to increase the impurity concentration of a channel region in order to adjust a lowered threshold voltage of a transistor to a desired value due to a reduction in gate length and a thinner gate oxide film accompanying miniaturization. In order to obtain a good sub-threshold characteristic while avoiding the problem of the so-called short channel effect,
Attempts have been made to lower the energy of ion implantation (hereinafter referred to as LDD ion implantation) for forming the D diffusion layer and to make the LDD diffusion layer shallower by lowering the process temperature.

As described above, according to the trend of miniaturization, LD
The D diffusion layer has a shallower junction, and the impurity concentration at the junction has also been increased due to the higher concentration of channel impurities.

[0004]

However, the former shallow junction of the LDD diffusion layer not only makes the junction position in the depth direction shallower, but also causes the end portion of the LDD diffusion layer in the channel vertical direction limited by the gate electrode to be shallow. Since the rounded radius of the bonding shape in the above is substantially equal to the bonding depth, local electric field concentration is caused by the reduction of the radius. further,
The electric field is particularly concentrated at the corners of the LDD diffusion layer which are limited by the gate electrode and the element isolation. As a result, the internal electric field is increasing even though the operating voltage is decreasing as the device is downsized, and the leakage current caused by the electric field is increased and the data retention characteristic of the DRAM is reduced. It is causing deterioration.

In a process in which the channel impurity is highly concentrated, the LDD diffusion layer has a shallow junction, and has a low temperature,
As described above, an increase in leakage current due to the electric field is inevitable.

In particular, DR which has been actively developed in recent years
In the process of the AM-embedded logic, since the temperature of the process is reduced, the deterioration of the data holding characteristic becomes more remarkable for the above-mentioned reason. This is because the transistors in the mixed logic area have the shortest gate length at the forefront, and the high-performance logic mounting process uses the so-called dual gate and introduces the salicide technology, which is a technology for reducing the resistance of the diffusion layer. In order to maintain the functions of the logic regions, a low-temperature process in forming a DRAM is indispensable.

A means for reducing the junction leakage current caused by the electric field as described above is to reduce the electric field concentration particularly at the end of the LDD diffusion layer. By the way, phosphorus is generally used as an impurity of the LDD diffusion layer of a normal memory cell. Compared to the same N-type impurity, arsenic,
This is because the problem of the electric field concentration is small, and the occurrence of defects is also small compared to the introduction of arsenic.
Therefore, the following description describes phosphorus that is typically used as an impurity.

A general method for setting LDD ion implantation conditions for realizing electric field relaxation includes a method as shown in FIG.

FIG. 11A is a diagram showing the relationship between the threshold voltage (vertical axis) of a MOS transistor and the dose (horizontal axis) of the LDD ion implantation, as shown in FIG. While suppressing the short channel effect, L
The dose of DD ion implantation is reduced, that is, L
As the concentration of the DD diffusion layer is reduced, the threshold voltage (Vth) increases. Therefore, in order to compensate for the increase in the threshold voltage (Vth), the channel impurity concentration is lowered so that the threshold voltage (Vth) is adjusted to be constant.

However, in the above setting method, the LDD
Although the diffusion relaxation of the diffusion layer is achieved, the effective channel length (Lef
f) increases, and the parasitic resistance of the diffusion layer also increases, which directly leads to a reduction in the drive current (Ids). Therefore,
In order to secure the drive current (Ids), for example, in a MOS transistor having a gate length of 0.20 μm, the dose of ion implantation for forming an LDD is 2 × 10 ¹³ / cm ² or more.
The dose is set to 3 × 10 ¹³ / cm ^{2, and} the degree of freedom in setting is small.

FIG. 11B shows the relationship between the threshold voltage (vertical axis) of the MOS transistor and the acceleration energy (horizontal axis) of the LDD ion implantation, as shown in FIG. As the acceleration energy in LDD ion implantation is increased for electrolytic relaxation, the threshold voltage (Vth)
Decrease. Therefore, in order to compensate for the decrease in the threshold voltage (Vth), the channel impurity concentration is increased so that the threshold voltage (Vth) is adjusted to be constant.

However, the above-described setting method is not effective in alleviating electrolysis because the channel impurity concentration eventually increases. Further, since the effective channel length (Leff) is reduced by increasing the acceleration energy, the short channel effect is increased. Therefore, in the conventional technology,
With the progress of general generations, there is a tendency to lower energy.

As described above, when the channel impurity concentration increases due to the reduction in the size of the device, the acceleration energy of the LDD ion implantation is reduced, and the process temperature is lowered, whereby the impurity concentration profile at the edge of the diffusion layer is reduced. Since the effect of reducing the roundness is large, the internal electric field tends to increase even when the drive current (Ids) is reduced.

As shown in FIG. 11C, a relationship between the drive current (Ids) and the dose of the LDD ion implantation is shown in FIG.
Simply, lowering the concentration of the LDD diffusion layer increases the resistance of the LDD diffusion layer and causes deterioration of the drive current (Ids), which is limited.

As a result, lowering the concentration of the LDD diffusion layer so as not to affect the drive current (Ids) results in a very small effect of improving the data retention characteristics.

In general, the dose also tends to decrease as the generation progresses. For the 0.25 μm to 0.18 μm generation, the dose is set to 2 × 10 ¹³ / cm ^{2 to} 3 × 10 ¹³ / cm ^2. ing.

Therefore, an effective condition setting for relaxing the electric field of the LDD diffusion layer is to increase the energy of the LDD ion implantation condition. However, increasing the energy requires L
This is effective in reducing the electric field in the surface and in the depth direction by lowering the impurity concentration of DD as a whole, but simply increasing the energy reduces the effective channel length (Leff),
Since the threshold voltage (Vth) is reduced, this is a condition that is incompatible with device miniaturization.

In the prior art, generally, 0.25 μm
In the 0.18 μm generation, the acceleration energy of the LDD ion implantation is set to 30 keV to 20 keV. These ion implantation conditions correspond to Rp / Lg of 0.15 or less, where Rp represents the projection range of the implanted ions and Lg represents the gate length. As described above, under the LDD ion implantation conditions along the trend of miniaturization, for example, the LDD ion implantation conditions for a 0.18 μm generation memory cell having a word line of Lg = 0.20 μm are as follows. The dose is set to 3 × 10 ¹³ / cm ² at 20 keV.

In the present invention, the LD set as described above is used.
The object of the present invention is to solve the problem caused by the electric field concentration, which is a problem under D ion implantation conditions, to realize a reduction in leak current and an improvement in data retention characteristics due to an electric field relaxation in the LDD diffusion layer.

[0020]

SUMMARY OF THE INVENTION The present invention relates to a method for setting ion implantation conditions and a method for manufacturing a semiconductor device, which have been made to solve the above-mentioned problems.

According to the method of setting ion implantation conditions of the present invention, there are provided a step of setting initial conditions of ion implantation for forming a diffusion layer of the MOS transistor, and a step of setting desired conditions for the set initial conditions of ion implantation. Setting impurity introduction conditions to the channel region to obtain a threshold voltage;
With respect to the channel impurity set in the impurity introduction condition, the ion implantation condition of the diffusion layer in which the acceleration energy is made higher than the initial condition of the ion implantation and the threshold voltage of the MOS transistor is constant is set. Determining the presence or absence of a selection condition in the step of selecting and setting ion implantation conditions that satisfy desired transistor characteristics from the set ion implantation conditions of the diffusion layer. The step of changing the initial condition of the ion implantation when there is no selection condition in the step, and returning to the step of setting the initial condition of the ion implantation for forming the diffusion layer of the MOS transistor again; If a selection condition exists in the process, an ion satisfying a desired transistor characteristic is obtained from the set ion implantation condition of the diffusion layer. It is characterized by comprising a step of selecting and setting down implantation conditions.

In the method of setting the ion implantation conditions, not only the energy of the ion implantation conditions is increased, but also the dose is reduced so as to keep the threshold voltage constant. ) Is maintained while the lowering of the threshold voltage and the accompanying problems are avoided. By using this setting method, it is possible to increase the energy which could not be obtained in the conventional example. In addition, the effect of increasing the depth of the diffusion layer avoids the problem of lowering the drive current (Ids) as compared with a simple reduction in the dose, so that the electric field can be more effectively alleviated.

According to a method of manufacturing a semiconductor device of the present invention, there is provided a method of manufacturing a semiconductor device having MOS transistors separated by element isolation regions, according to the ion implantation conditions set by using the method of setting the ion implantation conditions of the present invention. The ion implantation of the diffusion layer of the MOS transistor is performed.

In the above method of manufacturing a semiconductor device, the effective channel length (Leff) is obtained by not only mainly increasing the energy of the ion implantation conditions but also reducing the dose so as to keep the threshold voltage constant. , And a decrease in threshold voltage and the accompanying problems are avoided. By using this setting method, it is possible to increase the energy which could not be obtained in the conventional example. In addition, since the effect of increasing the depth of the diffusion layer avoids the problem of lowering the drive current (Ids) as compared with a simple reduction in the dose, the electric field can be alleviated more effectively, and the reliability of the MOS transistor can be improved. Can be achieved.

According to the method of manufacturing a semiconductor device of the present invention, in the method of manufacturing a semiconductor device having MOS transistors separated by element isolation regions, the ion implantation for forming the diffusion layer of the MOS transistor is performed by projecting the ion implantation. The ion implantation condition is set so that a value obtained by dividing the process by the gate length of the MOS transistor is not less than 0.25 and not more than 0.35.

In the above method of manufacturing a semiconductor device, the value obtained by dividing the projection range of the ion implantation by the gate length of the MOS transistor is 0.25 or more and 0.35 or less in the ion implantation for forming the diffusion layer of the MOS transistor. Since the ion implantation conditions are set, it is possible to increase the acceleration energy and reduce the dose while maintaining the effective channel length (Leff) while keeping the threshold voltage constant. Since the energy can be increased, which cannot be obtained in the conventional example, the problem of lowering the drive current (Ids) can be avoided by the effect of increasing the depth of the diffusion layer as compared with a simple reduction in the dose. Therefore, the electric field can be more effectively alleviated, and the reliability of the MOS transistor can be improved.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for setting ion implantation conditions according to the present invention will be described with reference to the flowchart of FIG. FIG. 1 illustrates a method for setting conditions for LDD ion implantation of a MOS transistor formed in a memory cell region of a DRAM.

As shown in FIG. 1, first, in "setting of initial conditions for ion implantation" S1, initial conditions for ion implantation for forming a diffusion layer of a MOS transistor, for example, an LDD diffusion layer are set.

More specifically, for example, (a) the LDD ion implantation conditions are set to the LDD ion implantation conditions of one generation before. (A) From the proven process, the tendency toward shallow junction and low concentration is adopted. To set initial conditions. In the description of the present embodiment, for the gate length (word line width) Lg = 0.20 μm, phosphorus ions are used as ion species, and the acceleration energy is set to 20 ke.
V and the dose were set to 3 × 10 ¹³ / cm ² . The standard of the acceleration energy is a value Rp / Lg (vertical axis) obtained by dividing the projection range (Rp) of the ion implantation by the gate length (Lg) of the MOS transistor and the projection range (R
p) (horizontal axis), the execution channel length (Lef
From the viewpoint of f), conditions are set such that Rp / Lg is about 0.15. The dose needs to be set to a low concentration condition so that a desired drive current (Ids) can be approximately obtained, and to be higher than the impurity concentration of the channel region. That is, the LDD ion implantation conditions obtained by the conventional example were set as initial values.

Next, in "setting of channel impurity introduction condition" S2, an impurity introduction condition to the channel region is set so as to obtain a desired threshold voltage with respect to the initial condition of ion implantation previously set. At this time, the impurity introduction condition is set so as to obtain a desired threshold voltage while suppressing the short channel effect of the MOS transistor.

More specifically, the impurity implantation condition is set to a desired threshold voltage and a good controllability of the threshold voltage with respect to the set LDD ion implantation condition. Here, the desired threshold voltage is a threshold voltage of a DRAM cell transistor which is set so as not to deteriorate data retention characteristics due to a subthreshold in the transistor within a range of manufacturing and design value variations. The controllability of the threshold voltage means an impurity profile set to suppress a so-called short channel effect.

Although it is necessary to ensure element isolation capability, a detailed description of a method for setting an impurity profile of a channel region is omitted in this embodiment.

In the present embodiment, boron ions are used as the ion species, the acceleration energy is 120 keV, the dose is 2 × 10 ¹³ / cm ² , the boron ions are used as the ion species, the acceleration energy is 10 keV, and the dose is 1.5x
It was set to 10 ¹³ / cm ² .

Next, according to “setting of ion implantation conditions so as to increase the acceleration energy and keep the threshold voltage constant” S3, the ion implantation is performed on the channel impurities set under the impurity introduction conditions. The ion implantation condition for the LDD diffusion layer is set such that the acceleration energy is higher than the initial condition and the threshold voltage of the MOS transistor is constant. At this time, the dose of the ion implantation condition is set so that the threshold voltage becomes constant under the increased energy condition of the acceleration energy.

Specifically, the impurity profile of the channel region set for the above initial conditions is
An LDD ion implantation condition under which the threshold voltage of the S transistor becomes substantially constant is obtained as a combination of the acceleration energy and the dose. As a result, as shown in FIG. 3, the relationship between the acceleration energy and the dose is obtained. FIG.
In the graph, the vertical axis indicates the dose, and the horizontal axis indicates the acceleration energy.

At this time, the obtained threshold voltage (Vth)
Has a substantially constant value as shown in FIG. In FIG. 4, the vertical axis indicates the threshold voltage, and the horizontal axis indicates the acceleration energy. As shown in FIG. 4, it can be seen that even if the acceleration energy in the LDD ion implantation is increased, the ion implantation condition in which the threshold voltage does not change can be set by simultaneously reducing the dose.

As shown in FIG. 5, it can be seen that the electric field distribution in the depth direction at the end of the LDD diffusion layer has a larger electric field relaxation effect as the acceleration energy is deeper. In FIG. 5, the vertical axis indicates the electric field, and the horizontal axis indicates the depth from the LDD diffusion layer surface.

Next, each characteristic of the cell transistor will be described with reference to FIG.

FIG. 6A shows the electric field strength (vertical axis) at the silicon surface and at a depth of 50 nm with respect to the acceleration energy (horizontal axis) from the electric field profile of FIG. As can be seen from this figure, it is confirmed that the larger the acceleration energy, the greater the electric field relaxation effect.

FIG. 6B shows the sub-threshold swing (S value) (vertical axis) with respect to the acceleration energy. As the energy becomes higher, the S value tends to improve.

As shown in FIG. 6C, the drive current (Ids) (vertical axis) tends to decrease its current value due to the increase in energy.

Therefore, “selection of conditions suitable for desired transistor characteristics from set ion implantation conditions” S 4
An ion implantation condition that satisfies desired transistor characteristics is selected from the set ion implantation conditions of the diffusion layer. At this time, it is determined whether or not a selection condition exists based on “selection availability” S5. That is, with respect to the obtained LDD ion implantation conditions (relationship between dose amount and acceleration energy at which a constant threshold voltage is obtained), only the drive current (Ids) deteriorates, so that the desired drive current (Ids) is obtained. The ion implantation conditions are set so as to obtain Ids).

In this determination step, if there is no selection condition, that is, if the desired drive current (Ids) cannot be obtained, the initial condition of the ion implantation, for example, the dose, is changed by "change of initial condition" S6. The amount is changed to, for example, + α, and the process returns to “setting of initial conditions for ion implantation” S1 again to set new initial conditions for ion implantation for forming the diffusion layer of the MOS transistor. The change of the initial condition of the ion implantation is performed, for example, by changing the dose of the ion implantation condition. Conversely, even when the drive current (Ids) does not need to be obtained or when a sufficient drive current (Ids) cannot be obtained, the condition setting is performed by setting the initial dose amount setting value to, for example, -α.

On the other hand, if there is a selection condition in the determination step, the ion implantation condition satisfying the desired transistor characteristics is determined from the set ion implantation condition of the diffusion layer by "selection and setting of ion implantation condition" S7. Select and set. Here, the acceleration energy and the dose for obtaining a desired drive current are set based on the set ion implantation conditions of the diffusion layer.

In the present embodiment, the condition that the driving current (Ids) is almost 10% lower than the driving current (Ids) of the initial setting conditions is as follows: the acceleration energy is 35 keV, the dose is 2 × 10 ¹³ / cm ² , Alternatively, assuming that the drive current (Ids) is almost 20% lower, the acceleration energy is 40 keV,
The dose was selected to be 1.8 × 10 ¹³ / cm ² . When these are expressed by Rp / Lg, each Rp / Lg = 0.2
6, 0.29. The acceleration energy is 50
It is possible to select up to about keV.

Rp / Lg conventionally set to 0.15
This means that the energy-enhancing condition of about twice as large as that described above has been achieved.

In the above-described method of setting the ion implantation conditions, the effective channel length (Leff) can be reduced by not only mainly increasing the energy of the ion implantation conditions but also reducing the dose so as to keep the threshold voltage constant. ) Is maintained while the lowering of the threshold voltage and the accompanying problems are avoided. By using this setting method, it is possible to increase the energy which cannot be obtained in the conventional example, that is, set the acceleration energy to 35 keV to 50 keV. In addition, the effect of increasing the depth of the diffusion layer avoids the problem of lowering the drive current (Ids) as compared with a simple reduction in the dose, so that the electric field can be more effectively alleviated.

Next, the M isolated by the element isolation region
In a method of manufacturing a semiconductor device having an OS transistor, a semiconductor in which a diffusion layer of a MOS transistor, for example, an LDD diffusion layer is ion-implanted, under ion implantation conditions set by using the ion implantation condition setting method described with reference to FIG. A method for manufacturing the device will be described.

As shown in FIG. 7, for example, an STI (Shallow Trench)
Isolation) An element isolation region 12 having a structure is formed to isolate an element formation region. A gate electrode 14 is formed in the element formation region via a gate insulating film 13. A word line 15 is formed on the element isolation region 12. An offset insulating film 16 is formed on the gate electrode 14 and the word line 15.

In this state, the LD is placed on the semiconductor substrate 11.
D ion implantation is performed. The setting of the condition is the same as that described above.
It is determined by the setting method of the ON injection condition. As a result,
If phosphorus is used as the ion species, the threshold voltage and the driving electrode (I
ds) or other ion-implantation with desired transistor characteristics
The condition is that the acceleration energy is in the range of 35 keV to 50 keV.
Box, the dose is 2.0 × 10¹³/ Cm^Two~
1.5 × 10¹³/ Cm ^TwoSelected from the range
LDD ion implantation is performed using the above conditions. And illustrated
As described above, the L of the diffusion layer to which the storage node electrode is connected is
LDD of the diffusion layer connecting the DD diffusion layer 21 and the bit line
A diffusion layer 22 is formed.

Note that, since the element isolation region 12 has the STI structure, the element isolation region 12 can be formed to a deep position. Therefore, even if the acceleration energy is increased, the ions are not implanted through the element isolation region 12.

The gate length (Lg), effective channel length (Leff), and overlap length (Lov) of the LDD diffusion with the gate electrode described in each of the above embodiments are shown in FIG.
It is defined as shown below.

Next, a second embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. FIG. 8 shows a relationship between Rp / Lg (vertical axis) and acceleration energy (horizontal axis) [or phosphorus projection range (Rp)], where Rg is a projection range and Lg is a gate length, using Lg as a parameter. FIG. This can be rewritten as shown in FIG. FIG. 9 is a diagram showing the relationship between E / Lg (vertical axis) and acceleration energy (horizontal axis) using Lg as a parameter, where E is the acceleration energy and Lg is the word line (gate length).

When performing ion implantation for forming a diffusion layer of a semiconductor device having a structure as shown in FIGS.
The ion implantation conditions were such that the gate length (Lg) was 0.15 μm or more.
The value of Rp / Lg is set to be 0.25 or more and 0.35 or less for 0.25 μm, or E / L
g is 0.18 [keV / nm] or more and 0.25 [keV
V / nm] or less.

In the above method of manufacturing a semiconductor device, the ion implantation conditions are set so that the value of Rp / Lg is not less than 0.25 and not more than 0.35, or the value of E / Lg is 0.1.
Since the setting is made to be 18 keV / nm or more and 0.25 keV / nm or less, the threshold voltage is kept constant, the effective channel length (Leff) is maintained, and the acceleration energy is increased. And a lower dose are realized at the same time. Since the energy can be increased, which cannot be obtained in the conventional example, the problem of lowering the drive current (Ids) can be avoided by the effect of increasing the depth of the diffusion layer as compared with a simple reduction in the dose. Therefore, the electric field can be more effectively alleviated, and the reliability of the MOS transistor can be improved.

FIG. 10 shows the relationship between the data retention time of the DRAM (vertical axis) and the electric field inside the DRAM memory cell (horizontal axis). As shown in FIG. 10, it was confirmed that the data retention time of the DRAM became longer as the electric field was reduced.

In the ion implantation for forming the diffusion layer of the MOS transistor, increasing the acceleration energy and reducing the dose under the ion implantation conditions is a method aimed at relaxing the electric field at the end of the LDD diffusion layer. In return, the drive current (Ids) decreases. Therefore, there is a concern about insufficient writing / lower Vccmin margin, and there is a limit to electric field relaxation. Therefore, while ensuring the drive current (Ids) by relaxing the electric field at the end of the LDD diffusion layer to the same extent, changing the ion implantation angle (direction) so as to reduce the concentration at the corner and effectively relax the electric field. It is also possible to perform ion implantation.

[0058]

As described above, according to the method of setting the ion implantation conditions of the present invention, the electric field at the LDD end can be efficiently relaxed while suppressing the decrease in the drive current (Ids) of the MOS transistor. Ion implantation conditions that allow
By keeping the threshold voltage (Vth) constant at a desired value, conditions for high acceleration energy and low dose can be set. Therefore, the data retention characteristics of the DRAM can be improved.

According to the method of manufacturing a semiconductor device of the present invention,
Since the ion implantation conditions are set using the method for setting the ion implantation conditions of the present invention, and the diffusion layer of the MOS transistor is formed using the ion implantation conditions, the driving current (Ids)
It is possible to efficiently reduce the electric field at the end of the LDD while suppressing the decrease in the data density, and it is possible to manufacture a DRAM having good data retention characteristics. This allows
The refresh busy state can be reduced, and low power consumption can be achieved. Therefore, the reliability can be improved.

According to the method of manufacturing a semiconductor device of the present invention,
Ion implantation for forming a diffusion layer of a MOS transistor
The ion implantation conditions are set such that the value obtained by dividing the projection range of the ion implantation by the gate length of the MOS transistor is 0.25 or more and 0.35 or less.
Higher acceleration energy and lower dose can be realized while maintaining the effective channel length (Leff). Therefore, the LDD can be reduced while suppressing a decrease in the drive current (Ids).
The electric field at the end can be efficiently reduced, and a DRAM having good data retention characteristics can be manufactured. This makes it possible to reduce the refresh busy state and achieve low power consumption. Therefore, the reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating an embodiment of a method for setting ion implantation conditions according to the present invention.

FIG. 2 is a projection range (Rp) / gate length (L) of ion implantation.
FIG. 6 is a relationship diagram between g) and a projected range (Rp) of phosphorus ions.

FIG. 3 is a relationship diagram between an acceleration energy and a dose.

FIG. 4 is a relationship diagram between a threshold voltage and acceleration energy.

FIG. 5 is a diagram showing the relationship between the electric field in the depth direction at the end of the LDD diffusion layer and the depth from the surface of the LDD diffusion layer.

FIG. 6 is a diagram showing a relationship between electric field intensity and acceleration energy at a silicon surface and a position at a depth of 50 nm.

FIG. 7 is a schematic sectional view showing a configuration of a memory cell transistor.

FIG. 8 is a relationship diagram between Rp / Lg and acceleration energy for explaining a second embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 9 is a relationship diagram between E / Lg and acceleration energy for explaining a second embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 10 is a diagram showing a relationship between a data retention time of a DRAM and an electric field inside a DRAM memory cell.

FIG. 11 is a diagram for explaining a general condition setting method concerning LDD ion implantation conditions for realizing electric field relaxation;
(A) shows the threshold voltage of a MOS transistor and its LD
FIG. 4 is a diagram showing the relationship between the dose of D ion implantation and the dose, and FIG.
FIG. 4 is a diagram illustrating a relationship between a threshold voltage of an OS transistor and acceleration energy of the LDD ion implantation, and FIG. 4C is a diagram illustrating a relationship between a driving current and a dose amount of the LDD ion implantation.

[Explanation of symbols]

S1: "setting of ion implantation initial condition", S2: "setting of channel impurity introduction condition", S3: "setting of ion implantation condition so as to increase acceleration energy and keep threshold voltage constant", S4 ... "Selection of conditions suitable for desired transistor characteristics from set ion implantation conditions", S5
... "selection possible", S6 ... "change of initial conditions", S7 ...
"Select and set ion implantation conditions"

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/088 H01L 29/78 301H 27/108 21/8242 (72) Inventor Ryosuke Nakamura Kitagawa Shinagawa-ku, Tokyo 6-7-35 Shinagawa, Sony Corporation (72) Inventor Tohru Anesaki 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Yasuji Ema Nakahara, Kawasaki City, Kanagawa Prefecture 4-1-1, Kamikadanaka, Ward F-term in Fujitsu Limited (reference) 5F040 DA22 DA30 EA08 EE05 EF02 EK05 5F048 AA07 AA09 AB01 AB03 AC01 AC10 BA01 BB14 BC06 BG12 5F083 AD10 GA06 KA01 NA01

Claims (8)

[Claims] A step of setting an initial condition of ion implantation for forming a diffusion layer of a MOS transistor; and a step of setting a desired threshold voltage with respect to the set initial condition of ion implantation. Setting the impurity introduction condition of the above; and making the acceleration energy higher than the initial condition of the ion implantation and maintaining the threshold voltage of the MOS transistor constant with respect to the channel impurity set by the impurity introduction condition. In the step of obtaining the ion implantation condition of the diffusion layer to be obtained, and the step of selecting and setting the ion implantation condition that satisfies a desired transistor characteristic from the set ion implantation condition of the diffusion layer, whether a selection condition exists. Step of determining whether or not, in the determining step, if there is no selection condition, change the initial conditions of the ion implantation, And a step of returning to a step of setting initial conditions of ion implantation for forming a diffusion layer of the MOS transistor. If there is a selection condition in the determination step, the ion implantation conditions of the set diffusion layer are determined. Selecting and setting ion implantation conditions that satisfy desired transistor characteristics. 2. The step of setting conditions for introducing impurities into a channel region so as to obtain a desired threshold voltage with respect to the set initial conditions of ion implantation is performed while suppressing a short channel effect of the MOS transistor. 2. The method for setting ion implantation conditions according to claim 1, wherein the setting is performed so as to obtain a desired threshold voltage. 3. The diffusion layer according to claim 1, wherein acceleration energy of the channel impurity set in the impurity introduction condition is made higher than that in the initial condition of the ion implantation, and a threshold voltage of the MOS transistor is constant. The step of obtaining the ion implantation conditions of the above, under the accelerated energy conditions of high energy,
2. The method according to claim 1, wherein the dose of the ion implantation condition is set so that the threshold voltage is constant. 4. The step of selecting and setting ion implantation conditions satisfying a desired transistor characteristic from the set diffusion layer ion implantation conditions, comprising the steps of: selecting a desired drive current from the set diffusion layer ion implantation conditions; 2. The method for setting ion implantation conditions according to claim 1, wherein the acceleration energy and the dose for obtaining the ion implantation are set. 5. The method according to claim 1, wherein changing the initial condition of the ion implantation comprises changing a dose amount of the ion implantation condition. 6. A MOS isolated by an element isolation region.
In the method for manufacturing a semiconductor device having a transistor, a step of setting initial conditions of ion implantation for forming a diffusion layer of the MOS transistor; and setting a desired threshold voltage with respect to the set initial conditions of ion implantation. Setting the impurity introduction condition to the channel region to obtain; and increasing the acceleration energy to be higher than the initial condition of the ion implantation for the channel impurity set by the impurity introduction condition; and A step of obtaining ion implantation conditions of the diffusion layer at which the threshold voltage is constant; anda step of selecting and setting ion implantation conditions that satisfy desired transistor characteristics from the set ion implantation conditions of the diffusion layer. A step of determining whether a selection condition exists; and Changing the initial conditions of the ion implantation and returning to the step of setting the initial conditions of the ion implantation for forming the diffusion layer of the MOS transistor again; and Selecting and setting an ion implantation condition that satisfies a desired transistor characteristic from the set ion implantation condition of the diffusion layer, and setting the ion implantation condition using a method for setting an ion implantation condition. A method for manufacturing a semiconductor device, comprising: ion-implanting a diffusion layer of a MOS transistor. 7. The MOS transistor according to claim 1, wherein the diffusion layer is an LD.
7. The method according to claim 6, comprising a D diffusion layer. 8. A MOS isolated by an element isolation region
In the method of manufacturing a semiconductor device having a transistor, in the ion implantation for forming the diffusion layer of the MOS transistor, a value obtained by dividing a projection range of the ion implantation by a gate length of the MOS transistor is 0.25 or more and 0.35 or less. A method for manufacturing a semiconductor device, wherein ion implantation conditions are set as follows.