JPH098288A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To obtain desired transistor characteristics by always holding an effective gate length constant irrespective of the processing size of a gate electrode. CONSTITUTION: After a gate oxide film 3 and a gate electrode 4 are formed, the size of the electrode 4 is measured by using a scanning electron microscope. The implant amount of impurity 5 for forming source and drain regions is regulated by the amount meeting the deviation of the measured gate electrode 4 from the target value, and doped in a semiconductor substrate 1. That is, the implant amount of the impurity 5 is reduced, and the introduction of an impurity diffused layer 6 into the electrode 4 is suppressed. If the size of the electrode 4 is larger than the target value, the implant amount of the impurity 5 is increased to aid the introduction of the layer 6 into the electrode 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.

[0002]

2. Description of the Related Art In recent years, in semiconductor devices whose miniaturization is progressing from sub-micron to half-micron and further to quarter-micron, their transistor characteristics are very strongly influenced by the size of the gate electrode, and now they are stable and as desired. Establishing the process conditions for obtaining the gate electrode size is becoming the most important factor in achieving stable transistor characteristics.

A conventional method of manufacturing a semiconductor device having a MOS transistor will be described below. A sectional view in the order of steps of a conventional method for manufacturing a semiconductor device is the same as the sectional view in the order of steps in the embodiment shown in FIG. 1 and will be described with reference to FIG. In FIG. 1, 1 is a semiconductor substrate, 2 is an element isolation insulating film, 3 is a gate oxide film (gate insulating film), 4 is a gate electrode, 5 is an impurity, and 6 is an impurity diffusion layer.

First, as shown in FIG. 1A, an element isolation insulating film 2 is formed on a semiconductor substrate 1 by a selective oxidation method, and then a usual lithography technique and etching technique are used for forming a MOS transistor. The gate oxide film 3
And a gate electrode 4 are formed. Next, as shown in FIG. 1B, the surface of the semiconductor substrate 1 is doped with impurities 5 by an ion implantation technique using the gate electrode 4 as a mask. Then, as shown in FIG. 1C, the impurities 5 are activated in the semiconductor substrate 1 by annealing, and
The impurity diffusion layer 6 to be the drain region is formed. Normal,
The implantation amount of the impurities 5 and the annealing conditions for activating the impurities 5 are determined in advance, and it is common to perform the processing under the determined conditions without changing the conditions.

[0005]

However, in the above-described conventional manufacturing method, particularly in the case of a semiconductor device having a transistor characteristic that changes sensitively according to the size of the gate electrode 3, the processing size of the gate electrode in the process is increased. There is a problem in that the effective gate length also varies due to the variation (difference from the target dimension), and satisfactory transistor characteristics cannot be obtained.

The present invention solves the above-mentioned conventional problems, and a semiconductor device capable of obtaining desired transistor characteristics by keeping the effective gate length constant regardless of the processing size of the gate electrode. It aims at providing the manufacturing method of.

[0007]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a gate electrode is formed and then a gate length is measured. When the measured value is larger than a target value, a source / drain region is formed. Therefore, the ion implantation amount of impurities is increased, and when the measured value is smaller than the target value, the ion implantation amount of impurities is reduced.

A method of manufacturing a semiconductor device according to claim 2 is
After forming the gate electrode, measure the gate length, and if this measured value is larger than the target value, set the heat treatment condition for forming the impurity diffusion layer to be the source / drain region so that the diffusion of impurities becomes large and the measured value Is smaller than the target value, the heat treatment condition is such that the diffusion of impurities becomes small.

[0009]

According to the manufacturing method of the present invention, when the measured value of the gate length is larger than the target value, the ion implantation amount of the impurities for forming the source / drain regions is increased, and when the measured value is smaller than the target value, the impurity is injected. By reducing the amount of ion implantation of the impurities, or by setting the heat treatment condition for forming the impurity diffusion layer to be the source / drain region when the measured gate length is larger than the target value, to increase the impurity diffusion. When the value is smaller than the target value, the heat treatment conditions are set so that the diffusion of impurities becomes small, so that the effective gate length is always kept constant and the desired transistor characteristics are obtained, regardless of the processing size of the gate electrode. be able to.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1A to 1D are cross-sectional views in order of the steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Here, differences from the conventional manufacturing method will be mainly described. FIG.
After forming the gate oxide film 3 and the gate electrode 4 by the usual lithographic technique and etching technique, as shown in (a) of FIG. 7, the dimension (gate length) of the gate electrode 4 is measured using a scanning electron microscope. . In particular, for a microcomputer / logic LSI having a random pattern, if the area of the gate electrode is generally different due to the influence of the microloading effect, the difference between the dimension of the gate electrode in the lithography process and the dimension in the etching process ( Dimension conversion difference,
The CD loss) is also often different, and may deviate from the target dimension (target value). In this embodiment, the amount of impurities 5 to be implanted to form the source / drain regions is adjusted by an amount corresponding to the amount of deviation between the measured size (gate length) of the gate electrode 4 and the target value. Dopant 1 in the substrate. That is, when the measured size of the gate electrode 4 is smaller than the target value, the amount of the impurities 5 is reduced in the impurity implantation step of FIG. 1B, and the impurities formed by the annealing of FIG. Intrusion of the diffusion layer 6 under the gate electrode 4 is suppressed. Further, when the size of the gate electrode 4 is larger than the target value, the impurity 5 is added in the impurity implantation step of FIG.
Is increased to promote the entry of the impurity diffusion layer 6 formed by the annealing in FIG. 1C into the area under the gate electrode 4.

As described above, according to this embodiment, the implantation amount of the impurity 5 is adjusted according to the processing size of the gate electrode 4 to control the entry of the impurity diffusion layer 6 under the gate electrode 4 due to annealing. Then, the effective gate length is always kept constant regardless of the processing size of the gate electrode 4,
Desired transistor characteristics can be obtained. In this embodiment, the effective gate length is stabilized by the implantation amount of the impurity 5. However, the implantation amount of the impurity 5 is kept constant and the temperature of the annealing performed after the implantation of the impurity 5 and The same effect can be obtained by adjusting the time. That is, when the measured size of the gate electrode 4 is smaller than the target value, the annealing temperature is lowered or the time is shortened to reduce the gate electrode 4 of the impurity diffusion layer 6.
If the size of the gate electrode 4 is larger than the target value, the temperature of annealing is increased or the time is lengthened to promote the entry of the impurity diffusion layer 6 below the gate electrode 4. You can do it.

[0012]

As described above, according to the method of manufacturing a semiconductor device of the present invention, when the measured value of the gate length is larger than the target value, the ion implantation amount of the impurities for forming the source / drain regions is increased and the measured value is increased. Is smaller than the target value, the ion implantation amount of the impurities is reduced, or when the measured gate length is larger than the target value, the heat treatment condition for forming the impurity diffusion layer to be the source / drain region is set to the impurity diffusion. The heat treatment condition is set so that the diffusion of impurities becomes small when the measured value is smaller than the target value, so that the effective gate length is always kept constant regardless of the processing size of the gate electrode. Therefore, desired transistor characteristics can be obtained.

[Brief description of drawings]

1A to 1D are cross-sectional views in order of the steps in a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[Explanation of symbols]

 1 semiconductor substrate 2 insulating film for element isolation 3 gate oxide film (gate insulating film) 4 gate electrode 5 impurities 6 impurity diffusion layer

Claims (2)

[Claims] 1. A gate electrode is formed on a semiconductor substrate via a gate insulating film, impurities for forming source / drain regions are ion-implanted on the surface of the semiconductor substrate by using the gate electrode as a mask, and then heat treatment is performed. A method of manufacturing a semiconductor device, wherein the impurity is diffused to form an impurity diffusion layer serving as the source / drain region, wherein a gate length is measured after forming the gate electrode, and the measured value is larger than a target value. Sometimes, the ion implantation amount of the impurity is increased, and when the measured value is smaller than the target value, the ion implantation amount of the impurity is reduced. 2. A gate electrode is formed on a semiconductor substrate via a gate insulating film, impurities for forming source / drain regions are ion-implanted on the surface of the semiconductor substrate using the gate electrode as a mask, and then heat treatment is performed. A method of manufacturing a semiconductor device, wherein the impurity is diffused to form an impurity diffusion layer serving as the source / drain region, wherein a gate length is measured after forming the gate electrode, and the measured value is larger than a target value. Sometimes, the heat treatment condition for forming the impurity diffusion layer is set so that the diffusion of the impurity becomes large, and when the measured value is smaller than the target value, the heat treatment condition is set so that the diffusion of the impurity becomes small. And a method for manufacturing a semiconductor device.