JPH09307077A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) Abstract: A semiconductor device having high electrical reliability and high integration is manufactured. A first material film for forming a first conductive portion is formed on an interlayer insulating film having a plurality of contact portions formed thereon.
Then, a columnar pattern 15 is formed on the first material film 14a and at a position directly above each of the plurality of contact portions 13.
To form Then, the second material film 16a for forming the second conductive portion is formed on the first material film 14a so as to cover the columnar pattern 15.
To form Then, a sidewall 17 is formed on the sidewall surface of the second material film 16a formed along the sidewall of the columnar pattern 15, and the sidewall 17 is used as a mask.
The first material film 14a and the second material film 16a are etched until the upper surface of the columnar pattern 15 is exposed and the interlayer insulating film 11 at the position 15 between the columnar patterns is exposed. Then, the sidewall 17 and the columnar pattern 15 are removed to obtain the storage node electrode 1 including the first conductive portion 14 and the second conductive portion 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device applied to the manufacture of a semiconductor integrated circuit in which electrodes or wirings are formed directly above respective contact parts formed on a conductive layer. Is.

[0002]

2. Description of the Related Art Some semiconductor devices are constructed by forming electrodes or wirings at positions immediately above respective contact portions formed on a conductive layer. For example, if an electrode is formed immediately above the contact part,
Dynamic RAM using that electrode as a storage node electrode
A memory cell (hereinafter referred to as DRAM) is known.

In the conventional method of manufacturing a semiconductor device, for example, in the case of forming a cylindrical (cylinder-type) storage node electrode, first, as shown in FIG. A plurality of contact portions 53, which are so-called plugs, are formed so as to be electrically connected to the conductive layer 50 and face the interlayer insulating film 51. The interlayer insulating film 51 is formed by stacking, for example, a silicon oxide (SiO ₂ ) layer 51a and a silicon nitride (SiN) layer 51b in this order on the conductive layer 50, and the contact portion 53 has the interlayer insulating film 5 formed thereon.
Each of the plurality of contact holes 52 formed in No. 1 is formed by embedding polysilicon (Poly-Si) containing impurities, for example. Next, a first material film 54a made of a Poly-Si film containing impurities is formed on the interlayer insulating film 51 so as to cover the upper surface of the contact portion 53, and a SiO ₂ film 55a is formed on the first material film 54a. .

Next, as shown in FIG. 3B, the SiO ₂ film 55a is patterned by lithography and etching, and then the first material film 54a is processed. As a result, the first conductive portion 5 made of the first material film 54a is provided directly above each of the plurality of contact portions 53.
4 is continuously formed on the contact portion 53,
A columnar pattern 56 including the first conductive portion 54 and the SiO ₂ pattern 55 is formed. The first conductive portion 54 becomes a portion that constitutes the bottom of the storage node electrode that is finally formed.

Next, as shown in FIG. 3 (c), the interlayer insulating film 51 is covered with a columnar pattern 56 and contains a Po containing impurity.
A second material film 57a made of a ly-Si film is formed, and subsequently, as shown in FIG. 3D, the second material film 57a is etched back to be formed on the sidewall surface of the columnar pattern 56 from the sidewall. The second conductive portion 57 is formed so as to be continuous with the first conductive portion 54. The second conductive portion 57 becomes a portion that constitutes the sidewall portion of the storage node electrode that is finally obtained. afterwards,
As shown in FIG. 3E, the SiO ₂ pattern 5 of the columnar patterns 56 was subjected to the cleaning treatment using hydrofluoric acid.
5 is removed by etching. As a result, the first conductive portion 5 is provided at the position directly above each of the plurality of contact portions 53.
A cylindrical storage node electrode 58 including the fourth conductive portion 57 and the second conductive portion 57 is obtained.

Further, in the conventional method of manufacturing a semiconductor device, when the wiring is formed directly above each of the plurality of contact portions formed on the conductive layer, first, as shown in FIG. 4A, the conductive layer 60 is formed. A plurality of contact portions 63 are formed in the upper interlayer insulating film 61 made of, for example, a SiO ₂ film so as to be electrically connected to the conductive layer 60 and face the interlayer insulating film 61. Each contact portion 63 is composed of a plug formed by filling a contact hole 62 formed in the interlayer insulating film 61 with a conductive material. Then, a barrier metal layer 64 is formed on the interlayer insulating film 61 so as to cover the upper surface of the contact portion 63.
a and the wiring material film 64b are laminated in this order. Subsequently, the barrier metal layer 64a and the wiring material film 64b are patterned by lithography and etching to form the wiring 64 at positions immediately above each of the plurality of contact portions 63, as shown in FIG. 4B.

By the way, FIGS. 3 and 4 show the formation of the storage node electrode 58 and the formation of the wiring 64 under ideal conditions in which there is no variation in etching processing or misalignment during lithography. Actually, the above-mentioned processing variations, misalignment, and the like occur when forming them. Therefore, conventionally, the diameter of the storage node electrode 58 and the width of the wiring 64 are formed to be larger than the diameters of the contact portions 53 and 63 so that the storage node electrode 58 and the wiring 6 have a so-called covering state.
4 are formed.

[0008]

However, in order to achieve high integration of semiconductor devices, which has been actively promoted in recent years, it is necessary to reduce the amount of covering of electrodes or wiring contact portions. That is, in the above-described conventional method for manufacturing a semiconductor device, the pitch of electrodes and wirings is limited by the lithographic process when patterning electrodes and wirings, and therefore the presence of the overcoat is a major factor that delays the reduction of these pitches. This is because they are one. Therefore, in terms of layout, it is desired that there be no cover. However, if the amount of coating is small, the above-mentioned variation in etching processing, misalignment during lithography, and the like are likely to occur, which causes the following problems.

For example, in the lithography in the step shown in FIG. 3B, misalignment of the resist pattern formed on the SiO ₂ film 55a with respect to the contact portion 53 is likely to occur. In this case, the first conductive portion 54 of the storage node electrode 58 is deviated from the contact portion 53 by the subsequent etching using the resist pattern as a mask and is covered with the resist pattern as shown in FIG. 5A. The uncovered contact portion 53 is dug to cause the trenching 70. Also, in the lithography and etching in the step shown in FIG. 4B, similarly, processing variations and misalignment are likely to occur, and in this case also, the wiring 64 is displaced from the contact portion 63 as shown in FIG. 5B. The trenching 70 occurs in the contact portion 63.

When such trenching 70 occurs,
When the insulating film is further formed on the storage node electrode 58 and the wiring 64, the insulating material is not completely filled in the trenching 70, and as a result, a void is generated in the insulating film and the withstand voltage of that portion is deteriorated. It will end up. Further, during the cleaning process using hydrofluoric acid performed after the trenching 70 is generated, the cleaning liquid enters from the trenching 70 portion and etches the interlayer insulating films 51 and 61 around the cleaning liquid. The etching progresses to the conductive layers 50 and 60 below the insulating films 51 and 61, resulting in a short circuit. Further, when the storage node electrode 58 is formed so as to deviate from the contact portion 53, the contact area between the contact portion 53 and the storage node electrode 58 decreases, so that the contact resistance increases or the contact portion 53 and the storage node electrode 58 increase. The current concentrates on the connection portion with 58, and the electrical reliability of this portion is reduced. Such a problem similarly occurs when the wiring 64 is formed so as to be displaced from the contact portion 63.

In order to prevent the above-mentioned inconvenience, it is necessary to set a large amount of coating on the storage node electrode 58 and the wiring, which is against the above-mentioned high integration of the semiconductor device. Become. For example, in the 256 MDRAM and later generations, which are being developed in recent years, it becomes difficult to secure a distance for separating the storage node electrodes 58 when the amount of covering is increased, and the memory cell size must be increased. It will end up. Therefore, it is desired to develop a technique capable of preventing the occurrence of trenching and reducing the pitch of electrodes and wirings, whereby a semiconductor device having high electrical reliability and high integration can be manufactured.

Further, in the conventional method of forming the storage node electrode 58 shown in FIG. 3, the second material film 57a is formed in the three directions of upward, obliquely upward and lateral in the etch back step shown in FIG. 3 (d). Received an ionic species attack. Therefore, the second conductive portion 57, which is the side wall portion of the storage node electrode 58, is greatly diminished in the height direction, the height controllability deteriorates, and the height of the storage node electrode 58 varies. If the height of the storage node electrode 58 varies, the surface area varies for each storage node electrode 58, and the amount of accumulated charges changes, resulting in a favorable DR.
The AM characteristic cannot be maintained. Further, this variation in the height of the storage node electrode 58 causes an increase in the etching amount when the second material film 57a and the first material film 54a are simultaneously etched by the etch back of FIG. 3D. It occurs even more. Therefore, conventionally, as shown in FIG. 3B, the first material film 54a is processed following the pattern processing of the SiO ₂ 55a, but this also does not solve the above-mentioned problem.

Further, in the etch back step of FIG. 3D, the second material film 57a is attacked by ionic species from three directions, so that the tip of the obtained second conductive portion 57 becomes an acute angle. As a result, after the storage node electrode 58 is formed,
Insufficient film attachment of the capacitor insulating film formed on this upper layer,
Insulation failure may occur due to electric field concentration.

[0014]

A method for manufacturing a semiconductor device according to a first aspect of the present invention for achieving the above object is a first method.
In the step, a first material film for forming the first conductive portion is formed on the interlayer insulating film on which a plurality of contact portions are formed, which is continuous with and covers the contact portion facing the interlayer insulating film,
Next, a columnar pattern is formed on the first material film and directly above each of the plurality of contact portions. Then the second
In the step, a second material film for forming the second conductive portion is formed on the first material film so as to cover the columnar pattern. Then, in the third step, the second layer formed along the sidewall of the columnar pattern is formed.
A sidewall made of a material having an etching selection ratio with respect to the first material film and the second material film is formed on the sidewall surface of the material film. Then, in a fourth step, the first material film and the second material film are etched using the sidewalls as a mask until the upper surfaces of the columnar patterns are exposed and the interlayer insulating film between the columnar patterns is exposed. Then, in a fifth step, the sidewall and the columnar pattern are removed by etching to obtain an electrode composed of the first conductive portion and the cylindrical second conductive portion continuous with the first conductive portion.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein in the first step, a contact portion facing the interlayer insulating film is continuously formed on the interlayer insulating film having a plurality of contact portions formed thereon. To form a first material film for forming the first conductive portion, and then form a second material film for forming the second conductive portion on the first material film. Next, in a second step, the second material film is etched to form the second conductive portion at the position directly above each of the plurality of contact portions. Subsequently, in a third step, a sidewall made of a material having an etching selection ratio with the first material film is formed on the sidewall surface of the second conductive portion. Then, in the fourth step, using the sidewall as a mask, the first insulating layer is exposed until the interlayer insulating film at the position between the second conductive portions is exposed.
The material film is etched to form a first conductive portion immediately below each second conductive portion, and a wiring including the first conductive portion and a second conductive portion continuous with the first conductive portion is obtained.

According to the first aspect of the present invention, the first material film and the first material film are exposed until the upper surface of the columnar pattern formed for each contact portion is exposed and the interlayer insulating film between the columnar patterns is exposed using the sidewall as a mask. Since the second material film is etched, the first material film and the second material film are separated for each columnar pattern, that is, for each contact portion, and at the same time for each contact portion, a first conductive portion made of the first material film is formed. A cylindrical second conductive portion made of the second material film is obtained. In addition, since the first material film and the second material film existing directly under the sidewalls remain without being etched, the first conductive portion and the second conductive portion are covered with the contact portion in a self-aligned manner. Further, since the upper portion of the side wall of the second material film is covered with the side wall and the columnar pattern during etching using the side wall as a mask,
During the etching, the obliquely upward and lateral components of the ion species with respect to the side wall of the second material film are blocked. Therefore, the second material film is not attacked by ionic species from three directions as in the conventional case, but is only attacked by ionic species from above. Furthermore, since the second material film is only attacked by ionic species from above, the shape of the tip of the obtained second conductive portion does not form an acute angle.

According to the third aspect of the invention, the first material film is etched until the interlayer insulating film at the position between the second conductive portions is exposed using the sidewall as a mask. That is, a wiring is obtained which is separated for each contact portion and which is made of the first conductive portion and the second conductive portion made of the first material film for each contact portion. Moreover, since the first material film existing immediately below the sidewall remains without being etched, the first conductive portion is covered with the first conductive portion in a self-aligned manner.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings. In addition,
In the drawings used to describe the present embodiment, for the sake of simplicity, the element isolation, transistors and the like in the lower layer of the contact portion of the present invention are omitted. FIG. 1 is an explanatory view showing a first embodiment of the present invention in the order of steps. In particular, the electrode forming step which is the feature of the invention of claims 1 and 2 is
It is a figure showing an example applied to formation of a cylindrical storage node electrode of a memory cell.

In this embodiment, in order to form a storage node electrode, first, as shown in FIG.
A first insulating film 11a and a second insulating film 12a are laminated in this order on the conductive layer 10 made of a substrate by, for example, a chemical vapor deposition method (hereinafter, referred to as a CVD method), and the first insulating film 11a and the second insulating film 12a are stacked in this order.
The interlayer insulating film 11 including the insulating film 11a and the second insulating film 11b is obtained. The second insulating film 11b is provided as a stopper layer when the columnar pattern 15 described later is wet-etched. Here, for example, the first insulating film 1
1a is a SiO ₂ film, and the second insulating film 11b is a SiN film.

Next, a plurality of contact holes 12 reaching the conductive layer 10 are formed in the interlayer insulating film 11 by lithography and anisotropic etching. Then, for example, C
A conductive material film, for example, a Poly-Si film containing impurities is formed on the interlayer insulating film 11 by the VD method so as to fill each contact hole 12. Subsequently, the Poly-Si film is removed by etching back or the like until the interlayer insulating film 11 is exposed, so that the Poly-Si film facing the interlayer insulating film 11 is exposed.
The contact portion 13 made of a Si plug is formed. At this time, the so-called plug loss caused by the formation of the contact portion 13 is set to be equal to or less than the film thickness of the second insulating film 11b.

Next, as shown in FIG. 1B, for example, CVD
By the method, a first material film 14a is formed on the interlayer insulating film 11 so as to be continuous with and cover the plurality of contact portions 13. The first material film 14a is a film for forming a first conductive portion that will be the bottom of the storage node electrode to be finally obtained.
Here, the first material film 14a is formed of, for example, a Poly-Si film containing impurities. Then, a material film 15a for forming a columnar pattern described later is formed on the first material film 14a. At this time, the material film 15a is formed of the same material as the sidewall to be formed as described later, for example, a SiO ₂ film.

Next, by patterning only the material film 15a by lithography and anisotropic etching, as shown in FIG. 1C, a plurality of contact portions 13 are formed.
A columnar pattern 15 is formed at a position directly above.
Then, the second material film 16a is deposited on the first insulating film 14a so as to cover each columnar pattern 15 by, for example, the CVD method. The second material film 16a is a film for forming a second conductive portion which will be a sidewall portion of the storage node electrode to be finally obtained.
Here, the second material film 16a is formed of Poly-Si containing impurities.
It is formed with a film.

Next, as shown in FIG. 1D, the second material film 16a formed along the sidewall of each columnar pattern 15 is formed.
Sidewalls 17 are formed on the side wall surfaces of the. At this time, the side wall 17 is formed of a material having an etching selection ratio with respect to the first material film 14a and the second material film 16a during anisotropic etching in a step shown in FIG. Here, for example, SiO 2 is formed on the second material film 16a.
After depositing the ₂ film, is etched back by anisotropic etching of the SiO ₂ film to form a side wall 17 made of SiO ₂ film.

Then, etching is performed using the sidewalls 17 as a mask. As described above, the first material film 14
a and the second material film 16a, since the sidewalls 17 are formed of a SiO ₂ film having an etching selection ratio, the first material film 14a and the second material film 1 are formed in this step.
6a is etched back. In this step, the upper surface of the columnar pattern 15 is exposed and the columnar pattern 15 is exposed.
The first material film 14 is formed until the interlayer insulating film 11 at the interposition is exposed.
a and the second material film 16a are etched back.

As a result, as shown in FIG. 1E, the first material film 14a and the second material film 16a can be separated for each columnar pattern 15, and at the same time, the first material film for each columnar pattern 15 can be separated. A first conductive portion 14 composed of 14a,
The cylindrical second conductive portion 16 made of the second material film 16a can be obtained. That is, since the columnar pattern 15 is formed directly above each contact portion 13, the first conductive portion 14 and the second conductive portion 16 can be formed separately for each contact portion 13. Furthermore, in the etching using the sidewall 17 as a mask, the first material film 14a and the second
Since the material film 16b remains without being etched, the first conductive portion 14 and the second conductive portion 16 can be formed in a self-aligned manner to cover the contact portion 13 by the thickness of the sidewall 17.

Thereafter, as shown in FIG. 1F, the sidewall 1 is formed by using the second insulating film 11b as a stopper layer by, for example, wet etching using a hydrofluoric acid cleaning solution.
7 and the columnar pattern 15 are removed. Since the columnar pattern 15 is made of the same material as the sidewall 17,
By this wet etching, the columnar pattern 15 and the sidewalls 17 can be removed together. Through the above steps, a plurality of cylindrical storage node electrodes 1 each including the first conductive portion 14 and the cylindrical second conductive portion 16 are formed in a state of being continuous with the contact portion 13 immediately therebelow.

As described above, according to the above-described embodiment, by using the sidewalls 17 as a mask, the covering of the contact portions 13 can be formed in a self-aligned manner without using lithography, and at the same time, the storage node can be formed for each contact portion 13. The electrode 1 can be formed separately. As a result, it is possible to prevent the occurrence of trenching and the reduction of the contact area of the storage node electrode 1 with respect to the contact portion 13 due to the formation of the cover. Can also be shortened. In addition, the pitch of the contact portions 13 can be reduced accordingly. Therefore,
Since it is possible to prevent a decrease in electrical reliability in the vicinity of the contact portion 13 and to reduce the size of the DRAM memory cell, according to this method, a semiconductor device having high electrical reliability and high integration is achieved. Can be manufactured.

Further, in the above embodiment, the sidewall 1
The second material film 1 during etching using 7 as a mask
Since the upper portion of the side wall of 6a is covered and protected by the side wall 17 and the columnar pattern 15, the components in the obliquely upward and lateral directions of the ion species with respect to the side wall of the second material film 16a are blocked during the etching. It Therefore, the second material film 16a is not attacked by ionic species from three directions as in the conventional case, but is only attacked by ionic species from above, so that the height of the obtained second conductive portion 16 is increased. It is possible to suppress the reduction in the depth direction. Therefore, the controllability of the height of the storage node electrode 1 is good, and the storage node electrode 58 having a substantially uniform height can be obtained.
A semiconductor device having AM characteristics can be manufactured.

Furthermore, since the second material film 16a is only attacked by ionic species from above, the tip shape of the second conductive portion 16 obtained as shown in FIG. 1 (f) does not have an acute angle. Therefore, after the storage node electrode 1 is formed, it is possible to prevent filming failure of the capacitor insulating film formed in the upper layer and insulation failure due to electric field concentration, so that it is possible to obtain a capacitor insulating film having high electrical reliability. .

In the above embodiment, the poly-Si film formed on the interlayer insulating film 11 is etched in the step shown in FIG. 1A to form the contact portion 13 made of a poly-Si plug. In the process shown in FIG. 1B, the contact portion 13 is covered on the interlayer insulating film 11 to cover Poly-S.
Although the first material film 14a made of the i film is formed, the contact portion 13 and the first material film 14a can be simultaneously formed by this etching if the above etching can be performed with good controllability. In this case, the number of steps can be reduced as compared with the above embodiment.

In the above embodiment, the case where the columnar pattern and the side wall are formed of the SiO ₂ film has been described, but the side wall is formed of a material having an etching selection ratio with respect to the first material film and the second material film. It is sufficient that the columnar pattern and the sidewall are formed of a material that can be selectively removed at the end, and the material is not limited to the above materials. For example, boron-phosphosilicate glass (BP
It is also possible to use SiO ₂ containing impurities such as SG) and phosphosilicate glass (PSG).

Next, a second embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to FIG. The second embodiment is an embodiment of a wiring forming process which is a feature of the invention of claims 3 and 4. To form the wiring in this embodiment, first, as shown in FIG. 2A, an interlayer insulating film 21 made of a SiO ₂ film is formed on the conductive layer 20 made of a Si substrate or a lower wiring by, for example, a CVD method.
Then by lithography and anisotropic etching,
A plurality of contact holes 22 reaching the conductive layer 20 are formed in the interlayer insulating film 21.

After that, a conductive film for an adhesion layer is formed on the interlayer insulating film 11 by, for example, a CVD method so as to cover the inner surface of each contact hole 22, and then the contact layer 22 is filled with the conductive film. A conductive material film is formed on the film for use. The film for the adhesion layer is made of, for example, titanium nitride (TiN) or a laminated body of TiN and titanium (Ti), and the conductive material film above it is made of, for example, tungsten (W).

Next, the film for the adhesion layer and the conductive material film are removed by etching back or the like until the upper surface of the interlayer insulating film 21 is exposed, so that the W plug is inserted into the contact hole 22 via the adhesion layer 23a. Has a structure in which
Further, the contact portion 23 facing the interlayer insulating film 21 is formed. Next, as shown in FIG. 2B, the first material film 2 is continuously formed on the interlayer insulating film 21 and covers the plurality of contact portions 23 by, for example, a CVD method or a sputtering method.
4a is formed. The first material film 24a is a barrier metal film for forming the first conductive portion of the wiring to be finally obtained, and here is formed of the first layer 241 made of a Ti film and the TiN film on the interlayer insulating film 21. The first material film 24a is formed by laminating the second layer 242 in this order.

Subsequently, a second material film 25a for forming the second conductive portion of the wiring finally obtained is formed on the first material film 24a by, for example, the CVD method or the sputtering method. In this embodiment, a conductive material film 251 is formed by laminating a first layer 251a and a second layer 251b which is an antireflection film in this order on the first material film 24a,
A protective film 252 made of a material having an etching selection ratio with the first material film 24a is formed on the upper layer. Then, the second material film 2 including the conductive material film 251 and the protective film 252
5a is formed. Further, here, for example, the conductive material film 25
The first layer 251a of No. 1 is aluminum (Al) -copper (C
u) alloy film, second layer 251b is TiN film, protective film 25
2 is formed of a SiO ₂ film.

Next, the second material film 25b is etched by lithography and anisotropic etching to obtain the structure shown in FIG.
As shown in (c), a pattern of a protective film 252 (hereinafter referred to as a protective film pattern) 252a and a pattern of a conductive material film 251 (hereinafter referred to as a conductive material film pattern) are provided directly above respective contact portions 23. ) And the second conductive portion 25 is formed. Next, the first material film 24 is formed on the first material film 24a so as to cover the second conductive portion 25.
A film made of a material having an etching selection ratio to that of a is formed, and then this film is etched back by anisotropic etching to form a sidewall on the side wall surface of the second conductive portion 25 as shown in FIG. 26 is formed. Here, the side wall 26 is formed of the same SiO ₂ film as the protective film 252.

Then, etching is performed using the sidewalls 26 and the protective film pattern 252a as a mask. As described above, since the side wall 26 and the protective film pattern 252a are formed of the SiO ₂ film having an etching selection ratio with the first material film 24a, the first material film 24a is etched back in this step. Further, in this step, the first material film 24a is etched back until the upper surface of the interlayer insulating film 21 located between the first material film 24a and the second conductive portion 25 is exposed. As a result, the first conductive portions 24 can be formed immediately below the respective second conductive portions 25, that is, the first material film 24a can be separated for each contact portion 23, and the first conductive portion 24 can be formed for each contact portion 23. , The second conductive portion 25
It is possible to form the wiring 2 composed of

Further, in the etching using the side wall 26 and the protective film pattern 252a as a mask, the first material film 24a existing immediately below the side wall 26 remains without being etched, so that the first conductive portion 24 and the contact portion 23 are not etched. It is possible to form a cover corresponding to the thickness of the sidewall 26 in a self-aligned manner. Through the above steps, the plurality of wirings 2 each including the first conductive portion 24 and the second conductive portion 25 are formed in a state of being continuous with the contact portion 23 immediately thereunder.

As described above, according to the above-described embodiment, by using the sidewall 26 and the protective film pattern 252a as a mask, the contact portion 23 can be covered in a self-aligned manner without using lithography, and the contact portion can be formed. The wiring 2 can be formed separately for each 23. As a result, the formation of the cover can prevent the occurrence of trenching and the reduction of the contact area of the wiring 2 with respect to the contact portion 23. Further, the pitch of the wiring 1 which was conventionally limited by lithography can be narrowed as compared with the conventional one. it can. In addition, the pitch of the contact portions 23 can be reduced accordingly. Therefore, the second
Also in the embodiment, it is possible to manufacture a highly integrated and highly integrated semiconductor device in the vicinity of the contact portion 23.

In the second embodiment, the second conductive portion 25
Since the overburden is formed low, the overburden hardly affects the capacitance between the wirings 2. In addition, in the second embodiment, the protective film pattern and the sidewall are made of Si.
Although the O ₂ film is used, the protective film pattern and the sidewall may be formed of any material as long as it has an etching selectivity with the first material film forming the first conductive portion. For example, it may be formed of a SiN film, or may be formed of a conductive material such as a metal material.

[0041]

As described above, according to the method of manufacturing the semiconductor device of the first aspect of the present invention, the first contact is formed for each contact portion by etching using the sidewall as a mask.
Since the electrode composed of the conductive portion and the second conductive portion can be separately formed, and the covering on the contact portion can be formed in a self-aligned manner, it is possible to prevent the occurrence of trenching, the reduction of the contact area of the electrode with respect to the contact portion, and the like. Then, it is possible to reduce the pitch of electrodes and contact portions, which is limited by lithography, compared to the conventional case. Therefore, it is possible to prevent a decrease in electrical reliability in the vicinity of the contact portion, and to reduce the cell size if the electrode is a storage node electrode of a DRAM memory cell. It is possible to manufacture a highly integrated semiconductor device having high reliability. Further, during etching using the sidewall as a mask, the upper portion of the side wall of the second material film is protected by the sidewall and the columnar pattern, and the second material film can be etched only by the ion species from above. It is possible to obtain the second conductive portion whose tip shape is not an acute angle. Therefore, the controllability of the height of the electrode is good, and an electrode having a substantially uniform height can be obtained, so that a semiconductor device having good electrical characteristics can be manufactured. Further, if this electrode is a storage node electrode, it is possible to prevent filming failure of the capacitor insulating film formed on this layer and insulation failure due to electric field concentration, so that it is possible to obtain a capacitor insulating film having high electrical reliability. Become.

According to the third aspect of the invention, the first contact is formed for each contact portion by etching using the sidewall as a mask.
It is possible to obtain a wiring including a conductive portion and a second conductive portion,
Further, since the cover for the contact portion can be formed in the first electrode portion in a self-aligned manner, it is possible to prevent the occurrence of trenching, the reduction of the contact area of the electrode with respect to the contact portion, and the like as in the invention of claim 1, and the wiring and the contact. The pitch of the parts can be reduced as compared with the conventional one. Therefore, also by this method, a semiconductor device having high electrical reliability and high integration can be manufactured.

[Brief description of drawings]

1A to 1F are explanatory views showing a first embodiment of a method for manufacturing a semiconductor device according to the present invention in the order of steps,
It is a figure which shows one Embodiment of the formation method of the electrode which the invention of Claims 1 and 2 characterized especially.

2 (a) to 2 (d) are explanatory views showing a second embodiment of a method for manufacturing a semiconductor device according to the present invention in the order of steps, and particularly formation of wiring characterized by the inventions of claims 3 and 4. FIG. FIG. 6 illustrates an embodiment of a method.

3A to 3E are explanatory views (No. 1) showing a conventional method for manufacturing a semiconductor device in the order of steps, showing a method for forming a storage node electrode.

4A and 4B are explanatory views (No. 2) showing a conventional method for manufacturing a semiconductor device in the order of steps, showing a method for forming wiring.

5 (a) and 5 (b) are views for explaining the problems of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Storage node electrode 2 Wiring 10, 20 Conductive layer 11, 12 Interlayer insulating film 13, 23 Contact part 14, 24 1st conductive part 14a, 24a 1st material film 15 Columnar pattern 16, 25 2nd conductive part 16a, 25a Second material film 17, 26 Side wall 251 Conductive material film 251c Conductive material film pattern 252 Protective film 252a Protective film pattern

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical indication H01L 21/822

Claims (4)

[Claims] 1. A plurality of contact portions are formed on an interlayer insulating film on a conductive layer so as to be electrically connected to the conductive layer and face the interlayer insulating film, and the contact portion is formed on the interlayer insulating film and on the plurality of contacts. An electrode composed of a first conductive portion and a cylindrical second conductive portion formed on the first conductive portion and continuous with the first conductive portion is provided at positions immediately above the contact portions, respectively, at contact portions directly below the electrodes. A method of manufacturing a semiconductor device which is formed continuously, wherein the first conductive portion is continuous with and covers a contact portion facing the interlayer insulating film on the interlayer insulating film on which the plurality of contact portions are formed. A first step of forming a first material film for formation, and then forming a columnar pattern on the first material film and at a position directly above each of the plurality of contact portions; and a step of covering the columnar pattern with the first step. Second on one material film
A second step of forming a second material film for forming a conductive portion, and the first material film and the second material film on the side wall surface of the second material film formed along the side wall of the columnar pattern. And a third step of forming a sidewall made of a material having an etching selection ratio; and using the sidewall as a mask, the upper surface of the columnar pattern is exposed and the interlayer insulating film at the position between the columnar patterns is exposed. A fourth step of etching the first material film and the second material film, and removing the sidewalls and the columnar pattern by etching to form the electrode composed of the first conductive portion and the second conductive portion. And a fifth step for obtaining the same. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the columnar pattern is made of the same material as the sidewall. 3. A plurality of contact portions are formed on the interlayer insulating film on the conductive layer so as to be electrically connected to the conductive layer and face the interlayer insulating film, and the contact portion is formed on the interlayer insulating film and on the plurality of contacts. The first conductive portion and the first conductive portion at positions immediately above the respective portions.
A method of manufacturing a semiconductor device, comprising: forming a wiring formed on a conductive portion and including a second conductive portion which is continuous with the first conductive portion, in a continuous manner at a contact portion directly under the wiring, respectively. A first material film for forming the first conductive portion is formed on the inter-layer insulating film having the portion formed thereon and is continuous with and covers the contact portion facing the inter-layer insulating film, and then on the first material film. A first step of forming a second material film for forming the second conductive portion; and a step of etching the second material film to form the second conductive portion at a position directly above each of the plurality of contact portions. 2 steps, a 3rd step of forming a sidewall made of a material having an etching selection ratio with the first material film on the side wall surface of the second conductive portion, and the second conductive film using the sidewall as a mask. Intersection of the section The first material film is etched until the edge film is exposed, the first conductive portions are formed immediately below the respective second conductive portions, and the wiring including the first conductive portions and the second conductive portions is formed. And a fourth step for obtaining the same. 4. The second material film formed in the first step,
The conductive material film is formed on the first material film, and the protective film is formed on the conductive material film and is made of a material having an etching selection ratio with the first material film. The conductive film is formed in the second step. The second conductive portion is composed of a pattern made of the conductive material film and a pattern made of the protective film, and the wiring formed in the fourth step protects the second conductive portion together with the sidewall. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the film pattern is also formed by etching using the mask as a mask.