JPH0620102B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JPH0620102B2 JPH0620102B2 JP12339687A JP12339687A JPH0620102B2 JP H0620102 B2 JPH0620102 B2 JP H0620102B2 JP 12339687 A JP12339687 A JP 12339687A JP 12339687 A JP12339687 A JP 12339687A JP H0620102 B2 JPH0620102 B2 JP H0620102B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- contact hole
- wiring
- insulating film
- electrode layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は半導体装置の配線層形成を改善した半導体装置
及びその製造方法に関するもので、特にコンタクトホー
ルと配線又は電極層の間隔が微細化されている超ＬＳＩ
デバイスに使用されるものである。The present invention relates to a semiconductor device in which the formation of a wiring layer of a semiconductor device is improved and a method for manufacturing the same, and more particularly to a contact hole and a wiring or an electrode layer. VLSI with finer spacing
It is used for devices.
（従来の技術） 従来、超ＬＳＩのような微細なデバイスではコンタクト
ホールと下層の配線または電極層の間隔は、フォトリソ
グラフィー工程の合わせ精度によって決定されており、
ある程度以上は小さくできない。特に下層の配線又は電
極層の厚さが厚い場合やコンタクトホールの大きさが小
さい場合、コンタクトホールのアスペクト比が大きくな
り、その為コンタクトの大きさを大きくしないと、その
上に形成される金属配線層が段切れを起こす問題が発生
する場合があり、コンタクトホールは可能な限り大きく
する必要がある。その場合、コンタクトホールと下層電
極層間の距離が近接し、コンタクトホール開口後形成す
る上部配線層と下層配線層がショートする危険性が増大
するので、コンタクトホールと下層電極層の間隔をあま
り小さくすることができない。(Prior Art) Conventionally, in a fine device such as a VLSI, the distance between the contact hole and the lower wiring or electrode layer is determined by the alignment accuracy of the photolithography process.
It cannot be made smaller than a certain amount. In particular, when the underlying wiring or electrode layer is thick or the size of the contact hole is small, the aspect ratio of the contact hole becomes large. Therefore, unless the size of the contact is increased, the metal formed on it There may be a problem that the wiring layer is disconnected, and the contact hole needs to be as large as possible. In that case, the distance between the contact hole and the lower electrode layer becomes close, and the risk of short-circuiting between the upper wiring layer and the lower wiring layer formed after opening the contact hole increases, so the distance between the contact hole and the lower electrode layer is made too small. I can't.
（発明が解決しようとする問題点） 上記問題を解決する手段として、コンタクトホール形成
後コンタクトホール側面に絶縁膜を形成し、たとえコン
タクトホール開口時に下層電極層とコンタクトホールが
近接しても、後で形成する上層金属電極層と下層電極層
がショートしないようにする方法が考えられる。しかし
上記絶縁膜には、両極性で高い電解強度と低欠陥密度さ
らに薄膜化が要求される。上記絶縁膜が厚いとコンタク
トホールの大きさが小さくなってしまい、微細デバイス
に使用できない。例えば通常のＣＶＤ法で堆積させるＳ
ｉＯ２層では、電界強度も低く、欠陥密度が多いので、
十分な信頼性は得られず当然薄膜化も達成できない。(Problems to be Solved by the Invention) As means for solving the above problems, after forming a contact hole, an insulating film is formed on the side surface of the contact hole, and even if the lower electrode layer and the contact hole are close to each other when the contact hole is opened, A method of preventing a short circuit between the upper metal electrode layer and the lower electrode layer formed in step 1 can be considered. However, the above-mentioned insulating film is required to have high electrolytic strength in both polarities, low defect density, and further thinning. If the insulating film is thick, the size of the contact hole becomes small and it cannot be used for a fine device. For example, S deposited by a normal CVD method
Since the electric field strength is low and the defect density is high in the iO 2 layer,
Sufficient reliability cannot be obtained and, of course, thinning cannot be achieved.
本発明は、下層配線又は電極層と、コンタクトホール開
口後に形成する上部配線層との間に、薄くかつ信頼性の
高い絶縁膜を堆積させることにより、コンタクトホール
と下層配線又は電極層との間の距離をできるだけ短くし
て、素子の高集積化を達成するものである。According to the present invention, by depositing a thin and highly reliable insulating film between a lower wiring or an electrode layer and an upper wiring layer formed after opening a contact hole, the contact hole and the lower wiring or the electrode layer are separated from each other. The distance is shortened as much as possible to achieve high integration of the device.
［発明の構成］ （問題点を解決するための手段と作用） 本発明は、下層電極又は配線層を形成後、層間絶縁膜を
形成し、次に、この相関絶縁膜にコンタクトホールを開
口し、その後、上部の電極又は配線層を堆積する前に薄
膜のＳｉＯ２／Ｓｉ３Ｎ４／ＳｉＯ２又はＳｉ３Ｎ４／
ＳｉＯ２／Ｓｉ３Ｎ４の３層膜を堆積させる。上記コン
タクトホール底部の上記３層膜を除去した後、上層の電
極又は配線層を形成することによって、上記上層と下層
の配線又は電極層は、たとえコンタクトホール開口時に
コンタクトホールと下層電極層が非常に近接してしまっ
ていても、次に堆積する３層絶縁膜によって上部電極層
とは絶縁される。また上記３層絶縁膜は欠陥密度が低く
電界強度も大きいので、薄膜化が可能で、その為、コン
タクトホールの大きさが小さくなってしまうことも最小
限に抑制される。これによりコンタクトホールと下層電
極層の間隔は、従来よりも大幅に小さく設計できる為、
素子の高集積化が可能となるものである。[Structure of the Invention] (Means and Actions for Solving Problems) In the present invention, after forming a lower electrode or a wiring layer, an interlayer insulating film is formed, and then a contact hole is opened in this correlation insulating film. , Then thin film SiO 2 / Si 3 N 4 / SiO 2 or Si 3 N 4 / before depositing the upper electrode or wiring layer
Depositing a triple layer of SiO 2 / Si 3 N 4. By removing the three-layer film at the bottom of the contact hole and then forming an upper electrode or wiring layer, the upper and lower wiring or electrode layers have a contact hole and lower electrode layer Even if it is close to the upper electrode layer, it is insulated from the upper electrode layer by the three-layer insulating film deposited next. Further, since the three-layer insulating film has a low defect density and a high electric field strength, it can be thinned, and thus the size of the contact hole can be minimized. As a result, the distance between the contact hole and the lower electrode layer can be designed to be significantly smaller than before,
The device can be highly integrated.
（実施例） 以下図面を参照して本発明の一実施例を説明する。第１
図ないし第５図は同実施例の製造工程図であるが、これ
は本発明を、第一層目の電極層の高さが高いＥＰＲＯＭ
（紫外線消去型ＰＲＯＭ）に適用した場合の例である。
第１図はコンタクトホールを形成する前の一般的なＥＰ
ＲＯＭの断面図で、１はＰ形シリコン基板、２はＮ＋拡
散層で、３は２層ポリシリコンよりなるＥＰＲＯＭセル
（第一層目の電極・配線層に相当）、４は層間絶縁膜で
ある。その後コンタクトホール開口のためのフォトリソ
グラフィーを行う。第２図に示すようにレジスト５を塗
布し、フォトリソグラフィー工程によりレジスト５のパ
ターニングを行ない、ＲＩＥ（リアクティブ・イオン・
エッチング）法によりコンタクトホール６を開口する。
この場合、コンタクトホール６とポリシリコン３間の距
離が短いので、部分７でポリシリコン電極３の側面の絶
縁層が非常に薄くなっている。このまま第２層目（上
層）の例えばＡｌ配線層を堆積させれば当然そのＡｌ配
線層とポリシリコン電極３は絶縁膜中の欠陥等によりシ
ョートしてしまう確率が増す。そこで第３図に示すよう
に例えばＬＰＣＶＤ法（ロープレッシャＣＶＤ法）によ
りＳｉＯ２膜８／Ｓｉ３Ｎ４膜９／ＳｉＯ２膜１０の３
層膜を例えばそれぞれ１００／１２０／１００Å堆積さ
せる。この３層膜の欠陥密度は通常０．０１cm−２以下
で、電界強度は極性によらず通常３０Ｖ以上、２０Ｖ印
加時のリーク電流も１０−１０Ａ／mm２以下である。Embodiment An embodiment of the present invention will be described below with reference to the drawings. First
FIG. 5 to FIG. 5 are manufacturing process diagrams of the same embodiment. This is an EPROM in which the first electrode layer has a high height.
This is an example when applied to (ultraviolet ray erasing type PROM).
Fig. 1 shows a general EP before forming contact holes.
In a cross-sectional view of a ROM, 1 is a P-type silicon substrate, 2 is an N + diffusion layer, 3 is an EPROM cell made of two-layer polysilicon (corresponding to the first electrode / wiring layer), and 4 is an interlayer insulating film. Is. After that, photolithography for opening contact holes is performed. As shown in FIG. 2, a resist 5 is applied, the resist 5 is patterned by a photolithography process, and RIE (reactive ion.
The contact hole 6 is opened by the etching method.
In this case, since the distance between the contact hole 6 and the polysilicon 3 is short, the insulating layer on the side surface of the polysilicon electrode 3 is extremely thin at the portion 7. If the second layer (upper layer), for example, an Al wiring layer is deposited as it is, the probability that the Al wiring layer and the polysilicon electrode 3 are short-circuited due to a defect in the insulating film naturally increases. Therefore, as shown in FIG. 3, the SiO 2 film 8 / Si 3 N 4 film 9 / SiO 2 film 3 is formed by LPCVD (low pressure CVD), for example.
Layer films are deposited, for example, 100/120 / 100Å respectively. The defect density of this three-layer film is usually 0.01 cm −2 or less, the electric field strength is usually 30 V or more regardless of polarity, and the leak current when 20 V is applied is also 10 −10 A / mm 2 or less.
上記３層膜と同様の特性はＳｉ３Ｎ４／ＳｉＯ２／Ｓｉ
３Ｎ４の組み合わせでも実現できる。The characteristics similar to those of the above three-layer film are Si 3 N 4 / SiO 2 / Si
It can be realized by a combination of 3 N 4 .
次に第４図に示すようにエッチバック法によりコンタク
トホール底部の３層膜を除去した後、第５図に示すよう
に第２層目（上層）の配線層となるＡｌ層１１を堆積
し、パターニングする。これにより２層ポリシリコンと
１層Ａｌ層の構造が完了した。Next, as shown in FIG. 4, the three-layer film at the bottom of the contact hole is removed by the etch back method, and then an Al layer 11 to be the second (upper) wiring layer is deposited as shown in FIG. , Patterning. This completed the structure of the two-layer polysilicon and the one-layer Al layer.
本発明によると、従来下層電極とコンタクトホール間の
距離を１μｍ程度に設計しなければならなかったのが、
大幅に縮小できる。理論的には０μｍとしてもショート
は起こらないが、どこまで短くできるかは、下層の電極
又は配線層の用途や種類等にも左右される。これにより
高集積化が可能となると同時に、従来生じていた配線層
間のショートを大幅に低減できる。According to the present invention, conventionally, the distance between the lower electrode and the contact hole had to be designed to be about 1 μm.
It can be greatly reduced. Theoretically, a short circuit does not occur even if the thickness is 0 μm, but the extent to which it can be shortened depends on the use and type of the lower electrode or wiring layer. As a result, high integration can be achieved, and at the same time, a short circuit between wiring layers, which has conventionally occurred, can be significantly reduced.
なお本発明は実施例にのみに限られず種々の応用が可能
である。例えば本実施例では第１層にポリシリコン、第
２層にＡｌを用いた場合について述べたが、これに限定
されないことはもちろんである。The present invention is not limited to the embodiments, and various applications are possible. For example, in this embodiment, the case where polysilicon is used for the first layer and Al is used for the second layer has been described, but it goes without saying that the present invention is not limited to this.
［発明の効果］ 以上説明した如く本発明によれば下層配線又は電極層
と、コンタクトホール開口後に形成する上部配線層との
間に、薄くかつ信頼性の高い絶縁膜を堆積させることに
より、コンタクトホールと下層配線又は電極層との間の
距離をできるだけ短くして、素子の高集積化を達成する
ことができるものである。As described above, according to the present invention, by depositing a thin and highly reliable insulating film between the lower wiring or electrode layer and the upper wiring layer formed after the contact hole is opened, the contact is improved. By making the distance between the hole and the lower wiring or electrode layer as short as possible, high integration of the device can be achieved.
第１図ないし第５図は本発明の一実施例の製造工程説明
図である。 １……Ｐ形シリコン基板、２……Ｎ＋拡散層、３……２
層ポリシリコン層、４……層間絶縁膜、５……フォトレ
ジスト、６……コンタクト開口部、７……問題となる領
域、８……ＳｉＯ２層、９……Ｓｉ３Ｎ４層、１０……
ＳｉＯ２層、１１……Ａｌ配線層。1 to 5 are explanatory views of the manufacturing process of one embodiment of the present invention. 1 ... P-type silicon substrate, 2 ... N + diffusion layer, 3 ... 2
Layer polysilicon layer, 4 ... interlayer insulating film, 5 ... photoresist, 6 ... contact opening, 7 ... problematic area, 8 ... SiO 2 layer, 9 ... Si 3 N 4 layer, 10 ......
SiO 2 layer, 11 ... Al wiring layer.
Claims (2)
ちの下層の配線又は電極層の上に層間絶縁膜を有し、こ
の層間絶縁膜にコンタクトホールが開口され、このコン
タクトホールを含み上層の配線又は電極層が設けられた
半導体装置において、前記コンタクトホールの側面部と
上層の配線又は電極層との間にＳｉＯ２／Ｓｉ３Ｎ４／
ＳｉＯ２又はＳｉ３Ｎ４／ＳｉＯ２／Ｓｉ３Ｎ４より成
る３層絶縁膜を有することを特徴とする半導体装置。1. A wiring or electrode layer having two or more layers, and an interlayer insulating film on a lower wiring or electrode layer among the wiring or electrode layers. A contact hole is formed in the interlayer insulating film. In a semiconductor device in which an upper wiring or electrode layer is provided, the SiO 2 / Si 3 N 4 / is formed between the side surface of the contact hole and the upper wiring or electrode layer.
A semiconductor device having a three-layer insulating film made of SiO 2 or Si 3 N 4 / SiO 2 / Si 3 N 4 .
を有する半導体装置の製造方法において、下層の配線又
は電極層を形成する工程と、前記下層の配線又は電極層
上に層間絶縁膜を形成する工程と、前記層間絶縁膜にコ
ンタクトホールを開口する工程と、前記コンタクトホー
ルを含む層間絶縁膜上にＳｉＯ２／Ｓｉ３Ｎ４／ＳｉＯ
２又は Ｓｉ３Ｎ４／ＳｉＯ２／Ｓｉ３Ｎ４よりなる３層膜を堆
積する工程と、前記コンタクトホール底部の前記３層膜
をエッチバック法により除去し、前記コンタクトホール
側面に前記３層膜を残す工程と、前記コンタクトホール
を含み上層の配線又は電極層を堆積させる工程とを具備
したことを特徴とする半導体装置の製造方法。2. A method of manufacturing a semiconductor device having two or more wiring or electrode layers on a semiconductor substrate, the step of forming a lower wiring or electrode layer, and an interlayer insulating film on the lower wiring or electrode layer. A step of forming a contact hole in the interlayer insulating film, and SiO 2 / Si 3 N 4 / SiO on the interlayer insulating film including the contact hole.
2 or a step of depositing a three-layer film of Si 3 N 4 / SiO 2 / Si 3 N 4 and removing the three-layer film at the bottom of the contact hole by an etch-back method to form the three-layer film on the side surface of the contact hole. A method of manufacturing a semiconductor device, comprising: a step of leaving a film; and a step of depositing an upper wiring or an electrode layer including the contact hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12339687A JPH0620102B2 (en) | 1987-05-20 | 1987-05-20 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12339687A JPH0620102B2 (en) | 1987-05-20 | 1987-05-20 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63288047A JPS63288047A (en) | 1988-11-25 |
| JPH0620102B2 true JPH0620102B2 (en) | 1994-03-16 |
Family
ID=14859526
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12339687A Expired - Fee Related JPH0620102B2 (en) | 1987-05-20 | 1987-05-20 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0620102B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3029444U (en) * | 1995-01-04 | 1996-10-01 | 恰 高橋 | Snow tire |
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-
1987
- 1987-05-20 JP JP12339687A patent/JPH0620102B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3029444U (en) * | 1995-01-04 | 1996-10-01 | 恰 高橋 | Snow tire |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63288047A (en) | 1988-11-25 |
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| LAPS | Cancellation because of no payment of annual fees |