JPH09213801A - Method of manufacturing semiconductor device having step of forming connection hole - Google Patents

Abstract

(57) Abstract: Regarding formation of a connection hole between a substrate and a conductor wiring, or a connection hole between the conductor wiring, a contact resistance can be reduced including a case of a borderless contact, and a highly integrated and fine semiconductor device can be obtained. A manufacturing method is provided. SOLUTION: A semiconductor substrate exposed portion at the bottom of a connection hole 6 is roughened by changing etching conditions (2
0) A step of performing a surface treatment is provided. On the lower insulating film,
The lower conductor wiring is formed by a structure in which at least the upper surface of the lower conductor wiring is a metal material having a chemical composition deviated from the stoichiometric composition. The embedded conductor is etched, and this etching roughens the surface of the conductor after etching.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a step of forming a connection hole. INDUSTRIAL APPLICABILITY The present invention can be used in the field of manufacturing various semiconductor devices having a step of forming connection holes.

[0002]

2. Description of the Related Art Semiconductor devices are being miniaturized.
With the miniaturization and integration of semiconductor devices, an increase in contact resistance of each part of the semiconductor device becomes a problem. For example, typically, the contact resistance increases in the connection hole between the substrate and the conductor wiring (the connection hole between the diffusion region of the semiconductor substrate and the upper wiring, etc.), or the connection hole between the conductor wirings (the lower conductor wiring on the semiconductor substrate). And the problem of increased contact resistance in the connection hole with the upper conductor wiring, etc.
Getting important.

The problems of the prior art will be described below with reference to the drawings. FIGS. 9A and 9B and FIGS. 10A and 10B show the first conventional technique. In this conventional technique, a connection hole is formed in an insulating film provided on a semiconductor substrate by etching, and a conductor is embedded in the connection hole to connect the diffusion region of the semiconductor substrate to the upper wiring. Is a typical method of.

In this conventional technique, first, an element isolation region 2 (here, so-called LOCOS) is formed in a semiconductor substrate 1 (here, an N-type silicon semiconductor substrate), and a diffusion region 3 is formed. Interlayer insulating film 4 such as silicon dioxide
Is formed by a method such as atmospheric pressure CVD film formation and heat treated,
A resist pattern 5 is formed thereon by a photolithography technique (FIG. 9A).

The conditions of the formation of the diffusion region 3, the formation of the silicon dioxide interlayer insulating film 4, and the heat treatment in the above steps are as follows.
It is shown below. Diffusion region 3 formation BF ₂ ⁺ ion implantation (implantation conditions: 35 keV, 3E15
ions / cm ² ) Heat treatment (heat treatment condition: annealing using vertical diffusion furnace, 90
0 ° C., N ₂ under 10 minutes) insulating film 4 formed atmospheric pressure CVD raw material gas: TEOS 60 sccm, TMPO 15s
ccm, TEB 15 sccm Temperature: 520 ° C. Film composition: Boron (B) 2 wt%, Phosphorus (P) 5 wt% Film thickness: 1200 nm Heat treatment of insulating film 4 Annealing using vertical diffusion furnace, N ₂ under 750 ° C. 10 minutes

Next, using the resist pattern 5 thus formed as a mask, a connection hole 6 is formed by etching (here, reactive ion etching is performed) (FIG. 9).
(B)). The processing and forming conditions of the connection hole 6 in this case are shown below. Connection hole 6 processability forming reactive ion etching temperature: -30 ° C. Pressure: 5.3 Pa Power: 1200 W Reaction _{Gas: CO 100sccm, C 4 F 8} 7scc
m, Ar 200 sccm Just etching with 30% over etching.

Next, after removing the resist, contact ion implantation and heat treatment are performed to form the connection hole 6 formed.
After activating the connection bottom portion and further performing a pretreatment for removing an oxide film, a metal, for example, is formed as the adhesion layer 7 on the entire surface by, for example, a magnetron sputtering method, and after performing lamp annealing, the conductor 8 is typically formed. A tungsten film is formed on the entire surface by a thermal CVD method (FIG. 10A). The conditions for the above film formation and the like are shown below.

Activation of Impurities by Contact Ion Implantation Ion implantation under the following conditions. BF ₂ ⁺ ion implantation (implantation conditions: 20 keV, 3E15
ion / cm ² ) Pretreatment for removal of oxide film Wet etching with the following chemical solution (60 seconds) H ₂ O: Buffered hydrofluoric acid = 400: 1 Adhesion layer 7 Metal sputter Collimated sputter of the following film by magnetron sputtering Ti 30 nm Pressure: 0. 52 Pa Power: 8 kW Gas: Ar 35 sccm Temperature: 300 ° C. TiN 70 nm Pressure: 0.78 Pa Power: 6 kW Gas: N ₂ 42 sccm, Ar 21 sccm Temperature: 300 ° C. Adhesion layer 7 lamp annealing Annealing for 30 seconds Temperature: 650 ° C. Pressure: 1 atm Atmosphere gas: N ₂ 100% Conductor 8 film formation (blanket tungsten film thermal CVD film formation) 600 nm thick under the following conditions Pressure: 10.7 kPa Raw material gas: WF ₆ : H ₂ : Ar = 40: 400: 22
50 sccm temperature: 450 ° C

Next, the entire surface is anisotropically etched to leave the tungsten only in the contact hole 6 to achieve the burying, thereby forming the burying plug 8a. Further, an upper conductor wiring material is formed on the entire surface by, for example, a magnetron sputtering method, and the upper conductor wiring 9 is formed by photoresist patterning and anisotropic etching (FIG. 10B).
The upper conductor wiring 9 includes a barrier metal 9a and a conductor portion 9
b and cap metal 9c. Buried plug 8a, upper conductor wiring 9 (barrier metal 9a, conductor portion 9
Examples of process conditions for forming the b and cap metal 9c) are shown below.

First step of forming buried plug (W etching) Pressure: 45.5 Pa Power: 275 W Reaction gas: SF ₆ : Ar: He = 110: 90: 5 s
ccm Second step (TiN etching) Pressure: 6.5 Pa Power: 250 W Reactive gas: Ar: Cl ₂ = 75: 5 sccm sccm Third step (W overetching) Pressure: 32.5 Pa Power: 70 W Reaction gas: SF ₆ : Ar : He = 20: 10: 10s
ccm upper conductor wiring material formation barrier metal formation Ti 20nm pressure: 0.52Pa power: 2kW gas: Ar 35sccm temperature: 300 ° C TiN 20nm pressure: 0.78Pa power: 6kW gas: N ₂ 42sccm, Ar 21sccm temperature: 300 ° C conductor Material formation Al-0.5 wt% Cu as Al-based alloy, 500n
m thickness and formed under the following conditions Pressure: 0.52 Pa Power: 15 kW Gas: Ar 65 sccm Temperature: 300 ° C. Cap metal formation Ti 10 nm Pressure: 0.52 Pa Power: 2 kW Gas: Ar 35 sccm Temperature: 300 ° C. TiN 100 nm Pressure: 0. 78 Pa Power: 6 kW Gas: N ₂ 42 sccm, Ar 21 sccm Temperature: 300 ° C. Conductor material formation Al-0.5 wt Cu% as Al-based alloy, 500 n
m thickness and formed under the following conditions Pressure: 0.52 Pa Power: 15 kW Gas: Ar 65 sccm Temperature: 300 ° C. Cap metal formation Ti 10 nm Pressure: 0.52 Pa Power: 2 kW Gas: Ar 35 sccm Temperature: 300 ° C. TiN 100 nm Pressure: 0. 78 Pa Power: 6 kW Gas: N ₂ 42 sccm, Ar 21 sccm Temperature: 300 ° C. Processing formation of upper conductor wiring RIE was performed under the following conditions. Reaction gas: BCl ₃ / Cl ₂ = 100 / 150scc
m Pressure: 1 Pa Microwave: 400 mA RF power: 110 W Just etching is applied with 40% overetching.

P of the connection hole formed by the above conventional process
⁺ The contact resistance on the Si substrate (contact resistance when making contact with the diffusion region) is a connection hole having a diameter of 0.4 μm and exhibits an ohmic resistance of 20Ω and a diameter of 0.2.
A 220 μΩ non-ohmic characteristic was exhibited with a connection hole of μm. The theoretical increase value calculated from the contact area and the plug resistivity becomes about 6 times 130 Ω when the diameter becomes 0.2 μm. However, in reality, the contact resistance has shifted to a value higher than the theoretical increase value. It is considered that secondary factors of increase in contact resistance are occurring due to reduction of contact area and increase of aspect ratio. If the contact resistance increases and the non-ohmic characteristic is obtained, there is a concern that the characteristics of the transistor may be deteriorated such as operation delay, performance variation, and reduced yield. Further, even in the connection holes between the conductor wirings, the contact resistance is inevitably increased due to the reduction of the contact area, although there is a difference in degree.

On the other hand, in order to reduce the circuit area, a so-called borderless (overlapless) contact in which the conductor wiring and the conductor plug do not overlap has attracted attention (for this, see HW Chung, et. a
l. , "EVALUATIOIN OF BORDER
LESS VIAS FOR SUB-HALF MI
CRON TECHNOLOGIES ”, June 27
-29, 1995 VMIC Conference,
1995 ISMIC, pp 667-669).

The normal conductor wiring is not formed on the upper part of the connection hole by the minimum design rule, but is formed by a loose design rule in consideration of the overlap of the connection hole and the misalignment of the conductor wiring to the connection hole. Has been done. Therefore,
As miniaturization progresses, the degree of integration will be defined by this overlap portion, so realizing borderless connection holes and conductor wiring is one breakthrough for higher integration.

The problems of the conventional borderless (overlapless) contact technique will be described below.
11), (a), (b), and FIG.
A description will be given with reference to (a), (b), and FIG.

In this conventional technique, the lower conductor wiring 11 is formed on the insulating film 10 on the substrate 1 by means of magnetron sputtering, photoresist patterning, anisotropic etching or the like (see FIG. 11 (a)). The lower conductor wiring 11 includes a barrier metal 11a and a conductor portion 11
b and a cap metal 11c. The conditions for forming / depositing the conductor structure and the wiring processing conditions are shown below.

Lower conductor wiring 11 formation Barrier metal formation Ti 20nm Pressure: 0.52Pa Power: 2kW Gas: Ar 35sccm Temperature: 300 ° C TiN 20nm Pressure: 0.78Pa Power: 6kW Gas: N ₂ 42sccm, Ar 21sccm Temperature: 300 ℃ Conductor material formation Al-0.5wt% Cu as Al system alloy, 500n
m thickness and formed under the following conditions Pressure: 0.52 Pa Power: 15 kW Gas: Ar 65 sccm Temperature: 300 ° C. Cap metal formation Ti 10 nm Pressure: 0.52 Pa Power: 2 kW Gas: Ar 35 sccm Temperature: 300 ° C. TiN 100 nm Pressure: 0. 78 Pa Power: 6 kW Gas: N ₂ 42 sccm, Ar 21 sccm Temperature: 300 ° C. Lower conductor wiring processed and formed RIE was performed under the following conditions. Reaction gas: BCl ₃ / Cl ₂ = 100 / 150scc
m Pressure: 1 Pa Microwave: 400 mA RF power: 110 W Just etching is applied with 40% overetching.

Next, an interlayer flattening film 12 is formed by using a CVD insulating film, a coating type silicon resin (such as SOG), or the like, and the connection hole 13 is formed by photolithography patterning technique. It is formed using an anisotropic etching technique or the like (FIG. 11B). At this time, in the borderless contact forming technique, as shown in FIG.
In FIG. 14B, a processed shape shown by reference numeral 14 in which the side surface of the lower conductor wiring 11 falls off from the lower conductor wiring 11 and falls off.

After that, the adhesion layer 15 is formed on the entire surface by the magnetron sputtering method, and then the embedded conductor 16 is formed.
As a film, a tungsten film is formed on the entire surface by thermal CVD (FIG. 12A). The respective film forming conditions are shown below.

Pretreatment for removing oxide film Sputter etching (20 n
m) Sputter etching conditions Pressure: 0.52 Pa Gas: Ar 20 sccm Power: 600 W Temperature: 300 ° C. Adhesion layer 15 metal sputter Sputtering of the following film by magnetron sputtering method Ti 30 nm Pressure: 0.78 Pa Power: 6 kW Gas: N ₂ 42 sccm , Ar 21 sccm Temperature: 300 ° C. Thermal CVD deposition of blanket tungsten film Formed to a thickness of 600 nm under the following conditions Pressure: 10.7 kPa Raw material gas: WF ₆ : H ₂ : Ar = 40: 400: 22
50 sccm temperature: 450 ° C

Next, by anisotropic etching on the entire surface, burying is achieved by leaving tungsten only in the connection hole 13 to form a burying plug 17 (FIG. 12B).
The embedded plug processing forming conditions are shown below.

First step of embedded plug processing (W etching) Pressure: 45.5 Pa Power: 275 W Reaction gas: SF ₆ : Ar: He = 110: 90: 5 s
ccm Second step (TiN etching) Pressure: 6.5 Pa Power: 250 W Reactive gas: Ar: Cl ₂ = 75: 5 sccm sccm Third step (W overetching) Pressure: 32.5 Pa Power: 70 W Reaction gas: SF ₆ : Ar : He = 20: 10: 10s
ccm

After that, an upper conductor wiring material is formed on the entire surface by a magnetron sputtering method, and an upper conductor wiring 18 is formed by using a photoresist patterning technique and an anisotropic etching technique. The upper conductor wiring 18 is composed of a barrier metal 18a, a conductor portion 18b, and a cap metal 18c (FIG. 13). An example of each forming process condition is shown below.

Formation of upper conductor wiring material Formation of barrier metal Ti 20 nm Pressure: 0.52 Pa Power: 2 kW Gas: Ar 35 sccm Temperature: 300 ° C. TiN 20 nm Pressure: 0.78 Pa Power: 6 kW Gas: N ₂ 42 sccm, Ar 21 sccm Temperature: 300 ℃ Conductor material formation Al-0.5wt% Cu as Al system alloy, 500n
m thickness and formed under the following conditions Pressure: 0.52 Pa Power: 15 kW Gas: Ar 65 sccm Temperature: 300 ° C. Cap metal formation Ti 10 nm Pressure: 0.52 Pa Power: 2 kW Gas: Ar 35 sccm Temperature: 300 ° C. TiN 100 nm Pressure: 0. 78 Pa Power: 6 kW Gas: N ₂ 42 sccm, Ar 21 sccm Temperature: 300 ° C. Processing formation of upper conductor wiring RIE was performed under the following conditions. Reaction gas: BCl ₃ / Cl ₂ = 100 / 150scc
m Pressure: 1 Pa Microwave: 400 mA RF power: 110 W Just etching is applied with 40% overetching.

At this time, in the borderless contact according to this conventional technique, the tungsten plug 17 is
As shown in FIG. 13, a region 19 whose upper surface is partially exposed is generated. In the multi-layered wiring having fine connection holes manufactured by this process, the yield of 1 million contact chains between conductor wirings is 0.3 μm diameter, and the deviation from the lower conductor wiring is 0.05 μm or more, the yield becomes remarkable. A drop was confirmed. This result can be explained, firstly, by the difference in contact resistance above and below the connection hole. That is, since the wiring side wall portion is also in contact with the displacement with respect to the lower conductor wiring, the contact resistance does not increase so much, but with the displacement with respect to the upper conductor wiring, the contact resistance between the plug and the upper conductor wiring increases. It will be. Therefore, even if the circuit design is reduced, it can be expected only to the extent specified by the allowable deviation amount from the upper conductor wiring.

[0025]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems of the prior art, and regarding the formation of a connection hole between a substrate and a conductor wiring, or a connection hole between the conductor wiring, including a contactless contact resistance, Therefore, it is an object of the present invention to provide a method for manufacturing a semiconductor device, which can reduce the semiconductor device, and can obtain a highly integrated and fine semiconductor device.

[0026]

According to a method of manufacturing a semiconductor device having a step of forming a connection hole of the present invention, firstly, a step of forming a connection hole by etching an insulating film provided on a semiconductor substrate, The method includes a step of performing a surface treatment for roughening the exposed portion of the semiconductor substrate at the bottom of the connection hole by changing the etching conditions, and a step of embedding a conductor in the connection hole.

Secondly, in the method of manufacturing a semiconductor device having a step of forming a connection hole of the present invention, secondly, a lower conductor wiring is provided on a lower insulating film provided on a semiconductor substrate, and at least an upper surface of the lower conductor wiring. Forming a metal material having a chemical composition deviated from the stoichiometric composition, forming an upper insulating film on the lower conductor wiring, and connecting the lower conductor wiring to the upper insulating film. The method includes a step of forming the connection hole to be formed by reactive ion etching and a step of embedding a conductor in the connection hole.

Thirdly, in the method of manufacturing a semiconductor device having a step of forming a connection hole of the present invention, thirdly, a step of forming a connection hole in an insulating film provided on a semiconductor substrate and a step of embedding a conductor in the connection hole. And a step of etching the conductor and roughening the surface of the conductor after the etching by this etching.

In this case, the connection hole is for connecting the lower conductor wiring on the lower insulating film provided on the semiconductor substrate to the upper conductor wiring, and the upper conductor wiring is not always the connection hole. It is possible to adopt a structure that does not cover the entire upper surface of the conductor embedded in, and can be applied to a so-called borderless contact structure.

According to the first aspect of the present invention, the surface treatment for making the exposed portion of the semiconductor substrate at the bottom of the connection hole rough by changing the etching conditions is performed. Therefore, by embedding a conductor in the connection hole, the rough surface is formed. It is possible to secure a sufficient contact area. Therefore, a connection with reduced contact resistance can be achieved, and a highly reliable semiconductor device having a highly reliable connection structure can be manufactured.

According to the second invention, since the lower conductor wiring is formed of a metal material having a chemical composition deviating from the stoichiometric composition at least on the upper surface of the lower conductor wiring, the lower conductor wiring is formed on the lower conductor wiring. When the holes are formed by etching or the like, the upper surface corresponding to the bottom of the connection holes is roughened by the etching or the like for forming the connection holes. Therefore, by embedding the conductor in the formed connection hole, a sufficient contact area can be secured on this rough surface. Therefore, a connection with reduced contact resistance can be achieved, and a highly reliable semiconductor device having a highly reliable connection structure can be manufactured.

According to the third invention, after the conductor is embedded in the connection hole, the conductor is etched, and the surface of the conductor after etching is roughened by this etching. Therefore, the upper layer wiring is formed on the upper surface of the connection hole. When formed, the connection portion with the upper layer wiring can secure a sufficient contact area on this rough surface. Therefore, a connection with reduced contact resistance can be achieved, and a highly reliable semiconductor device having a highly reliable connection structure can be manufactured. The present invention can be effectively applied to the formation of a borderless contact structure.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. However, as a matter of course, the present invention is not limited to the embodiments specifically described below.

First Embodiment A first embodiment of the present invention will be described with reference to FIGS. 1 and 2. In this example, a connection hole is formed by etching in an insulating film provided on a semiconductor substrate, and a conductor is embedded in the connection hole to connect the diffusion region of the semiconductor substrate to the upper wiring. The invention of No. 1 is applied.

In this example, an element isolation region 2 (so-called LO) is formed on a semiconductor substrate 1 (here, an N-type silicon semiconductor substrate).
COS), and the diffusion region 3 is formed. An interlayer insulating film 4 made of silicon dioxide or the like is formed by means of atmospheric pressure CVD film forming or the like and heat-treated, and a resist pattern 5 is formed thereon by a photolithography technique (FIG. 1A).

The conditions of the formation of the diffusion region 3, the formation of the silicon dioxide interlayer insulating film 4, and the heat treatment in the above steps are as follows.
It is shown below. Diffusion region 3 formation BF ₂ ⁺ ion implantation (implantation conditions: 35 keV, 3E15
ions / cm ² ) Heat treatment (heat treatment condition: annealing using vertical diffusion furnace, 90
0 ° C., N ₂ under 10 minutes) insulating film 4 formed atmospheric pressure CVD raw material gas: TEOS 60 sccm, TMPO 15s
ccm, TEB 15 sccm Temperature: 520 ° C. Film composition: Boron (B) 2 wt%, Phosphorus (P) 5 wt% Film thickness: 1200 nm Heat treatment of insulating film 4 Annealing using vertical diffusion furnace, N ₂ under 750 ° C. 10 minutes

Next, using the resist pattern 5 formed above as a mask, a connection hole 6 is formed by etching (here, reactive ion etching is performed) (FIG. 1).
(B)). In this example, the processing and forming of the connection hole 6 are performed under the following conditions, and the over-etching is performed under the following conditions, so that the surface of the bottom portion (contact portion) of the connection hole 6 is roughened. The bottom surface of the connection hole 6 is roughened as shown in FIG.
Reference numeral 20 is schematically shown in (b). Connection hole 6 processability forming reactive ion etching temperature: -30 ° C. Pressure: 5.3 Pa Power: 1200 W Reaction _{Gas: CO 100sccm, C 4 F 8} 7scc
m, Ar 200sccm Substrate over-etching Reactive ion etching Temperature: -30 ° C Pressure: 5.3Pa Power: 1200W Reaction gas: CO 100sccm, C ₄ F ₈ 7scc
m, Ar 200 sccm, Cl _{2 10} sccm Oxide film 400 nm Etching time treatment

This over-etching can be continuously carried out by changing the composition condition of the gas by adding chlorine gas.

After removing the resist, the contact bottom portion of the contact hole 6 formed by contact ion implantation and heat treatment is activated, and further pretreatment for removing the oxide film is performed, and then, as the adhesion layer 7, for example, a metal is formed. Is formed on the entire surface by, for example, a magnetron sputtering method, lamp annealing is performed, and then a conductor 8, for example, a tungsten film is formed on the entire surface by a thermal CVD method (FIG. 2A). The conditions for the above film formation and the like are shown below.

Activation of Impurities by Contact Ion Implantation Ion implantation under the following conditions. BF ₂ ⁺ ion implantation (implantation conditions: 20 keV, 3E15
ion / cm ² ) Pretreatment for removal of oxide film Wet etching with the following chemical solution (60 seconds) H ₂ O: Buffered hydrofluoric acid = 400: 1 Adhesion layer 7 Metal sputter Collimated sputter of the following film by magnetron sputtering Ti 30 nm Pressure: 0. 52 Pa Power: 8 kW Gas: Ar 35 sccm Temperature: 300 ° C. TiN 70 nm Pressure: 0.78 Pa Power: 6 kW Gas: N ₂ 42 sccm, Ar 21 sccm Temperature: 300 ° C. Adhesion layer 7 lamp annealing Annealing for 30 seconds Temperature: 650 ° C. Pressure: 1 atm Atmosphere gas: N ₂ 100% Conductor 8 film formation (blanket tungsten film thermal CVD film formation) 600 nm thick under the following conditions Pressure: 10.7 kPa Raw material gas: WF ₆ : H ₂ : Ar = 40: 400: 22
50 sccm temperature: 450 ° C

Next, the entire surface is anisotropically etched to leave the tungsten only in the contact hole 6 to achieve the burying, thereby forming the burying plug 8a. Further, an upper conductor wiring material is formed on the entire surface by, for example, a magnetron sputtering method, and the upper conductor wiring 9 is formed by photoresist patterning and anisotropic etching (FIG. 2B). The upper conductor wiring 9 includes a barrier metal 9a, a conductor portion 9b,
And a cap metal 9c. Embedded plug 8
a, upper conductor wiring 9 (barrier metal 9a, conductor portion 9b,
Examples of respective process conditions for forming the cap metal 9c) are shown below.

First step of forming buried plug (W etching) Pressure: 45.5 Pa Power: 275 W Reaction gas: SF ₆ : Ar: He = 110: 90: 5 s
ccm Second step (TiN etching) Pressure: 6.5 Pa Power: 250 W Reactive gas: Ar: Cl ₂ = 75: 5 sccm Third step (W over etching) Pressure: 32.5 Pa Power: 70 W Reactive gas: SF ₆ : Ar : He = 20: 10: 10s
ccm upper conductor wiring material formation barrier metal formation Ti 20nm pressure: 0.52Pa power: 2kW gas: Ar 35sccm temperature: 300 ° C TiN 20nm pressure: 0.78Pa power: 6kW gas: N ₂ 42sccm, Ar 21sccm temperature: 300 ° C conductor Material formation Al-0.5 wt% Cu as Al-based alloy, 500n
m thickness and formed under the following conditions Pressure: 0.52 Pa Power: 15 kW Gas: Ar 65 sccm Temperature: 300 ° C. Cap metal formation Ti 10 nm Pressure: 0.52 Pa Power: 2 kW Gas: Ar 35 sccm Temperature: 300 ° C. TiN 100 nm Pressure: 0. 78 Pa Power: 6 kW Gas: N ₂ 42 sccm, Ar 21 sccm Temperature: 300 ° C. Processing formation of upper conductor wiring RIE was performed under the following conditions. Reaction gas: BCl ₃ / Cl ₂ = 100 / 150scc
m Pressure: 1 Pa Microwave: 400 mA RF power: 110 W Just etching is applied with 40% overetching.

In the connection hole formed by the process of this example, P ⁺
The contact resistance in the Si substrate (contact resistance when making contact with the diffusion region) is 220 Ω in the connection hole of 0.2 μm in diameter in the prior art, but it is much better than the non-ohmic characteristic. It was possible to improve the ohmic characteristics up to about 120Ω. This is performed in the above-mentioned process by over-etching in the process of forming the connection hole 6 under the condition that the surface of the bottom portion (contact portion) of the connection hole 6 is roughened (specifically, by changing the gas composition here). This is due to the fact. It is considered that the contact contact area was approximately doubled due to this roughening treatment.

As described above, in this example, the connection hole 6 is formed in the insulating film 4 provided on the semiconductor substrate 1 by etching, and the etching condition of the exposed portion of the semiconductor substrate at the bottom of the connection hole 6 is changed. As a result of the configuration including a step of performing a surface treatment for roughening (FIGS. 1A and 1B) and a step of embedding the conductor 8 in the connection hole 6 (FIGS. 2A and 2B),
A semiconductor device having a low contact resistance and good connectivity could be manufactured.

Second Embodiment A second embodiment of the present invention will be described with reference to FIGS. In this example, a lower conductor wiring is formed on a lower insulating film provided on a semiconductor substrate, an upper insulating film is formed on the lower conductor wiring, and a lower conductor wiring is further formed on the upper insulating film. The second invention is applied to the case of forming a connection hole for connecting to a conductor wiring.

In this example, the insulating film 10 on the substrate 1
And the lower conductor wiring 11 by the magnetron sputtering method,
It is formed by means of photoresist patterning, anisotropic etching, etc. (FIG. 3A). The lower conductor wiring 11 includes a barrier metal 11a, a conductor portion 11b, and a cap metal 21. Here, in this example, the cap metal 21 of the lower conductor wiring 11 is usually made to have a gas ratio of N ₂
/ (N ₂ + Ar) was about 75%, and a film was formed under the condition of about 60%, whereby the composition of titanium and nitrogen was deviated from the stoichiometric composition 1: 1. Obtained by forming a titanium nitride film. It is considered that the titanium-rich composition is about 30 at%. The specific conditions for processing each wiring are shown below.

Formation of Lower Conductor Wiring 11 Formation of Barrier Metal Ti 20 nm Pressure: 0.52 Pa Power: 2 kW Gas: Ar 35 sccm Temperature: 300 ° C. TiN 20 nm Pressure: 0.78 Pa Power: 6 kW Gas: N ₂ 42 sccm, Ar 21 sccm Temperature: 300 ℃ Conductor material formation Al-0.5wt% Cu as Al system alloy, 500n
m thickness and formed under the following conditions Pressure: 0.52 Pa Power: 15 kW Gas: Ar 65 sccm Temperature: 300 ° C. Cap metal formation Ti 10 nm Pressure: 0.52 Pa Power: 2 kW Gas: Ar 35 sccm Temperature: 300 ° C. TiN 100 nm Pressure: 0. 78 Pa Power: 6 kW Gas: N ₂ 40 sccm, Ar 25 sccm Temperature: 300 ° C. (This TiN formation condition is stoichiometrically normal 1: 1
The gas composition is N ₂ 42 s
It was the above composition that ccm and Ar were about 21 sccm. ) Process formation of lower conductor wiring RIE was performed under the following conditions. Reaction gas: BCl ₃ / Cl ₂ = 100 / 150scc
m Pressure: 1 Pa Microwave: 400 mA RF power: 110 W Just etching is applied with 40% overetching.

Next, the interlayer flattening film 12 is formed by using a CVD insulating film, a coating type silicon resin (such as SOG), etc., and the connection hole 13 is formed by photolithography patterning technique. It is formed using an anisotropic etching technique or the like. At this time, in this example, the cap metal (TiN) is deviated from the stoichiometric composition and is probably a titanium nitride film in a porous state. Therefore, it is presumed that the etching rate of the crystal grain boundary portion is increased during the etching for forming the contact hole, but as shown by reference numeral 22 in FIG. 3B, the cap metal surface (that is, the bottom portion of the contact hole). A rough surface is formed, which has a poor surface morphology.

The processing conditions for connecting holes are shown below. Formation of connection hole processing Reactive ion etching was performed under the following conditions. Temperature: -30 ° C Pressure: 5.3Pa Power: 1200W Reaction gas: CO 100sccm, C ₄ F ₈ 7sc
cm, Ar 200 sccm Just etching with 30% overetch.

After that, the adhesion layer 15 is formed on the entire surface by the magnetron sputtering method, and then the tungsten film forming the conductor 16 for embedding is formed on the entire surface by thermal CVD (FIG. 4A). The respective film forming conditions are shown below.

Pretreatment for Oxide Film Removal Sputter etching (20 n
m) Sputter etching conditions Pressure: 0.52 Pa Gas: Ar 20 sccm Power: 600 W Temperature: 300 ° C. Adhesion layer 15 metal sputter Sputtering of the following film by magnetron sputtering TiN 30 nm Pressure: 0.78 Pa Power: 6 kW Gas: N ₂ 42 sccm , Ar 21 sccm Temperature: 300 ° C. Thermal CVD deposition of blanket tungsten film Formed to a thickness of 600 nm under the following conditions Pressure: 10.7 kPa Raw material gas: WF ₆ : H ₂ : Ar = 40: 400: 22
50 sccm temperature: 450 ° C

Next, the entire surface is anisotropically etched to achieve the filling by leaving the tungsten only in the connection hole 13 to form the embedded plug 17 (FIG. 4B). The embedded plug processing forming conditions are shown below.

First step of embedded plug processing (W etching) Pressure: 45.5 Pa Power: 275 W Reaction gas: SF ₆ : Ar: He = 110: 90: 5 s
ccm Second step (TiN etching) Pressure: 6.5 Pa Power: 250 W Reactive gas: Ar: Cl ₂ = 75: 5 sccm sccm Third step (W overetching) Pressure: 32.5 Pa Power: 70 W Reaction gas: SF ₆ : Ar : He = 20: 10: 10s
ccm

After that, the upper conductor wiring material is formed on the entire surface by magnetron sputtering, and the upper conductor wiring 18 is formed by using the photoresist patterning technique and the anisotropic etching technique (FIG. 5). This upper conductor wiring 1
Reference numeral 8 is composed of a barrier metal 18a, a conductor portion 18b, and a cap metal 18c. An example of each forming process condition is shown below.

Formation of Upper Conductor Wiring Material Formation of Barrier Metal Ti 20 nm Pressure: 0.52 Pa Power: 2 kW Gas: Ar 35 sccm Temperature: 300 ° C. TiN 20 nm Pressure: 0.78 Pa Power: 6 kW Gas: N ₂ 42 sccm, Ar 21 sccm Temperature: 300 ℃ Conductor wiring 18 formation Al-0.5wt% Cu as an Al type alloy, 500n
m thickness and formed under the following conditions Pressure: 0.52 Pa Power: 15 kW Gas: Ar 65 sccm Temperature: 300 ° C. Cap metal formation Ti 10 nm Pressure: 0.52 Pa Power: 2 kW Gas: Ar 35 sccm Temperature: 300 ° C. TiN 100 nm Pressure: 0. 78 Pa Power: 6 kW Gas: N ₂ 42 sccm, Ar 21 sccm Temperature: 300 ° C. Processing formation of upper conductor wiring RIE was performed under the following conditions. Reaction gas: BCl ₃ / Cl ₂ = 100 / 150scc
m Pressure: 1 Pa Microwave: 400 mA RF power: 110 W Just etching is applied with 40% overetching.

In the multi-layer wiring having the fine connection holes formed by the process of this example, the contact resistance can be sufficiently reduced,
We were able to improve the connection contact. It has become possible to reduce the contact resistance to about 1/2. this is,
In the above process, the composition of the cap metal 21 forming the bottom surface of the connection hole 6 is deviated from the stoichiometry, and the surface of the bottom portion (contact portion) of the connection hole 6 is roughened to form the roughened surface 22. It is thought that this is because the contact area of the contacts has doubled.

As described above, in this example, the lower conductor wiring 11 is formed on the lower insulating film 10 provided on the semiconductor substrate 1.
A metal material (cap metal 21) having a chemical composition deviating from the stoichiometric composition at least on the upper surface of the lower conductor wiring 11 (FIG. 3).
(A)), a step of forming an upper insulating film 12 on the lower conductor wiring 11, and the lower conductor wiring 1 on the upper insulating film 12.
As a result of the configuration including the step of forming the connection hole 13 to be connected to 1 by reactive ion etching and the step of embedding the conductor in the connection hole 13 (FIG. 4A), the contact resistance is low and the good connectivity is achieved. It was possible to manufacture a semiconductor device having

Third Embodiment A third embodiment of the present invention will be described with reference to FIGS. 6 to 8. In this example, the third invention is applied to the case where a borderless contact is formed.

In this example, the insulating film 10 on the substrate 1
The lower conductor wiring 11 is formed thereon by means of magnetron sputtering, photoresist patterning, anisotropic etching, etc. (FIG. 6A). The lower conductor wiring 11 includes a barrier metal 11a, a conductor portion 11b, and a cap metal 11c. Formation of this conductor structure
Film forming conditions and wiring processing conditions are shown below.

Lower conductor wiring 11 formation Barrier metal formation Ti 20nm Pressure: 0.52Pa Power: 2kW Gas: Ar 35sccm Temperature: 300 ° C TiN 20nm Pressure: 0.78Pa Power: 6kW Gas: N ₂ 42sccm, Ar 21sccm Temperature: 300 ℃ Conductor material formation Al-0.5wt% Cu as Al system alloy, 500n
m thickness and formed under the following conditions Pressure: 0.52 Pa Power: 15 kW Gas: Ar 65 sccm Temperature: 300 ° C. Cap metal formation Ti 10 nm Pressure: 0.52 Pa Power: 2 kW Gas: Ar 35 sccm Temperature: 300 ° C. TiN 100 nm Pressure: 0. 78 Pa Power: 6 kW Gas: N ₂ 42 sccm, Ar 21 sccm Temperature: 300 ° C. Lower conductor wiring processed and formed RIE was performed under the following conditions. Reaction gas: BCl ₃ / Cl ₂ = 100 / 150scc
m Pressure: 1 Pa Microwave: 400 mA RF power: 110 W Just etching is applied with 40% overetching.

Next, an insulating film 12 forming an interlayer flattening film is formed by using a CVD insulating film, a coating type silicon resin (such as SOG), or the like.
The connection hole 13 is formed here using a photolithography patterning technique, an anisotropic etching technique, or the like (FIG. 6).
(B). Reference numeral 14 is the same as that described with reference to FIG.

After that, the adhesion layer 15 is formed on the entire surface by the magnetron sputtering method, and then the embedded conductor 16 is formed.
Then, a tungsten film is formed over the entire surface by thermal CVD (FIG. 7A). The respective film forming conditions are shown below.

Pretreatment for removing oxide film Sputter etching (20 n
m) Sputter etching conditions Pressure: 0.52 Pa Gas: Ar 20 sccm Power: 600 W Temperature: 300 ° C. Adhesion layer 15 metal sputter Sputtering of the following film by magnetron sputtering method Ti 30 nm Pressure: 0.78 Pa Power: 6 kW Gas: N ₂ 42 sccm , Ar 21 sccm Temperature: 300 ° C. Thermal CVD deposition of blanket tungsten film Formed to a thickness of 600 nm under the following conditions Pressure: 10.7 kPa Raw material gas: WF ₆ : H ₂ : Ar = 40: 400: 22
50 sccm temperature: 450 ° C

Then, the entire surface is anisotropically etched to leave the tungsten only in the connection hole 6 and the filling is achieved to form the embedded plug 17. At this time, in this example, the process of roughening the contact surface of the plug is performed in the final step of the plug processing step. Specifically, etching is performed under the following conditions to roughen the surface of the contact portion (FIG. 7B). The portion subjected to the treatment for roughening the surface of the contact portion is schematically shown by reference numeral 20a in FIG. 7 (b). The embedded plug processing forming conditions are shown below.

First step (W etching) of embedded plug processing Pressure: 45.5 Pa Power: 275 W Reaction gas: SF ₆ : Ar: He = 110: 90: 5 s
ccm Second step (TiN etching) Pressure: 6.5 Pa Power: 250 W Reactive gas: Ar: Cl ₂ = 75: 5 sccm sccm Third step (W overetching) Pressure: 32.5 Pa Power: 70 W Reaction gas: SF ₆ : Ar : He = 20: 10: 10s
ccm 4th step (etching for W surface roughening treatment) Pressure: 6.5 Pa Power: 250 W Reaction gas: Ar: Cl ₂ : F = 30: 30: 10 scc
m

After that, an upper conductor wiring material is blanket deposited by a magnetron sputtering method, and an upper conductor wiring 18 is formed by using a photoresist patterning technique and an anisotropic etching technique (FIG. 8). This upper conductor wiring 1
Reference numeral 8 is composed of a barrier metal 18a, a conductor portion 18b, and a cap metal 18c. An example of each forming process condition is shown below.

Upper conductor wiring material formation Barrier metal formation Ti 20nm Pressure: 0.52Pa Power: 2kW Gas: Ar 35sccm Temperature: 300 ° C TiN 20nm Pressure: 0.78Pa Power: 6kW Gas: N ₂ 42sccm, Ar 21sccm Temperature: 300 ℃ Conductor material formation Al-0.5wt% Cu as Al system alloy, 500n
m thickness and formed under the following conditions Pressure: 0.52 Pa Power: 15 kW Gas: Ar 65 sccm Temperature: 300 ° C. Cap metal formation Ti 10 nm Pressure: 0.52 Pa Power: 2 kW Gas: Ar 35 sccm Temperature: 300 ° C. TiN 100 nm Pressure: 0. 78 Pa Power: 6 kW Gas: N ₂ 42 sccm, Ar 21 sccm Temperature: 300 ° C. Processing formation of upper conductor wiring RIE was performed under the following conditions. Reaction gas: BCl ₃ / Cl ₂ = 100 / 150scc
m Pressure: 1 Pa Microwave: 400 mA RF power: 110 W Just etching is applied with 40% overetching.

At this time, in the borderless contact,
A region 19 of which the upper surface of the tungsten plug 17 is partially exposed occurs (FIG. 8). In the multi-layer wiring having fine connection holes manufactured by this example, 10
With respect to the yield of 0,000 contact chains, even if the displacement with respect to the upper conductor wiring is about 0.25 μm, the contact area between the conductor plug 17 and the upper conductor wiring 18 can be secured by the above-mentioned roughening treatment, so that the yield is not significantly reduced. It cannot happen. As a result, the circuit can be further reduced, and a fine and highly integrated semiconductor device can be manufactured.

[0069]

According to the method of manufacturing a semiconductor device of the present invention, regarding the formation of the connection hole between the substrate and the conductor wiring, or the connection hole between the conductor wiring, including the case of the borderless contact,
The contact resistance can be effectively reduced, and thus a highly integrated and fine semiconductor device can be manufactured.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing the steps of the first embodiment in order (1).

FIG. 2 is a sectional view showing the steps of the first embodiment in order (2).

FIG. 3 is a sectional view showing the steps of the second embodiment in order (1).

FIG. 4 is a sectional view sequentially showing the steps of the second embodiment (2).

5A to 5C are sectional views showing the steps of the second embodiment in order (3).

FIG. 6 is a sectional view showing the steps of the third embodiment in order (1).

FIG. 7 is a sectional view sequentially showing the steps of the third embodiment (2).

FIG. 8 is a sectional view showing the steps of the third embodiment in order (3).

FIG. 9 is a diagram showing a process of the conventional technique (I) (1).

FIG. 10 is a diagram showing a process of the conventional technique (I) (2).

FIG. 11 is a diagram showing a process of the conventional technique (II) (1).

FIG. 12 is a diagram showing a step of the related art (II) (2).

FIG. 13 is a diagram showing a process of a conventional technique (III) (3).

[Explanation of symbols]

 1 Semiconductor Substrate 2 Element Isolation Region 3 Diffusion Region of 3 (Semiconductor Substrate) 4 Insulating Film 5 Resist Pattern 6 Connection Hole 8 Conductor 8a Embedded Plug 9 Upper Conductor Wiring 10 Lower Insulating Film 11 Lower Wiring 21 Cap Metal 22 Rough Surface 12 Upper Insulation Membrane 13 Connection hole 17 Embedded plug 18 Upper wiring 20a Rough surface

Claims (4)

[Claims] 1. A step of forming a contact hole in an insulating film provided on a semiconductor substrate by etching, and a step of subjecting a semiconductor substrate exposed portion at the bottom of the contact hole to roughening by changing etching conditions. A method for manufacturing a semiconductor device having a step of forming a connection hole, which comprises a step of burying a conductor in the connection hole. 2. A lower conductor wiring is formed on a lower insulating film provided on a semiconductor substrate by a metal material having a chemical composition in which at least the upper surface of the lower conductor wiring is deviated from the stoichiometric composition. A step of forming an upper insulating film on the lower conductor wiring, forming a connection hole in the upper insulating film for connecting to the lower conductor wiring by reactive ion etching, and forming a conductor in the connection hole. A method of manufacturing a semiconductor device having a step of forming a connection hole, which has a step of burying. 3. A step of forming a connection hole in an insulating film provided on a semiconductor substrate, a step of embedding a conductor in the connection hole, etching the conductor, and the surface of the conductor after etching by this etching. A method of manufacturing a semiconductor device, comprising a step of forming a connection hole, the method comprising: 4. The connection hole is for connecting the lower conductor wiring on the lower insulating film provided on the semiconductor substrate to the upper conductor wiring, and the upper conductor wiring is not necessarily formed in the connection hole. The method of manufacturing a semiconductor device having a step of forming a connection hole according to claim 3, wherein the structure does not cover the entire upper surface of the embedded conductor.