JPH09162246A - TAB tape connection structure and connection method - Google Patents

Abstract

(57) [Abstract] [Problem] When the pitch of wiring is shortened, the copper foil becomes thin, making it impossible to perform photoresist pattern etching, leading to a decrease in lead strength and a decrease in connection reliability. In a semiconductor device in which an inner lead of a one-layer wiring lead frame is connected to an LSI and an input lead and an output lead of a one-layer wiring TAB tape are connected to an LCD panel or a printed circuit board, a polyimide tape is provided. Single-layer wiring TAB tape 10 on one side
3 is attached with an adhesive 102a, and the semiconductor chip 1 is attached to the other surface.
01 is attached with the adhesive 102b. In addition, output lead 1
Anisotropic conductive film 110 is temporarily adhered to 08. The input lead 107 is connected to an electrode such as an LCD panel via the anisotropic conductive film 110, and the input lead 107 is connected to a printed circuit board or the like by soldering.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a TA for single-layer wiring.
B (Tape Automated Bonding) tape connection structure, especially LSI for LCD (Liquid Crystal Display) drive
The present invention relates to a TAB tape connecting structure and a connecting method which are effectively used for mounting.

[0002]

2. Description of the Related Art For example, an LCD driving LSI (Large
The connection of Scale Integrated Circuit) has traditionally been TCP
It is performed using a TAB tape for (Tape Carrier Package). FIG. 11 is a plan view showing a connection structure of a conventional LCD TAB tape, and FIG. 12 is a sectional view taken along line CC of FIG. In addition, FIG. 13 shows the semiconductor device of FIG.
It is sectional drawing which shows the state mounted in the module.

An opening for mounting the semiconductor chip 202 is provided in the central portion of the rectangular TAB tape 201, and inner leads 203 are provided from each side toward the center of the opening.
Are attached, and the output leads 204 are connected to the outer ends of some of them. And the inner lead 20
An Au bump 205 is provided on the lower side of each inner end of No. 3. The electrodes of the semiconductor chip 202 are aligned with the Au bumps 205 and the ILB (Inner
Lead Bonding) Connected and semiconductor chip 20 under the opening
2 is provided. TAB tape 2 in this state
The opening 01 is filled with silicon resin 206, and the semiconductor chip 202 is fixed as shown in FIG.

In the semiconductor device completed as shown in FIG. 12, the output leads 204 have LCD panels 2 as shown in FIG.
ITO (Indium Tin Oxide) electrode 20 provided on 07
8 through the anisotropic conductive film 211, and Sn-plated ends of the other inner leads 203 are soldered to the electrode pattern 210 of the printed board 209.

As a method of connecting a TAB tape to an LSI or the like, for example, JP-A-5-41404 and JP-A-5-41404.
90353, JP-A-6-299474, JP-A-6-224262 and the like,
In JP-A-5-41404, a semiconductor chip and a circuit board are fixed via a thermosetting resin sheet, and bumps of the semiconductor chip and wiring patterns of the circuit board are connected.

[0006]

However, the conventional TAB
According to the tape connection structure, the thickness of the copper foil forming the wiring layer is 4 μm or more and 35 μm or less, and the photoresist pattern etching can be performed with the copper foil thickness of 35 μm as the lower limit when the pitch between the wirings is 100 μm. However, if the pitch between the wirings is 100 μm or less (for example, 80 μm or less), photoresist pattern etching becomes impossible unless the copper foil thickness is 25 μm or less, and as a result, the strength of the leads decreases.

Further, by using a TCP TAB tape,
When miniaturizing the connecting portion of the CD driving LSI,
Au bumps and TAs placed on the periphery due to the smaller size of
Make an ILB connection with the inner lead of the B tape.
Unless the structure of the AB tape is devised, the lead strength is reduced and the connection reliability cannot be obtained. Therefore, according to the present invention, the flip-chip connection can be performed even if the lead strength is weakened, and the reliability thereof can be improved.
An object of the present invention is to provide a B tape connecting structure and a connecting method.

[0008]

In order to achieve the above-mentioned object, according to the present invention, an inner lead of a one-layer wiring TAB tape is flip-chip connected to a semiconductor chip, and
In a semiconductor device in which input / output leads of a layer wiring TAB tape are connected to an external circuit, the one layer wiring TAB tape is attached to one surface with an adhesive and the semiconductor chip is attached to the other surface with an adhesive. The polyimide tape to be attached and the anisotropic conductive film temporarily attached to the output lead portion of the one-layer wiring TAB tape are provided.

According to this structure, the insufficient strength of the leads is compensated by the affixed polyimide tape, and the reliability of the connection can be improved. In addition, high insulation resistance can be provided between the leads, which facilitates fine wiring. The one-layer wiring TAB tape has a size substantially equal to the mounting area of the semiconductor chip.

By making the size equivalent to a chip as described above, the wiring pattern length is shortened and the stray capacitance is reduced, so that the transmission speed can be improved. Moreover, the self-inductance is reduced by shortening the wiring length, and the amount of noise generated in the power supply is reduced. The one-layer wiring TAB tape has a thickness of 3 to 35 μm and the wiring material is copper or copper alloy.

The copper used for the wiring is suitable for versatility and mass production, and is advantageous in terms of price. Furthermore, the copper alloy has heat resistance and sufficient lead strength, and is also suitable for photoresist processing and solder processing. The one-layer wiring TAB tape has a constitution in which a wiring layer is attached to one surface of a punched polyamic acid layer and further made into a polyimide.

According to this structure, for example, fine etching with a pitch of 80 μm can be performed, a chip size TAB tape connection structure can be realized by flip chip connection, and electrical characteristics can be improved and connection reliability can be improved. it can. Further, the polyimide tape has a thickness of 25
.About.75 .mu.m, the thickness of the adhesive is 13 to 100 .mu.m, and the material is thermosetting or thermoplastic.

The polyimide tape having the above-mentioned thickness has an appropriate degree of elasticity, and it is possible to obtain versatility and mass productivity suitable for the price. The adhesive having the above thickness has a necessary adhesive force and mass productivity, and is not disadvantageous in terms of price. Further, the above-mentioned object is to provide a semiconductor chip with a single-layer wiring T.
In the semiconductor device in which the inner lead of the AB tape is flip-chip connected, and the input / output lead of the one-layer wiring TAB tape is connected to an external circuit, the one-layer wiring T
The inner lead regions other than the bumps of the AB tape are fixed to one side of a polyimide tape having adhesives on both sides, and an anisotropic conductive film is temporarily adhered to the output lead of the one-layer wiring TAB tape, and the semiconductor chip Is attached to a predetermined position of the polyimide tape, the inner lead and the electrode portion of the semiconductor chip are gang bonded, and the output lead of the one-layer wiring TAB tape is connected using the anisotropic conductive film. This can also be achieved by bonding to a mating partner and soldering the input lead of the one-layer wiring TAB tape to the mating partner.

According to this method, the inner lead portion is first fixed by the polyimide tape, the strength of the lead is reinforced, and the lead is attached to the semiconductor chip in this state. There is no deformation. In addition, high insulation resistance can be provided between the leads, which facilitates fine wiring.

[0015]

1 is a front sectional view showing an embodiment of a connection structure of a TAB tape according to the present invention, and FIG. 2 is an explanatory view showing a part of a manufacturing process of the TAB tape of FIG. FIG. 3 is a sectional view showing a state in which the semiconductor device completed as shown in FIG. 2 is mounted on an LCD module.

On the connection surface of the semiconductor chip 101 (here, the LCD driving LSI), with respect to the semiconductor chip 101,
A slightly large shape (several mm from the periphery of the semiconductor chip 101)
A polyimide tape 102 with a double-sided adhesive, which is dimensioned to have a size exposed, that is, a chip size, is attached, and a TAB tape 103 is attached to the other surface. At the center of the polyimide tape 102, the electrodes of the semiconductor chip 101 and the inner leads 1 of the TAB tape 103 are formed.
04, an opening 105 for connecting to the semiconductor chip 101 and the inner lead 104 is formed.
The Au bumps 106 are connected, that is, flip chip connection.

The TAB tape 103 is used for the semiconductor chip 10.
An inner lead 104 corresponding to each of the first electrodes, and an input lead 1 formed outside the inner lead 104.
07, the output lead 108, and the polyamic acid layer 10 provided so as to cover the surfaces of the inner lead 104.
9 and the anisotropic conductive film 110 provided so as to cover the surfaces of the output leads 108.

Referring now to FIG. 2, the TAB tape 103
The manufacturing procedure of will be described. First, as shown in (a), a predetermined thickness (specifically, 20 to 75 μm is suitable, here, 40 μm).
Unnecessary part 109 from the polyamic acid layer 109)
A is punched out, and the wiring layer 111 is formed on one side as shown in (b).
After laminating, the polyimide is applied. Furthermore, a photoresist process and a patterning process are performed, and fine leads of 80 μm pitch are secured by one-side exposure and one-side etching. Next, after soldering with a thickness of 4 μm is applied to the portions of the semiconductor chip 101 to be connected to the electrodes, the input lead portion without the polyimide layer, and the output lead portion, the polyimide tape 10 with adhesives 102a and 102b applied on both sides.
2 is attached (the inner lead portion in the area other than the bump connection). Further, the anisotropic conductive film 110 is temporarily adhered to the output lead 108 portion. This state is shown in FIG.
The anisotropic conductive film 108 is provided for the output lead 107.
Is temporarily adhered, and I of the LCD panel 207 described with reference to FIG.
This is to reduce the number of connecting steps with the TO electrode 208.

The polyimide tape 102 has a polyimide-based thermosetting base with a thickness of 50 μm, and the adhesives 102a and 102b applied to the base have a thickness of 13 μm. And, for example, the mounted LSI is 2 × 15 mm
In this case, the polyimide tape 102 has an inner size of 1.5 × 13 mm and an outer size of 4 × 17 mm. Inner leads 10 connected to the electrodes of the semiconductor chip 101
4, the output lead 108 and the input / output lead 104
Each of these is plated with Sn solder or Au. With respect to the TAB tape in this state, the semiconductor chip 101 is arranged at the center as shown in FIG. 1 with respect to the TAB tape 103 obtained as shown in FIG.
The polyimide tape 102 in which the area other than the bump connection portion at the tip of the inner lead 104 is fixed to the inner lead 104 of the TAB tape 103 by performing flip-chip connection between the inner lead 104 and the inner lead 104 with the adhesive 102b. Adhesively fixed through. As a result, the semiconductor device shown in FIG. 1 is completed.

Here, the TAB tape 103 (single-layer wiring T
The thickness of the wiring layer 111 provided on the AB tape is 3 to 3
It is set to 5 μm. This is based on the fact that photoresist and patterning are single-sided exposure and single-sided etching.
For fine etching of 0 μm pitch, the thickness is 35
This is because it is desirable that the thickness is less than μm. Further, if the wiring thickness is less than 3 μm, the lead may be deformed during transportation and handling, which causes a decrease in mass productivity.

The material of the wiring layer 111 (wiring material) is
Copper or copper alloys (for example, Cu-Zr alloys, Cu-Sn alloys, etc.) are desirable in terms of versatility, mass productivity, and cost. Particularly, when importance is placed on strength and heat resistance, a copper alloy is suitable. As described above, the thickness of the base of the polyimide tape 102 is preferably 25 to 75 μm, and the thickness of the adhesives 102a and 102b applied to both surfaces thereof is 13 to 100 μm.
m is suitable. Here, the reason for setting the base thickness to 25 to 75 μm is that the base thickness of a commercially available double-sided adhesive-attached polyimide tape is 25 to 75 μm, which can satisfy general versatility and mass productivity. If the base thickness is less than 25 μm, it becomes soft and the waist becomes weak, making it difficult to handle.
Further, if it exceeds 75 μm, the stiffness becomes strong and it hardens, and it becomes difficult to handle. Further, the adhesive 102a, 102
The material of b is an elevated temperature (about 180 ° C.) due to heat conduction accompanying the heating when the ILB is connected to the inner lead 104.
Those that can withstand the time (° C.) (about several seconds), specifically, thermosetting or thermoplastic epoxy resin-based or polyimide resin-based adhesives are suitable.

As shown in FIG. 1, the size of the TAB tape is the semiconductor chip 101 which is a driving LSI for the LCD.
The reason why the connection is made substantially the same in size is that the connection structure is downsized, the wiring length is shortened (for example, 1/3 or less of the conventional),
This is because the transmission speed can be improved and the self-inductance Ls can be suppressed (for example, 1/3 or less), whereby the noise amount (Vn) generated in the power supply can be reduced to, for example, 1/3 or less.

The semiconductor device completed in the state of FIG.
As shown in FIG.
The anisotropic conductive film 110 is used to connect to the ITO electrode 208 provided on the. The input / output lead 108 is soldered to the electrode pattern 210 provided on the printed board 204. The LCD module is completed by the above. Although not shown in FIG. 3, the surface of the inner lead 104 is covered with a protective silicone resin.

FIG. 4 is a plan view showing another embodiment of the TAB tape connection structure according to the present invention, and FIG. 5 is a sectional view taken along line AA of FIG. 6 is a cross-sectional view showing an LCD module formed by connecting the semiconductor device having the structure shown in FIG. 5 to an LCD panel. As shown in FIG. 3, the TAB tape connection structure shown in FIG.
While the mounting structure is arranged at a position higher than the CD panel 207, in this configuration example, the semiconductor chip 101 and L
The CD panels 207 are arranged on the same level. Therefore, it is necessary to provide a connection surface for connecting the printed board 204 and the LCD panel 207 on the semiconductor chip 101 side.

Therefore, as shown in FIG. 5, wiring layers (inner lead 104, input lead 107 and output lead 1) are formed.
No. 08) each having a thickness of 3 to 35 μm is formed on the tape 112, and the one-layer wiring TAB tape 112 is used.
A portion of the inner lead 104 connected to the Au bump 106 is soldered or Au plated. As shown in FIG. 4, the chip size (semiconductor chip 101 is 2 × 15 mm
Inner dimension is 1.5 × 13mm, outer dimension is 4 × 1
A frame-shaped polyimide tape 102 having a connection portion with the semiconductor chip 101 having an opening of 7 mm) is adhered to the inner lead portion via an adhesive agent 102a. Further, the anisotropic conductive film 110 is temporarily adhered to the surface of the output lead 108 to which the polyimide tape 102 is not adhered.

As shown in FIG. 5, the single-layer wiring TAB tape having such a structure is mounted with the semiconductor chip 101 so that the connection portion is located in the opening portion, and the inner lead 10 is formed.
4 and Au bump 106 are flip-chip connected by gang bonding. Then, the polyimide tape 102 is attached to the semiconductor chip 101 via the adhesive agent 102b. As described above, by fixing the semiconductor chip 101 to the one-layer wiring TAB tape with the polyimide tape 102, the setting values of the respective portions in the configuration of FIGS. 4 and 5 at the connection portion between the bump and the inner lead will be described below. explain.

The thickness of the wiring layer of the TAB tape 112 is 3 to.
35 μm, 80 by one side exposure and one side etching
Leads are formed with a μm pitch. To perform exposure and etching with this pitch, 35 μm is suitable.
In this case, if the thickness is less than 3 μm, the lead may be deformed during transportation and handling, which causes a decrease in mass productivity. Also, two layers of CCL (Cupper Cla), which is an adhesiveless polyimide casting material (thickness 40 μm)
80 when using a 1-layer wiring TAB tape of d Laminate)
Fine etching with a μm pitch is possible.

Further, as the material of the wiring layer, copper or a copper alloy (for example, Cu-Z) is used in terms of versatility, mass productivity and cost.
r alloy, Cu-Sn alloy, etc.) is desirable. Particularly, when importance is placed on strength and heat resistance, a copper alloy is suitable. The polyimide tape 102 has a base made of polyimide and has a thickness of 50 μm.
The thickness of 2a and 102b is 13 to 100 μm, and those having thermosetting or thermoplastic characteristics, specifically, epoxy resin type or polyimide resin type can be used.
The base thickness is preferably in the range of 25 to 75 μm. The reason is that the commercially available double-sided adhesive-attached polyimide tape has a base thickness of 25 to 75 μm and can satisfy general versatility and mass productivity. If the base thickness is less than 25 μm, it becomes soft and the waist becomes weak, making it difficult to handle. Also, 7
If it exceeds 5 μm, the stiffness becomes strong and it hardens, and it becomes difficult to handle.

In the semiconductor device completed in the state shown in FIGS. 4 and 5, the output lead 108 is connected to the ITO electrode 208 provided on the LCD panel 207 by using the anisotropic conductive film 110, as shown in FIG. It Also, the input lead 109
Is an electrode pattern 21 provided on the printed circuit board 209.
Soldered to 0. Further, the silicon resin 113 is replaced with Au.
The area around the bump 106 is filled to protect the connection portion. The LCD module is completed by the above.

Also in this configuration, the size of the TAB tape is set to be substantially the same as the size of the semiconductor chip 101, which is the LCD driving LSI, so that the connection structure can be downsized and the wiring length can be reduced to 1/3 of that of the conventional structure. As a result,
The transmission speed is improved and the self-inductance Ls can be suppressed to 1/3 or less. As a result, the amount of noise (Vn) generated in the power supply can be reduced to 1/3 or less.

FIG. 7 shows a modification of the connection structure shown in FIG. 5, and FIG. 8 shows a sectional view taken along line BB of FIG. 9 is a sectional view showing an LCD module formed by connecting the semiconductor device having the structure shown in FIG. 8 to an LCD panel. While the single-layer wiring TAB tape shown in FIGS. 4 and 5 has a chip size, the input lead 107 side is extended, the thickness of the printed board 204 is smaller than the thickness of the LCD panel 207, and the upper surface level is the printed board. A feature is that the TAB tape can be connected without trouble even if the 204 and the LCD panel 207 are different. As shown in FIG. 7, the TAB tape 112 in the portion of the input lead 107 is made wide by extending a predetermined length from the polyimide tape 102. Therefore, as shown in FIG. 9, the portion of the input lead 107 can be bent and connected to the electrode pattern 210 according to the uneven thickness of the printed circuit board 204 and the LCD panel 207, and the degree of freedom of connection is improved. To do.

In the connection structure of the TAB tape for LCD of the present invention described above, the electrolytic copper foil is used for the inner leads, the output leads, etc., but the softening temperature is 45.
42 alloy (Fe-42% N) with a thickness of 35 μm at 0 ° C. or higher
i alloy) foil can also be used. Further, in the above description, the polyimide-based resin is used for the double-sided adhesive, but a “epoxy resin-based + phenol resin-based” resin can also be used. Furthermore, as a polyimide tape with double-sided adhesive 104, the base thickness is 50 μm and the adhesive thickness is 13 μm.
However, instead of this, it is also possible to use only a 13 μm to 100 μm adhesive layer (thermosetting or thermoplastic epoxy resin type or polyimide type resin) having no base.

Further, in the above description, the description has been limited to the TAB tape for LCD, but the present invention is not limited to the LCD and its driving IC, and is applied to all semiconductor devices using the TAB tape. It is possible.

[0034]

EXAMPLE LC constructed as shown in FIGS. 3, 6 and 9
The present inventors conducted various tests on the D module according to the test items shown in the left column of FIG. As a result, the results shown in the right column of FIG. 10 were obtained. As is clear from FIG. 10, the defect occurrence rate was 0 for the number of test samples “25”, and it was confirmed that the reliability of the connection was extremely high.

As a result, the ASIC for the LCD drive circuit
High insulation resistance between wirings for (Application Specific Integrated Circuit) (1000 at temperature 85 ℃, humidity 85%)
It has become possible to obtain a highly reliable connection structure of fine wiring (pitch between wirings is 80 μm or less) with insulation resistance of 10 ⁹ Ω or more over time.

[0036]

As is apparent from the above, according to the connection structure of the present invention, the one-layer wiring TAB tape is attached to one surface with an adhesive and the semiconductor chip is attached to the other surface with an adhesive. Since the polyimide tape and the anisotropic conductive film which is temporarily adhered to the output lead portion of the one-layer wiring TAB tape are provided, the insufficient strength of the lead is compensated by the adhered polyimide tape, and the connection reliability is improved. It is possible to improve the sex. In addition, high insulation resistance can be provided between the leads, which facilitates fine wiring.

According to the connection method of the present invention, the inner lead regions other than the bumps of the one-layer wiring TAB tape are fixed to one side of a polyimide tape having adhesives on both sides, and the one-layer wiring TAB tape is fixed. Anisotropic conductive film is temporarily adhered to the output lead of, and the semiconductor chip is attached to a predetermined position of the polyimide tape, and then the inner lead and the electrode part of the semiconductor chip are gang-bonded to each other to form the first layer. The output lead of the wiring TAB tape is bonded to the connection partner by using the anisotropic conductive film, and the input lead of the one-layer wiring TAB tape is soldered to the connection partner. Since the lead part is fixed and the strength of the lead is reinforced and it is attached to the semiconductor chip in this state, flip chip Even when the connection is made, the lead is not deformed. In addition, high insulation resistance can be provided between the leads, which facilitates fine wiring.

[Brief description of the drawings]

FIG. 1 is a front sectional view showing an embodiment of a connection structure of a TAB tape according to the present invention.

FIG. 2 is an explanatory view showing a part of a manufacturing process of the TAB tape of FIG.

FIG. 3 is a cross-sectional view showing a state in which the semiconductor device completed as shown in FIG. 2 is mounted on an LCD module.

FIG. 4 is a plan view showing another embodiment of the TAB tape connection structure of the present invention.

FIG. 5 is a sectional view taken along line AA of FIG. 4;

6 is a cross-sectional view showing an LCD module formed by connecting the semiconductor device having the configuration of FIG. 5 to an LCD panel.

FIG. 7 is a plan view showing a modified example of the connection structure shown in FIG.

FIG. 8 is a sectional view taken along the line BB of FIG. 7;

9 is a cross-sectional view showing an LCD module formed by connecting the semiconductor device having the configuration shown in FIG. 8 to an LCD panel.

FIG. 10 is an explanatory diagram showing an effect of the present invention.

FIG. 11 is a plan view showing a connection structure of a conventional LCD TAB tape.

FIG. 12 is a sectional view taken along the line CC of FIG. 11;

13 is a cross-sectional view showing a state where the semiconductor device shown in FIG. 12 is mounted on an LCD module.

[Explanation of symbols]

 101 Semiconductor Chip 102 Polyimide Tape 102a, 102b Adhesive 103 TAB Tape 104, 112 Inner Lead 106 Au Bump 107 Input Lead 108 Output Lead 109 Polyamic Acid Layer 110 Anisotropic Conductive Film 111 Wiring Layer

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Gunichi Takahashi 3-1-1 Sukegawa-cho, Hitachi-shi, Ibaraki Hitachi Cable Co., Ltd.

Claims (6)

[Claims] 1. A semiconductor device in which inner leads of a one-layer wiring TAB tape are flip-chip connected to a semiconductor chip, and input / output leads of the one-layer wiring TAB tape are connected to an external circuit. A polyimide tape having one surface attached with an adhesive and the semiconductor chip attached to the other surface with an adhesive; and an anisotropic conductive film temporarily attached to the output lead portion of the one-layer wiring TAB tape. A connection structure for a TAB tape, which comprises: 2. The TAB tape connection structure according to claim 1, wherein the one-layer wiring TAB tape has a size substantially equal to a mounting area of the semiconductor chip. 3. The connection structure for a TAB tape according to claim 1, wherein the one-layer wiring TAB tape has a wiring layer having a thickness of 3 to 35 μm and a wiring material made of copper or a copper alloy. 4. The one-layer wiring TAB tape is obtained by laminating a wiring layer on one surface of a punched polyamic acid layer,
The connection structure of the TAB tape according to claim 2 or 3, wherein the connection structure has a polyimide structure. 5. The polyimide tape has a base thickness of 25 to 75 μm, and the adhesive has a thickness of 13 to 100 μm.
2. The connection structure for a TAB tape according to claim 1, wherein m and its material have thermosetting property or thermoplastic property. 6. A semiconductor device in which inner leads of a single-layer wiring TAB tape are flip-chip connected to a semiconductor chip, and input / output leads of the single-layer wiring TAB tape are connected to an external circuit. The inner lead regions other than the bumps are fixed to one side of a polyimide tape having adhesives on both sides, and an anisotropic conductive film is temporarily adhered to the output lead of the one-layer wiring TAB tape. After sticking on the polyimide tape at a predetermined position, the inner lead and the electrode part of the semiconductor chip are gang-bonded, and the output lead of the one-layer wiring TAB tape is connected to the other side by using the anisotropic conductive film. Bonding, and soldering the input lead of the one-layer wiring TAB tape to a connection partner. Connection method.