JP2003338180A - Semiconductor storage device - Google Patents

Abstract

(57) [Problem] To provide a semiconductor memory device capable of electrically switching a memory cell configuration from a normal single memory cell type to a twin memory cell type. SOLUTION: Row address signals RA <0:11> and / RA <corresponding to address signals A0 to A11 by a row address decoder 26 of a semiconductor memory device 10.
0:11>, the internal row address signals RAD <0:11>, / RAD in which the most significant bit and the least significant bit are replaced.
<0:11> is generated. In the twin cell mode, the most significant bit RA <1 not used in the row address signal
1> and / RA <11>, the least significant bits RAD <0> and / RAD <0> of the internal row address signal are simultaneously selected by the row address decoder 26, and the adjacent word lines 61 and 62 and the word line 63 are selected. , 64 are activated simultaneously.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of storing 1-bit storage data of storage information represented by binary information using two memory cells.

[0002]

2. Description of the Related Art D which is one of the typical semiconductor memory devices
RAM (Dynamic Random Access Memory) is usually 1
Since the structure of a memory cell for storing bit data is composed of one transistor and one capacitor, and the structure of the memory cell itself is simple, it is suitable for high integration and large capacity of semiconductor devices. Used in various electronic devices.

FIG. 13 shows a memory cell array in a DRAM in which a memory cell for storing 1-bit data is composed of one transistor and one capacitor (hereinafter, such a DRAM is referred to as a single memory cell type). FIG. 6 is a circuit diagram showing a configuration of memory cells arranged in a matrix.

Referring to FIG. 13, memory cell 100 is
It includes an N-channel MOS transistor N101 and a capacitor C101. N-channel MOS transistor N
101 is connected to the bit line BL and the capacitor C101, and the gate is connected to the word line WL. The other end of the capacitor C101 different from the connection end with the N-channel MOS transistor N101 is connected to the cell plate 110.

N-channel MOS transistor N101
Is driven by word line WL which is activated only during data writing and data reading, is turned on only during data writing and data reading, and is turned off otherwise.

The capacitor C101 stores binary information "1" and "0" depending on whether or not electric charges are accumulated. When data is written to the capacitor C101,
Bit line BL is precharged to power supply voltage Vcc or ground voltage GND in accordance with the write data. Then, the word line WL is activated to turn on the N-channel MOS transistor N101, and the bit line BL
Via N-channel MOS transistor N101 to 2
The voltage corresponding to the progress information "1" and "0" is the capacitor C1.
01 is applied. As a result, the capacitor C101 is charged / discharged, and data is written.

On the other hand, when data is read, bit line BL is precharged to voltage Vcc / 2 in advance. Then, the word line WL is activated to turn on the N-channel MOS transistor N101,
The bit line BL and the capacitor C101 are energized. As a result, a minute voltage change according to the charged state of the capacitor C101 appears on the bit line BL, and a sense amplifier (not shown) amplifies the minute voltage change to the voltage Vcc or the ground voltage GND. The voltage level on bit line BL corresponds to the state of the read data.

Here, in the memory cell of the DRAM, the charge of the capacitor C101 corresponding to the stored data leaks due to various factors and is gradually lost. That is, stored data is lost over time. Therefore, in the DRAM, when the data is read, a refresh operation of once reading and rewriting the data is executed before the voltage change of the bit line BL corresponding to the stored data cannot be detected.

Although this refresh operation is indispensable in DRAM, it is a drawback from the viewpoint of speeding up the operation. Therefore, by adopting a twin memory cell type memory configuration in which two memory cells are allocated to 1-bit stored data, the interval between refresh operations can be lengthened, and access to the stored data can be speeded up. Techniques that can do this are known.

FIG. 14 shows a twin memory cell type DRAM.
3 is a circuit diagram showing a configuration of memory cells arranged in a matrix on the memory cell array in FIG.

Referring to FIG. 14, in the memory cell in this DRAM, two memory cells 100A and 100B, which respectively store the storage data and the inverted data of the storage data, are assigned to the storage data of 1 bit. It has a twin memory cell type configuration. Memory cell 1
00A is an N-channel MOS transistor N102,
And a capacitor C102, and the memory cell 100B is
It includes an N-channel MOS transistor N103 and a capacitor C103.

N-channel MOS transistor N102
Is connected to one bit line BL of the bit line pair BL and / BL and the capacitor C102, and has a gate connected to the word line W.
It is connected to L _n (n is an even number of 0 or more). N channel M
The OS transistor N102 is driven by the word line WL _n which is activated only during data writing and data reading, and is turned on only during data writing and data reading, and is turned off otherwise.

N-channel MOS transistor N103
Is the other bit line / B of the bit line pair BL, / BL
It is connected to L and the capacitor C103, and the gate is connected to the word line WL _{n + 1} . N-channel MOS transistor N103 is driven by the word line WL _{n + 1} is activated at the same time as the word line WL _n, and ON time of data writing and during data reading only and OFF at other times.

The capacitors C102 and C103 store binary information "1" and "0" depending on whether or not they have accumulated charges.
Memorize The capacitor C103 is the capacitor C10.
The inversion data of the storage data stored in 2 is stored. The capacitor C102 has one end connected to the N-channel MOS transistor N102 and the other end connected to the cell plate 110.
Connected to. The capacitor C103 has one end connected to the N-channel MOS transistor N103 and the other end connected to the cell plate 110.

When 1-bit storage data is written to capacitors C102 and C103, bit line BL is precharged to either power supply voltage Vcc or ground voltage GND in accordance with the write data, and bit line BL and The bit line / BL is precharged to the other different voltage. Then, the word lines WL _n and WL _{n + 1} are simultaneously activated, so that the N-channel MOS transistor N10 is activated.
2, N103 are simultaneously turned on, a voltage corresponding to the storage data is applied to the capacitor C102 from the bit line pair BL via the N channel MOS transistor N102, and the bit line pair / BL to the N channel MOS transistor N10.
A voltage corresponding to the inversion data of the stored data is applied to the capacitor C103 via 3. As a result, 1-bit storage data is written in the capacitors C102 and C103.

On the other hand, when the stored data is read out, the bit line pair BL and / BL are both set to the voltage Vc in advance.
Precharged to c / 2. And word line W
Since L _n and WL _{n + 1} are activated at the same time, the N-channel MOS transistors N102 and N103 are simultaneously turned on.
Then, the bit line BL and the capacitor C102 are energized, and the bit line / BL and the capacitor C103 are energized. As a result, minute voltage changes in opposite directions appear on the bit line pair BL, / BL, and a sense amplifier (not shown) detects the potential difference between the bit line pair BL, / BL and amplifies it to the voltage Vcc or the ground voltage GND. This amplified voltage level corresponds to the state of the read stored data.

In this twin memory cell, since two memory cells are allocated to 1-bit data, the area of the memory cell is certainly 2 as compared with the conventional memory cell.
However, since the two memory cells store mutually inverted information, the amplitude of the potential difference between the bit line pair BL, / BL is large, the operation is stabilized, and the refresh operation interval is widened. It has the advantage of being able to.

Furthermore, the present twin memory cell type DR
In the AM, at the time of data reading, the bit line pair BL, / BL is used as in the single memory cell type DRAM described above.
Is precharged to a voltage of 1/2 Vcc, but in this case, when the stored data is read to the bit line pair BL, / BL, the voltages of the bit line pair BL, / BL change in opposite directions. , The single memory cell type D described above
Compared with the RAM, the amplitude of the voltage change on the bit line corresponding to the stored data is doubled, and the twin memory cell type DRAM also has an advantage that the data can be accessed at high speed during data reading.

[0019]

As described above, FIG.
14 and a single memory cell type DRAM shown in FIG.
The difference from the twin memory cell type DRAM shown in FIG. 3 is that only one memory cell or two memory cells are allocated to 1-bit storage data, and the basic structure of the memory cell is the same for both. Is. Therefore, in the manufacturing process of the semiconductor memory device, instead of making the single memory cell type and the twin memory cell type separately from the beginning, if the single memory cell type can be switched to the twin memory cell type during the manufacturing process, It is expected that the manufacturing cost can be reduced by reducing the manufacturing process and flexibly responding to orders.

Here, when the single memory cell type is switched to the twin memory cell type, it can be switched by switching the pattern of aluminum wiring in the wiring process, but in this method, it is necessary to divide the mask pattern, and
As a result, the mask process also differs, and the manufacturing cost cannot be reduced sufficiently.

On the other hand, if the semiconductor memory device can be electrically switched without structurally switching, the mask pattern can be unified in the single memory cell type and the twin memory cell type, and the mask process can be unified. The manufacturing cost can be greatly reduced.

Therefore, the present invention has been made to solve the above problems, and an object thereof is to provide a semiconductor memory device capable of switching a single memory cell type to a twin memory cell type in a memory cell configuration. An object of the present invention is to provide a semiconductor memory device that can be electrically switched.

[0023]

According to the present invention, a semiconductor memory device has a memory cell array including a plurality of memory cells arranged in a matrix, a plurality of word lines arranged in a row direction, and a column direction. Select a specific word line and a specific bit line pair from the plurality of word lines and the plurality of bit line pairs based on the plurality of bit line pairs arranged in a row and the address signal specifying each of the plurality of memory cells. When the twin cell mode signal for storing the storage data of 1 bit of the storage information represented by the binary information by using the two memory cells is activated, the decoder has two A word line and a bit line pair for activating the memory cell are selected, and the two memory cells store the stored data and the inverted data of the stored data, respectively.

Preferably, the decoder generates an internal row address signal for selecting a specific word line based on the address signal, and when the twin cell mode signal is activated, a predetermined bit of the internal row address signal is generated. A first word line corresponding to a logic level of the first logic level,
The second word line corresponding to the logic level of the predetermined bit at the second logic level is simultaneously selected.

Preferably, the predetermined bit is the least significant bit of the internal row address signal, and the decoder sets the most significant bit of the address signal that is not used when the twin cell mode signal is activated to the internal row address. Assign the least significant bit of the signal and the least significant bit of the address signal to the most significant bit of the internal row address signal.

Preferably, the semiconductor memory device, in the normal operation mode in which the twin cell mode signal is inactivated,
The storage capacity is 2 × n (n is a natural number) bits, and
When the word structure is 2 × m (m is a natural number) bits and the twin cell mode signal is activated, the storage capacity is n bits and the word structure is 2 × m bits.

Preferably, the semiconductor memory device further includes a refresh control circuit for periodically performing a refresh operation to hold stored information, and the refresh control circuit performs k (k is a natural number) refresh operations. The first refresh mode for completing the refresh of all the memory cells included in the memory cell array and
The refresh operation is executed in one of the second refresh modes in which the refresh operation of all memory cells included in the memory cell array is completed by the refresh operation of × k times, and the address signal selects the first and second refresh modes. The refresh mode selection bit for performing the operation is included in the most significant bit, the predetermined bit is the least significant bit of the internal row address signal, and the decoder assigns the refresh mode selection bit to the least significant bit of the internal row address signal. The least significant bit of is assigned to the most significant bit of the internal row address signal.

Preferably, the semiconductor memory device, in the normal operation mode in which the twin cell mode signal is inactivated,
The storage capacity is 2 × n (n is a natural number) bits, and
When the word structure is 2 × m (m is a natural number) bits and the twin cell mode signal is activated, the storage capacity is n bits and the word structure is m bits.

Preferably, the twin cell mode signal is externally input via a predetermined terminal.

Preferably, the semiconductor memory device further includes a fuse circuit for switching the logic level of the twin cell mode signal.

Preferably, the semiconductor memory device further includes a refresh control circuit for periodically performing a refresh operation to retain stored information, and the refresh control circuit selects a memory cell row to be refreshed. A refresh row address for designating is generated, and the refresh row address includes at least one partial self-refresh address bit for designating execution of a refresh operation targeting a partial region of the memory cell array, and the decoder is It includes a selection circuit for selecting at least one partial self refresh address bit from different refresh row addresses depending on whether the twin cell mode signal is activated or not.

Preferably, the refresh control circuit is k
(K is a natural number) The first refresh mode which completes the refresh of all the memory cells included in the memory cell array by the refresh operation and the refresh operation of 2 × k times refreshes all the memory cells included in the memory cell array. The refresh operation is executed in any of the second refresh modes that are completed, and the selection circuit
When the twin cell mode signal is inactivated and the refresh control circuit executes the refresh operation in the second refresh mode, at least a 1-bit portion from the refresh row address generated corresponding to the second refresh mode. Select the self-refresh address bit.

As described above, in the semiconductor memory device according to the present invention, the semiconductor memory device functioning as a normal single memory cell type is changed to the semiconductor memory device functioning as a twin memory cell type based on the twin cell mode signal. Switching is done electrically.

Therefore, according to the semiconductor memory device of the present invention, it is not necessary to switch the mask patterns to create different mask patterns, and it is possible to reduce the manufacturing cost by reducing the number of masks and the manufacturing process.

[0035]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts will be denoted by the same reference characters and description thereof will not be repeated.

[First Embodiment] FIG. 1 is a schematic block diagram showing an overall structure of a semiconductor memory device according to a first embodiment of the present invention.

Referring to FIG. 1, the semiconductor memory device 10 is
A control signal terminal 12, an address terminal 14, and a data input / output terminal 16 are provided. Further, the semiconductor memory device 10 is
The control signal buffer 18, the address buffer 20, and the input / output buffer 22 are provided. Further, the semiconductor memory device 10 includes a control circuit 24, a row address decoder 26,
A column address decoder 28, an input / output control circuit 30, a sense amplifier 32, and a memory cell array 34 are provided.

In FIG. 1, the semiconductor memory device 1
For 0, only the main part related to data input / output is representatively shown.

The memory cell array 34 is a memory element group in which memory cells are arranged in a matrix, and each of the memory cell arrays 34 is composed of four banks that can operate independently. Also, since the memory cell array 34 is composed of four banks,
Four sets of row address decoders 26, column address decoders 28, input / output control circuits 30, and sense amplifiers 32 are also provided.

Control signal terminal 12 receives command control signals such as chip select signal / CS, row address strobe signal / RAS, column address strobe signal / CAS and write enable signal / WE. The control signal buffer 18 has a chip select signal / CS, a row address strobe signal / RAS, and a column address strobe signal / CAS.
And write enable signal / WE to control signal terminal 12
It is taken in from, latched, and output to the control circuit 24.

The address terminal 14 has address signals A0 to A0.
An (n is a natural number) and bank address signals BA0,
Receive BA1. The address buffer 20 includes a row address buffer and a column address buffer (not shown). The row address buffer of the address buffer 20 includes address signals A0 to An and a bank address signal BA.
0 and BA1 are fetched and latched, and bank address signal B
Row address signals RA <0: n>, / RA to row address decoder 26 corresponding to the bank designated by A0 and BA1.
<0: n> (for any code X, X <0: n> is X
It represents <0> to X <n>. ) Is output. The column address buffer of the address buffer 20 includes address signals A0-An and bank address signals BA0, BA1.
Take in and latch, bank address signals BA0, BA
Column address decoder 2 corresponding to the bank indicated by 1
8 column address signals CA <0: n>, / CA <0: n>
Is output.

The data input / output terminal 16 is a terminal for exchanging data read / written in the semiconductor memory device 10 with the outside, and receives the data DQ0 to DQi (i is a natural number) input from the outside at the time of data writing. During data reading, data DQ0 to DQi are output to the outside. The I / O buffer 22 receives data DQ0 to DQi when writing data.
It fetches and latches, and outputs internal data IDQ to input / output control circuit 30. On the other hand, input / output buffer 22 outputs internal data IDQ received from input / output control circuit 30 to data input / output terminal 16 when reading data.

The control circuit 24 takes in the command control signal from the control signal buffer 18 and controls the row address decoder 26, the column address decoder 28 and the input / output buffer 22 based on the taken-in command control signal.

Row address decoder 26 receives row address signals RA <0: n>, / from the address buffer 20.
Signals RAD <0: n>, / R for selecting a word line on the memory cell array 34 based on RA <0: n>.
AD <0: n> is generated. Then, the row address decoder 26 outputs signals RAD <0: n> and / RAD <0: n>.
The row address is decoded based on the above, and the word line on the memory cell array 34 corresponding to the decoded row address is selected. Then, the selected word line is activated by a word driver (not shown).

The column address decoder 28 receives the column address signals CA <0: n received from the address buffer 20.
> / CA <0: n>, the column address is decoded, and the bit line pair on the memory cell array 34 corresponding to the decoded column address is selected.

When writing data, the input / output control circuit 30
The internal data IDQ received from the input / output buffer 22 is output to the sense amplifier 32, and the sense amplifier 32 outputs the column address decoder 2 according to the logic level of the internal data IDQ.
The bit line pair selected by 8 is precharged to the power supply voltage Vcc or the ground voltage GND. by this,
Writing the internal data IDQ to the memory cells on the memory cell array 34 connected to the word line activated by the row address decoder 26 and the bit line pair selected by the column address decoder 28 and precharged by the sense amplifier 32. Is performed.

On the other hand, when reading data, the sense amplifier 32
Precharges the bit line pair selected by the column address decoder 28 to the voltage Vcc / 2 before data reading, and detects / amplifies a minute voltage change generated in the selected bit line pair corresponding to read data. Then, the logical level of the read data is determined and output to the input / output control circuit 30.
Then, input / output control circuit 30 outputs the read data received from sense amplifier 32 to input / output buffer 22.

As described above, the memory cell array 34 is composed of four banks each of which can operate independently, and each bank of the memory cell array 34 has a word line arranged in a row direction on the bank. Is connected to the row address decoder 26, and is also connected to the sense amplifier 32 via a bit line pair arranged on the bank in the column direction.

FIG. 2 is a circuit diagram showing a configuration of memory cells arranged in a matrix on memory cell array 34 of semiconductor memory device 10. In FIG. 2, among the memory cells arranged on the memory cell array 34, four memory cells adjacent in the row direction are shown.

Referring to FIG. 2, memory cell 340 has N
The memory cell 341 includes a channel MOS transistor N0 and a capacitor C0, and the memory cell 341 includes an N-channel MOS transistor N1 and a capacitor C1.
Is an N-channel MOS transistor N2 and a capacitor C
2 and the memory cell 343 includes an N-channel MOS transistor N3 and a capacitor C3.

N channel MOS transistor N0 is connected to bit line BL and capacitor C0, and has its gate connected to word line WL0. N channel MOS transistor N0 is driven by word line WL0 activated only during data writing and data reading, and is turned on only during data writing and data reading, and is turned off otherwise.

The capacitor C0 stores binary information "1" and "0" depending on whether or not electric charge is accumulated. The capacitor C0 has one end connected to the N-channel MOS transistor N0 and the other end connected to the cell plate 77. Then, charges are exchanged with bit line BL via N-channel MOS transistor N0, and data writing / reading is performed with respect to capacitor C0.

N channel MOS transistor N1 is connected to bit line / BL and capacitor C1 and has its gate connected to word line WL1. N-channel MOS transistor N1 is driven by word line WL1 which is activated only during data writing and data reading, and is turned on only during data writing and data reading, and is turned off otherwise.

The capacitor C1 stores binary information "1" and "0" depending on whether or not electric charge is accumulated. The capacitor C1 has one end connected to the N-channel MOS transistor N1 and the other end connected to the cell plate 77. Then, charges are exchanged with bit line / BL via N-channel MOS transistor N1, and data writing / reading is performed on capacitor C1.

N-channel MOS transistor N2 is connected to bit line / BL and capacitor C2, and has its gate connected to word line WL2. N channel MOS transistor N2 is driven by word line WL2 which is activated only during data writing and data reading, and is turned on only during data writing and data reading, and is turned off otherwise.

The capacitor C2 stores binary information "1" and "0" depending on whether or not electric charge is accumulated. The capacitor C2 has one end connected to the N-channel MOS transistor N2 and the other end connected to the cell plate 77. Then, charges are exchanged with bit line / BL via N channel MOS transistor N2, and data writing / reading is performed with respect to capacitor C2.

N channel MOS transistor N3 is connected to bit line BL and capacitor C3, and has its gate connected to word line WL3. N channel MOS transistor N3 is driven by word line WL3 which is activated only during data writing and data reading, is turned on only during data writing and data reading, and is turned off otherwise.

The capacitor C3 stores binary information "1" and "0" depending on whether or not electric charges are accumulated. The capacitor C3 has one end connected to the N-channel MOS transistor N3 and the other end connected to the cell plate 77. Then, charges are exchanged with the bit line BL via the N-channel MOS transistor N3, and data writing / reading is performed with respect to the capacitor C3.

When semiconductor memory device 10 functions as a single memory cell type semiconductor memory device, 1 bit of data is stored in each of memory cells 340-343. Then, the memory cells 340 to 343
When writing / reading data to / from each of the above, the corresponding word lines WL0 to WL3 are activated and the bit line BL or bit line / to which the memory cell is connected.
Charges are exchanged with BL.

On the other hand, when semiconductor memory device 10 functions as a twin memory cell type semiconductor memory device, adjacent memory cells 340 and 341 store one bit of data, and adjacent memory cells 342 and 342. 343
One bit of data is stored at. Memory cell 341
Stores data in which the logical level of the storage data of the memory cell 340 is inverted, and the memory cell 343 stores data in which the logical level of the storage data of the memory cell 342 is inverted.

When data is written to memory cells 340 and 341 forming a twin memory cell, bit line BL is precharged to a predetermined voltage corresponding to the stored data, and the stored data is also stored. The bit line / BL is precharged to a predetermined voltage corresponding to the inverted data of. Then, the word lines WL0 and WL1 are simultaneously activated, the charge corresponding to the storage data is supplied from the bit line BL to the capacitor C0, and the charge corresponding to the inverted data of the storage data is supplied from the bit line / BL to the capacitor C1.
Is supplied to.

When data is written to memory cells 342 and 343 forming a twin memory cell, bit line BL is precharged to a predetermined voltage corresponding to the stored data, and the stored data is stored. The bit line / BL is precharged to a predetermined voltage corresponding to the inverted data of. Then, the word lines WL2 and WL3 are simultaneously activated, the charge corresponding to the storage data is supplied from the bit line BL to the capacitor C2, and the charge corresponding to the inverted data of the storage data is supplied from the bit line / BL to the capacitor C3. Supplied.

As described above, when the semiconductor memory device 10 is used as a twin memory cell, the bit line pair BL,
Data which are inverted to each other are written in / BL and adjacent word lines are simultaneously activated, so that two memory cells adjacent in the row direction store 1-bit data.

FIG. 3 is a diagram conceptually illustrating the structure of the memory area in each bank of memory cell array 34. In the following description, the semiconductor memory device 1
When 0 operates as a normal single memory cell type semiconductor memory device, it functions as a semiconductor memory device having a memory capacity of 128 M (mega) bits and a word structure of “× 32”. That is, the semiconductor memory device 10
Is used as a normal single memory cell type,
The most significant bit of the address signal An is A11 (n = 11)
Is.

Referring to FIG. 3, each of the banks of memory cell array 34 is made up of regions 51 to 56, and all the regions have 3 banks.
It has a storage capacity of 2 Mbits (= 128 Mbits / 4 banks). Each bank of the memory cell array 34 has 8
192 word lines are arranged, and the signal RAD <
A predetermined word line is selected based on 0:11>, / RAD <0:11>. The row address signal RA <0:
11> and / RA <0:11> are signals corresponding to address signals A0 to A11 instructed from the outside, and row address signals RA <11> and / RA <11> are the most significant bits of the row address. And the row address signal RA
<0> and / RA <0> represent the least significant bit of the row address.

Memory areas 51 to 53 and memory area 5
4 to 56 have the same memory configuration and the signal RAD <
Based on 0:11> and / RAD <0:11>, the word lines at the same location in each region are selected relatively.

The areas 51 and 52 and the areas 54 and 55 are
Selected by the logic level of the signal / RAD <11>,
Regions 53 and 56 are selected by the logic level of signal RAD <11>. When the areas 51, 52 and the areas 54, 55 are selected by the signal / RAD <11>, the areas 51, 54 are selected according to the logic level of the signal / RAD <10>, and the areas 52, 55 are selected. Is the signal R
It is selected according to the logic level of AD <10>. Similarly, signals RAD <0:11>, / RAD <0:11>
A more subdivided region is selected by the lower bits of the signals, and finally signals RAD <0:11>, / RAD <0:
The word line designated by 11> is selected.

Here, in this semiconductor memory device 10, row address signals RA <0:11>, / RA <0: 1.
1> based on the signals RAD <0:11>, / RAD <
When generating 0:11>, the row address signal RA <0: 1
1>, / RA <0:11> with the most significant bit and the least significant bit interchanged to generate signals RAD <0:11>, / RAD
<0:11> is generated. That is, the most significant bits RA <11> and / RA <11> of the row address are signal RAD.
<0:11>, / RAD The least significant bit R of <0:11>
AD <0> and / RAD <0> are assigned respectively, and the least significant bits RA <0> and / RA <0> of the row address are the highest bits of the signals RAD <0:11> and / RAD <0:11>. Bits RAD <11> and / RAD <11> are respectively assigned.

The storage capacity is 64 Mbits,
When the semiconductor memory device 10 functions as a twin memory cell type semiconductor memory device having a word structure of “× 32”,
When the signals RAD <0:11>, / RAD <0:11> are generated, the least significant bits RAD <0>, / RAD <0
> Is always selected. As a result, the adjacent word lines 61 and 62 and the word lines 63 and 64 are simultaneously selected as shown in FIG. 3, and the adjacent memory cells are simultaneously selected as described in FIG. 2 to form a twin memory cell. To be done.

When the semiconductor memory device 10 functions as a twin memory cell type semiconductor memory device having a memory capacity of 64 Mbits and a word structure of "× 32",
The most significant bit of the row address signal is RA <10>, / RA
<10> and row address signals RA <11>, / RA
Since <11> is not used, the row address signal RA <1
1>, / RA <11> corresponding signals RAD <0>, /
Even if RAD <0> is rewritten inside the semiconductor memory device 10, there is no problem in address specification.

In FIG. 4, RAD <0 for generating the least significant bits RAD <0>, / RAD <0> of signals RAD <0:11>, / RAD <0:11> included in row address decoder 26. > Is a circuit diagram showing a circuit configuration of a generation circuit.

Referring to FIG. 4, the RAD <0> generation circuit receives NAND cell 7 receiving twin cell mode signal / TWIN and the most significant bit RA <11> of the row address.
1 and the output of the NAND gate 71 are inverted to obtain the signal RAD.
Inverter 72 that outputs <0>, twin cell mode signal / TWIN, and most significant bit of row address / RA
A NAND gate 73 receiving <11> and an inverter 74 inverting the output of NAND gate 73 and outputting a signal / RAD <0>.

The twin cell mode signal / TWIN is a signal whose logic level becomes L (logical low) level when the semiconductor memory device 10 functions as a twin cell memory type semiconductor memory device. At the time of manufacture, its logic level is set depending on whether the signal line of the twin cell mode signal / TWIN is wired to the power supply node or the ground node. When the twin cell mode signal / TWIN is at L level, NAND
The gates 71 and 73 have row address signals RA <1 respectively.
1>, / RA <11> regardless of the logic level of the H level signal, the least significant bit RAD <
0> and / RAD <0> are both selected (the least significant bits RAD <0> and / RAD <0> are selected at the L level).

In the above description, the twin cell mode signal / TWIN is generated by switching the bonding of the signal line, but it may be set as one of the commands given from the outside. Alternatively, a dedicated terminal may be provided. Alternatively, a twin circuit mode signal / TWIN may be set by providing a fuse circuit inside and depending on whether or not the fuse element of the fuse circuit is cut during manufacturing.

As described above, according to semiconductor memory device 10 of the first embodiment, adjacent word lines are simultaneously activated in response to a twin cell mode signal, so that a single memory cell type semiconductor memory device can be used. Since switching to the twin memory cell type semiconductor memory device is performed electrically, there is no need to switch mask patterns to create different mask patterns in the mask process step, reducing the number of masks,
It is possible to reduce the manufacturing cost by reducing the manufacturing process.

[Second Embodiment] The semiconductor memory device 10 according to the first embodiment has a storage capacity of 128 Mbits,
Further, it is possible to switch from a single memory cell type semiconductor memory device having a word structure of “× 32” to a twin memory cell type semiconductor memory device having a storage capacity of 64 Mbits and a word structure of “× 32”. However, the semiconductor memory device 10A according to the second embodiment further has a storage capacity of 64M.
It is possible to switch to a twin memory cell type semiconductor memory device which is a bit and has a word structure of “× 16”.

As described above, the refresh operation is indispensable in the DRAM, and during the refresh operation,
In each of the memory cells to be refreshed,
Data reading, amplification and rewriting are executed, and the stored data is retained. This refresh operation is executed for each word line arranged on the memory cell array, and its operation cycle (hereinafter referred to as a refresh cycle) is the refresh interval and the number of word lines which can guarantee the retention of data in each memory cell. Is determined in consideration of.

Referring again to FIG. 3, when the refresh operation is performed in each bank of memory cell array 34 in semiconductor memory device 10 according to the first embodiment, address signals A0-A1 received by address terminal 14 are received.
Row address signal RA <0:11 generated based on 1
, / RA <0:11>, the 4096 word lines in each of the regions 51 to 53 and the regions 54 to 56 are respectively the regions 51 to 53 and the regions 54 to 56.
Are sequentially activated in. That is, refreshing of all memory cells is completed by 4096 refresh operations (hereinafter, a case where 4096 refresh operations are required until the refreshing of all memory cells is completed is referred to as “4K refresh”, which will be described later. In area 5
The case where all 8192 word lines of 1 to 56 are sequentially activated and 8192 refresh operations are required until the refresh of all memory cells is completed is called "8K refresh". ).

Semiconductor memory device 10A according to the second embodiment
Is compatible with 8K refresh, and in order to sequentially select 8192 word lines, row address signal RA <
12> and / RA <12> are further provided. In the refresh operation, the row address signal RA <0: 1
2>, / RA <0:12>, 8192 word lines are sequentially activated in each bank of the memory cell array 34, and refresh of all memory cells is completed in 8192 times.

In the semiconductor memory device 10A, the most significant bits RA <12> and / RA <12> are signaled to the signal RAD.
<0:12>, / RAD least significant bit R of <0:12>
When the semiconductor memory device 10A is assigned to AD <0> and / RAD <0> and functions as a twin memory cell type semiconductor memory device, the semiconductor memory device 10 according to the first embodiment is used.
Similarly, the least significant bits RAD <0>, / RAD <0>
By activating all of the
It also functions as a semiconductor memory device that is a bit and has a word structure of “× 16”.

The reason why this can be done is that the storage capacity is 64 Mbits and the word structure is "× 16".
When the semiconductor memory device 10A functions as a twin memory cell type semiconductor memory device, the most significant bits of the row address signal are RA <11>, / RA <11>, and the row address signal RA <12>, / RA <11>. Since RA <12> is not used, row address signals RA <12> and / RA <12> are used.
This is because even if the signals RAD <0> and / RAD <0> corresponding to are rewritten inside the semiconductor memory device 10A, there is no problem in address specification.

Semiconductor memory device 10A according to the second embodiment
Since the overall configuration of is the same as that of semiconductor memory device 10 according to the first embodiment shown in FIG. 1, description thereof will not be repeated.

FIG. 5 is a diagram conceptually illustrating a memory area in each bank of memory cell array 34 of semiconductor memory device 10A.

Referring to FIG. 5, in each of the banks of memory cell array 34 in semiconductor memory device 10A, regions 51 to 53 are compared to the banks of memory cell array 34 in semiconductor memory device 10 shown in FIG. Further selected by the logic level of signal / RAD <12>, regions 54-56 are further selected by the logic level of signal RAD <12>.

Here, in semiconductor memory device 10A, row address signals RA <0:12>, / RA <0: 1.
2> based on the signals RAD <0:12>, / RAD <
When generating 0:12>, the row address signal RA <0: 1
2>, / RA <0:12>, the most significant bit and the least significant bit are interchanged to generate signals RAD <0:12>, / RAD.
<0:12> is generated. That is, the most significant bits RA <12> and / RA <12> of the row address are signal RAD.
<0:12>, / RAD least significant bit R of <0:12>
AD <0> and / RAD <0> are respectively assigned, and the least significant bits RA <0> and / RA <0> of the row address are the highest bits of the signals RAD <0:12> and / RAD <0:12>. Bits RAD <12> and / RAD <12> are respectively assigned.

The memory capacity is 64 Mbits,
Further, when the semiconductor memory device 10A functions as a twin memory cell type semiconductor memory device having a word structure of “× 16”, when signals RAD <0:12> and / RAD <0:12> are generated, Least significant bit RAD <0>, / RAD
All of <0> are always selected. As a result, as shown in FIG. 5, adjacent word lines 61 and 62 and word lines 63 and 64 are simultaneously selected, and adjacent memory cells are simultaneously selected to form a twin memory cell.

As described above, according to semiconductor memory device 10A of the second embodiment, the most significant bit RA <12> of the row address signal provided for 8K refresh,
Adjacent word lines can be activated at the same time by using / RA <12>. Therefore, a single memory cell type semiconductor memory device has a storage capacity of 64 Mbits and a word structure of “× 16”. Switching to the twin memory cell type semiconductor memory device can also be electrically performed.

[Third Embodiment] The semiconductor memory device according to the third embodiment is the same as the semiconductor memory device 10 according to the second embodiment.
A has a self-refresh function, and further has a so-called partial self-refresh function capable of refreshing only a part of the memory area.

As described above, during the refresh operation,
In each of the memory cells to be refreshed,
Data reading, amplification and rewriting are performed periodically,
Stored data is retained. This refresh operation is executed for each word line.

In the self refresh,
A row address for selecting a word line to be refreshed is internally generated to perform a refresh operation. In partial self-refresh, upper 1 of row address
The logical level of the bit or the upper 2 bits is, for example, L
The refresh operation is executed only in the level memory area.

Therefore, in the partial self refresh, in order to properly refresh a predetermined part of the area, the semiconductor memory device functions as a single memory cell type semiconductor memory device or a twin memory cell type semiconductor memory device. It is necessary to associate the most significant bit of the row address with the refresh space in the partial self refresh depending on whether it functions as a device or corresponds to 8K refresh.

FIG. 6 is a schematic block diagram showing the overall structure of a semiconductor memory device according to the third embodiment of the present invention.

Referring to FIG. 6, the semiconductor memory device 11 is
In addition to the semiconductor memory device 10A according to the second embodiment, a refresh control circuit 36 is further provided. The refresh control circuit 36 includes a self-refresh control circuit 38,
A refresh address generation circuit 40 is included.

The refresh control circuit 36 is the control circuit 2
4 based on the instruction from the row address (hereinafter, refresh row address signal / QAD
It is referred to as <0: n>. ) Is generated and output to the row address decoder 26. Row address decoder 26 receives a row address signal RA <received from address buffer 20 in normal operation based on an instruction from control circuit 24.
Word lines in the memory cell array 34 are selected based on 0: n> and / RA <0: n>. On the other hand, in the self-refresh mode, row address decoder 26 selects a word line in memory cell array 34 based on refresh row address signal / QAD <0: n> from refresh control circuit 36.

The self-refresh control circuit 38 generates a refresh signal QCU based on a pulse signal generated by a transmission circuit (not shown), and the generated refresh signal QCU is refresh address generation circuit 40.
Output to. The refresh signal QCU is activated at a predetermined refresh cycle that is determined in consideration of a refresh interval capable of guaranteeing data retention in each memory cell in the memory cell array 34 and the number of word lines in the memory cell array 34. To be done.

The refresh address generation circuit 40 updates the refresh row address in response to the refresh signal QCU and sequentially switches the memory cell rows to be refreshed. Specifically, the refresh row address signal / QAD <0: n> is incremented according to the refresh signal QCU.

As described above, in semiconductor memory device 11 according to the third embodiment, in order to further reduce the power consumption in the standby mode, the refresh operation is performed for all memory areas in the self-refresh mode. Instead, it has a so-called partial self-refresh function for performing a refresh operation on a part of the memory area.

In this partial self refresh, in each bank of the memory cell array 34,
Only the memory area in which the upper 1 bit or the upper 2 bits of the refresh row address signal / QAD <0: n> is L level is refreshed. This makes it possible to reduce power consumption in the standby mode without increasing the refresh cycle.

The semiconductor memory device 11 functions as a normal single memory cell type semiconductor memory device, functions as a twin memory cell type semiconductor memory device, and has an 8K refresh function. The most significant bit of different row addresses in
According to each usage mode, it is appropriately allocated to the refresh space of the partial self refresh.

FIG. 7 is a functional block diagram for functionally explaining refresh address generating circuit 40 shown in FIG.

Referring to FIG. 7, refresh address generating circuit 40 includes refresh address counters 401 to 401.
412 are included. The refresh address counter 401 corresponding to the least significant bit counts up according to the refresh signal QCU output from the self-refresh control circuit 38 and outputs the count data as a refresh row address signal / QAD <0>.

Refresh address counters 402-4
Each of 12 performs count-up according to the count data output from the refresh address counter on the lower bit side, and outputs the count data as refresh row address signals / QAD <1> to / QAD <11>, respectively.

In this way, during self refresh,
Refresh row address signal / QAD <for sequentially selecting each memory cell row at every predetermined refresh cycle
0:11> is generated.

FIG. 8 shows the refresh address counter 4
It is a circuit diagram which shows the circuit structure of 01-412.

Referring to FIG. 8, refresh address counters 401 to 412 each have inverters 82 and 86 for inverting an input signal, and are activated when the logic level of the input signal is L level to receive the output signal. An inverter 81 that inverts the output of the inverter 81, inverters 83 and 84 that form a latch circuit that latches the output of the inverter 81, and an inverter that is activated when the logic level of the input signal is the H level and receives the output of the inverter 81 85, a NAND gate 87 whose input node is connected to the power supply node and the output node of the inverter 85,
And an inverter 88 that constitutes a latch circuit that inverts and latches the output of the inverter 85.

Refresh address counters 401 to 4
In each of 12, the inverter 81 is activated and the output of the inverter 81 becomes H level when the input signal is L level when the logic level of the output signal is L level. On the other hand, at this stage, the inverter 85 is not activated, and the output of the inverter 81 is
Is not transmitted to the output node of.

Then, when the logic level of the input signal becomes H level, inverter 81 is inactivated, but the output of inverter 81 is latched by inverters 83 and 84. On the other hand, the inverter 85 is activated, and the inverter 85 inverts the H level input and outputs the L level signal. Therefore, the NAND gate 87 outputs an H level signal, and its output is the NAND gate 87.
And latched by inverter 88.

Then, when the logic level of the input signal becomes L level, inverter 81 is activated and inverter 8
The output of 1 becomes L level. On the other hand, the inverter 85 is deactivated, and the output of the inverter 81 is
Is not transmitted to the output node of.

Next, when the logic level of the input signal becomes H level, inverter 81 is inactivated, but the output of inverter 81 is latched by inverters 83 and 84. On the other hand, the inverter 85 is activated, and the inverter 85 inverts the L level input and outputs the H level signal. Therefore, the NAND gate 87 outputs an L level signal, and its output is the NAND gate 87.
And latched by inverter 88.

As described above, each of the refresh address counters 401 to 412 outputs an output signal in which the cycle of the input signal is halved, whereby the refresh row address signal / QAD <0:11> counts up. Will be done.

FIG. 9 is a circuit diagram showing a circuit configuration of an address selection circuit included in row address decoder 26. The address selection circuit receives the row address signal RA <0:11> from the address buffer 20 in response to the self-refresh mode signal QADSEL received from the control circuit 24.
And refresh row address signal / QAD <0:11
> Is selected and output as a signal RAD <0:11>.

Note that, in FIG. 9, for the sake of explanation, each input bit and output signal other than the self-refresh mode signal QADSEL are collectively displayed, and each bit is also shown in the following explanation. The data will be described as a combined signal, but in reality, a circuit is provided corresponding to each bit data.

Referring to FIG. 9, the address selection circuit includes an inverter 91 which receives and inverts row address signals RA <0:11>, and a self-refresh mode signal QADSE.
An inverter 94 which receives L and inverts, and is activated when the self-refresh mode signal QADSEL is at H level, refresh row address signal / QAD <0:11.
> Is inverted to output the signal RAD <0:11>, and the self-refresh mode signal QADSE.
It is composed of an inverter 92 which is activated when L is at L level, inverts the output of the inverter 91 and outputs the signal RAD <0:11>.

Self-refresh mode signal QADSE
L is a signal which becomes H level in the self refresh mode, and is generated by the control circuit 24.

When the self-refresh mode signal QADSEL is at H level, the address selection circuit outputs a signal obtained by inverting the refresh row address signal / QAD <0:11> as a signal RAD <0:11>. On the other hand, the address selection circuit outputs the row address signal RA <0:11> as the signal RAD <0:11> when the self-refresh mode signal QADSEL is at L level.

The circuits shown in FIGS. 10 to 12 are circuits included in the row address decoder 26, and the upper bits of the row address are associated with the refresh space of the partial self refresh according to the usage mode of the semiconductor memory device 11. It is a circuit for. FIG. 10 is a circuit diagram showing a configuration of a circuit for selecting an upper bit next to the most significant bit of a row address according to a use mode. FIG. 11 shows
It is a circuit diagram showing a configuration of a circuit for selecting the most significant bit of a row address according to a usage mode. FIG. 12 is a circuit diagram showing a configuration of a circuit for generating a self-refresh stop signal for stopping the self-refresh operation.

Here, the use mode includes the normal mode in which the semiconductor memory device 11 functions as a normal single memory cell type semiconductor memory device and the twin mode in which the semiconductor memory device 11 functions as a twin memory cell type semiconductor memory device. There are a cell mode and an 8K refresh mode when the semiconductor memory device 11 performs an 8K refresh operation.

In the normal mode, the most significant bit of the refresh row address is / QAD <11>, and in the twin cell mode, the most significant bit of the refresh row address is / QAD <10>, and 8K refresh is performed. In mode, the most significant bit of the refresh row address is /
QAD <12>.

Referring to FIG. 10, this circuit includes an inverter 10 which receives and inverts twin cell mode signal TWIN.
2, and when the twin cell mode signal TWIN is at the H level, the refresh row address signal / QAD <
9> and an inverter 101 which receives and inverts the signal, and an inverter 10 which receives and inverts the 8K refresh mode signal 8K.
4 and 8K is activated when the refresh mode signal 8K is at H level, and refresh row address signal / QAD
An inverter 103 that receives <11> and inverts it, and an inverter 10 that receives and inverts the normal mode signal NORMAL
6, and when the normal mode signal NORMAL is at H level, the refresh row address signal / QAD <1 is activated.
0> receiving and inverting the inverter 105, receiving the outputs of the inverters 101, 103 and 105, inverting the inverter 107, receiving the output of the inverter 107 and inverting and outputting the signal QAD <10>. Become.

This circuit is a signal in which the refresh row address signal / QAD <9> is inverted when the semiconductor memory device 11 functions as a twin memory cell type semiconductor memory device and the twin cell mode signal TWIN is at the H level. Is output as a signal QAD <10>. Further, in this circuit, the semiconductor memory device 11 operates with 8K refresh,
When the 8K refresh mode signal 8K is at H level, a signal obtained by inverting the refresh row address signal / QAD <11> is output as the signal QAD <10>. Further, this circuit is a signal in which the refresh row address signal / QAD <10> is inverted when the semiconductor memory device 11 functions as a normal single memory cell type semiconductor memory device and the normal mode signal NORMAL is at the H level. Is output as a signal QAD <10>.

Referring to FIG. 11, this circuit includes an inverter 11 which receives and inverts twin cell mode signal TWIN.
2, and when the twin cell mode signal TWIN is at the H level, the refresh row address signal / QAD <
10> and an inverter 111 which receives and inverts the 8K refresh mode signal 8K.
14 and 8K is activated when the refresh mode signal 8K is at H level, and refresh row address signal / QA
An inverter 113 that receives and inverts D <12>, and an inverter 1 that receives and inverts the normal mode signal NORMAL
16 and is activated when the normal mode signal NORMAL is at H level, and the refresh row address signal / QAD <
11> receiving and inverting, an inverter 117 receiving and inverting the outputs of the inverters 111, 113 and 115, and an inverter 118 receiving and inverting the output of the inverter 117 and outputting a signal QAD <11>. Become.

This circuit is a signal in which the refresh row address signal / QAD <10> is inverted when the semiconductor memory device 11 functions as a twin memory cell type semiconductor memory device and the twin cell mode signal TWIN is at the H level. Is output as a signal QAD <11>. Further, in this circuit, the semiconductor memory device 11 operates with 8K refresh,
When the 8K refresh mode signal 8K is at H level, a signal obtained by inverting the refresh row address signal / QAD <12> is output as the signal QAD <11>. Further, this circuit is a signal in which the refresh row address signal / QAD <11> is inverted when the semiconductor memory device 11 functions as a normal single memory cell type semiconductor memory device and the normal mode signal NORMAL is at the H level. Is output as a signal QAD <11>.

Referring to FIG. 12, this circuit uses the signal SE
LF_1MSB, signal SELFREF and signal QAD
NAND gate 123 receiving <11> and signal QAD
NAND gate 12 receiving <11> and QAD <10>
1, an inverter 122 that receives and inverts the output of the NAND gate 121, an output of the inverter 122, and a signal SE
NA that receives LFREF and signal SELF_2MSB
The ND gate 124 and the input gate are the power supply node and N
The NAND gate 125 connected to the output nodes of the AND gates 123 and 124, and the output of the NAND gate 125 are inverted to receive the self-refresh stop signal SELF.
And an inverter 126 that outputs _STOP.

Signal SELF_1MSB is a mode signal corresponding to the refresh mode in which the self refresh is performed only in the memory region in which the most significant bit of the refresh row address signal is at the L level in the partial self refresh. Signal SELF_2MSB is a mode signal corresponding to a refresh mode in which, in partial self refresh, only the memory area in which the most significant bit and the next upper bit of the refresh row address signal are both at the L level is self-refreshed. Signal SELFREF is a signal that becomes H level when partial self refresh is performed. All of these signals are generated by the control circuit 24.

Self refresh stop signal SELF_S
TOP is output to the control circuit 24, and when the self-refresh stop signal SELF_STOP is at H level,
The control circuit 24 stops the refresh operation. on the other hand,
If the self-refresh stop signal SELF_STOP is at the L level during the self-refresh operation, the control circuit 24 instructs execution of the refresh operation.

In this circuit, the signal SELFREF
When both the signal SELF_1MSB and the signal SELF_1MSB are at the H level (the signal SELF_2MSB is at the L level),
When the signal QAD <11> is at H level, the output of the NAND gate 123 becomes L level and the self-refresh stop signal SELF_STOP becomes L level. Therefore, the refresh operation is executed in the memory area in which the most significant bit of refresh row address signal / QAD is at the L level. On the other hand, the signal QAD <11> is L
At the level, the output of the NAND gate 123 becomes the H level, and the self-refresh stop signal SELF_ST
OP becomes H level. Therefore, the refresh operation is not executed in the memory area in which the most significant bit of refresh row address signal / QAD is at the H level.

In addition, the signal SELFREF and the signal SE
When both LF_2MSB are at H level (signal S
ELF_1 MSB becomes L level), signal QAD <1
If both 1> and QAD <10> are H level, N
The output of the AND gate 124 becomes L level, and the self-refresh stop signal SELF_STOP becomes L level. Therefore, the refresh row address signal / QAD
Both the most significant bit and the next higher bit are L
A refresh operation is executed in the memory area which is the level. On the other hand, the signals QAD <11> and QAD <1
When at least one of 0> is L level, the output of the NAND gate 124 becomes H level and the self-refresh stop signal SELF_STOP becomes H level. Therefore, the refresh operation is not executed in the memory region in which neither the most significant bit of refresh row address signal / QAD nor the next higher bit is L level.

As described above, according to semiconductor memory device 11 of the third embodiment, even if the most significant bit of the row address differs depending on the usage mode, a part of the refresh operation is executed in the partial self refresh. Since the predetermined memory area can be selected, the partial self refresh is appropriately executed in each usage mode.

The embodiments disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the claims, and is intended to include meanings equivalent to the claims and all modifications within the scope.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing an overall configuration of a semiconductor memory device according to a first embodiment.

FIG. 2 is a circuit diagram showing a configuration of memory cells arranged in a matrix on the memory cell array shown in FIG.

FIG. 3 is a diagram conceptually illustrating a configuration of a memory area in each bank of the memory cell array shown in FIG.

4 is an R included in the row address decoder shown in FIG. 1;
It is a circuit diagram which shows the circuit structure of an AD <0> generation circuit.

FIG. 5 is a diagram conceptually illustrating a structure of a memory region in each bank of the memory cell array of the semiconductor memory device according to the second embodiment.

FIG. 6 is a schematic block diagram showing an overall configuration of a semiconductor memory device according to a third embodiment.

7 is a functional block diagram for functionally explaining the refresh address generation circuit shown in FIG.

FIG. 8 is a circuit diagram showing a circuit configuration of the refresh address counter shown in FIG.

9 is a circuit diagram showing a circuit configuration of an address selection circuit included in the row address decoder shown in FIG.

FIG. 10 is a circuit diagram showing a configuration of a circuit for selecting an upper bit next to a most significant bit according to a usage mode.

FIG. 11 is a circuit diagram showing a configuration of a circuit for selecting a most significant bit according to a usage mode.

FIG. 12 is a circuit diagram showing a configuration of a circuit that generates a self-refresh stop signal for stopping a self-refresh operation.

FIG. 13 is a circuit diagram showing a configuration of memory cells arranged in a matrix on a memory cell array in a single memory cell type DRAM.

FIG. 14 is a circuit diagram showing a configuration of memory cells arranged in a matrix on a memory cell array in a twin memory cell type DRAM.

[Explanation of symbols]

10, 10A, 11 semiconductor memory device, 12 control signal terminal, 14 address terminal, 16 data input / output terminal,
18 control signal buffers, 20 address buffers, 2
2 input / output buffer, 24 control circuit, 26 row address decoder, 28 column address decoder, 30 input / output control circuit, 32 sense amplifier, 34 memory cell array, 36 refresh control circuit, 38 self refresh control circuit, 40 refresh address generation circuit, 51-56 regions, 61-64, WL0-WL3,
WL _n , WL _{n + 1} word lines, 71, 73, 87, 12
1,123-125 NAND gate, 72,74 inverter, 77,110 cell plate, 100,10
0A, 100B memory cells, 401-412 refresh address counters, 81-86, 88, 91-9
4, 101-108, 111-118, 122, 126
Inverter, N0-N3, N101-N103 N-channel MOS transistor, C0-C3, C101-C1
03 Capacitor, BL, / BL bit line pair.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hideki Yoneya             2-3 2-3 Marunouchi, Chiyoda-ku, Tokyo             Inside Ryo Electric Co., Ltd. (72) Inventor Tsutomu Nagasawa             2-3 2-3 Marunouchi, Chiyoda-ku, Tokyo             Inside Ryo Electric Co., Ltd. (72) Inventor Masato Suwa             2-3 2-3 Marunouchi, Chiyoda-ku, Tokyo             Inside Ryo Electric Co., Ltd. (72) Inventor Masashige Ta             Daioden 1-132 Ogino, Itami City, Hyogo Prefecture             Machine Co., Ltd. (72) Inventor Tadaaki Yamauchi             2-3 2-3 Marunouchi, Chiyoda-ku, Tokyo             Inside Ryo Electric Co., Ltd. (72) Inventor Junko Matsumoto             2-3 2-3 Marunouchi, Chiyoda-ku, Tokyo             Inside Ryo Electric Co., Ltd. F term (reference) 5M024 AA91 BB07 BB28 BB35 BB36                       BB39 DD62 DD63 EE05 EE30                       HH10 KK10 PP01 PP02 PP03

Claims (10)

[Claims] 1. A memory cell array including a plurality of memory cells arranged in a matrix, a plurality of word lines arranged in a row direction, a plurality of bit line pairs arranged in a column direction, and the plurality of memories. And a decoder that selects a specific word line and a specific bit line pair from the plurality of word lines and the plurality of bit line pairs based on an address signal that specifies each cell, and is represented by binary information. When the twin cell mode signal for storing the storage data of 1 bit of the storage information using two memory cells is activated, the decoder is a word line for activating the two memory cells. And a bit line pair are selected, and the two memory cells store the storage data and inverted data of the storage data, respectively. 2. The decoder generates an internal row address signal for selecting the specific word line based on the address signal, and when the twin cell mode signal is activated, the internal row address is generated. A first word line corresponding to the logic level of a predetermined bit of the signal at the first logic level and a second word line corresponding to the logic level of the predetermined bit of the signal at the second logic level are simultaneously selected;
The semiconductor memory device according to claim 1. 3. The predetermined bit is the least significant bit of the internal row address signal, and the decoder is the most significant bit of the address signal that is unused when the twin cell mode signal is activated. 3. The semiconductor memory device according to claim 2, wherein is assigned to the least significant bit of the internal row address signal, and the least significant bit of the address signal is assigned to the most significant bit of the internal row address signal. 4. In the normal operation mode in which the twin cell mode signal is inactivated, the storage capacity is 2 × n (n is a natural number) bits and the word structure is 2 × m (m is a natural number). 4. The semiconductor memory device according to claim 3, wherein the semiconductor memory device is a bit, the memory capacity is n bits and the word structure is 2 × m bits when the twin cell mode signal is activated. 5. The memory device further comprises a refresh control circuit for periodically performing a refresh operation to hold the stored information, wherein the refresh control circuit performs the refresh operation k (k is a natural number) times. In a first refresh mode in which the refresh of all memory cells included in the memory cell array is completed and in a second refresh mode in which the refresh of all memory cells included in the memory cell array is completed by 2 × k refresh operations. The refresh operation is executed, and the address signal includes a refresh mode selection bit for selecting the first and second refresh modes in a most significant bit, and the predetermined bit is a least significant bit of the internal row address signal. The decoder is configured to 3. The semiconductor memory device according to claim 2, wherein the mode selection bit is assigned to the least significant bit of the internal row address signal, and the least significant bit of the address signal is assigned to the most significant bit of the internal row address signal. 6. The normal operation mode in which the twin cell mode signal is inactivated, the storage capacity is 2 × n (n is a natural number) bits and the word structure is 2 × m (m is a natural number). 6. The semiconductor memory device according to claim 5, wherein the semiconductor memory device is a bit, the memory capacity is n bits, and the word structure is m bits when the twin cell mode signal is activated. 7. The semiconductor memory device according to claim 1, wherein the twin cell mode signal is externally input via a predetermined terminal. 8. The semiconductor memory device according to claim 1, further comprising a fuse circuit for switching a logic level of said twin cell mode signal. 9. A refresh control circuit for periodically executing a refresh operation to hold the stored information, the refresh control circuit for designating a memory cell row to be the target of the refresh operation. Of the refresh row address, the refresh row address includes at least one partial self-refresh address bit for designating execution of the refresh operation targeting a partial region of the memory cell array, and the decoder is 2. The semiconductor memory device according to claim 1, further comprising a selection circuit that selects the at least one partial self-refresh address bit from the different refresh row address depending on whether the twin cell mode signal is activated or not. . 10. The refresh control circuit comprises k (k
Is a natural number) refresh operation of all memory cells included in the memory cell array is completed in the first refresh mode, and refresh operation of 2 × k times refreshes all memory cells included in the memory cell array. The refresh operation is executed in any one of the second refresh modes to be completed, the selection circuit is configured to inactivate the twin cell mode signal, and the refresh control circuit is configured to perform the refresh operation in the second refresh mode. 10. The semiconductor memory device according to claim 9, wherein when performing an operation, said at least one partial self-refresh address bit is selected from said refresh row address generated corresponding to said second refresh mode.