JPH0786607A - Thin film transistor - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to provide a thin film transistor capable of suppressing power consumption to be low, reducing a leak current, and increasing an ON / OFF ratio. [Structure] The N-channel TFT 1 includes a drain electrode 2, a gate electrode 4, a source electrode 6, a semiconductor layer 8, and a photovoltaic device 12. The semiconductor layer has a source region 3 and a drain region 5 which are N-type doped, and a channel region 7 which is located between the source region 3 and the drain region 5, and a voltage is applied between the source and drain electrodes. In this case, a minute leak current flows in the channel region. When a voltage is applied to the gate electrode in this state, electrons are attracted in the channel region and an ON current flows between the electrodes. The photovoltaic device has a function of blocking the backlight 11 incident on the channel region, converting the absorbed backlight into a voltage, attracting holes to the channel region, and reducing a leak current.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (hereinafter referred to as TFT) used as a switching element of, for example, an active matrix type liquid crystal display.

[0002]

2. Description of the Related Art As a display element using a liquid crystal, a large-capacity, high-density active matrix type liquid crystal display intended for a television display or a graphic display has been actively developed and put into practical use. With such an indicator,
Semiconductor switches are used as means for driving and controlling each pixel so that high-contrast display without crosstalk can be performed. As the semiconductor switch, a TFT formed on a transparent insulating substrate is usually used for the reason that a transmissive display is possible and the area can be easily increased.

The TFT has, for example, a staggered structure in which a source layer, a drain electrode layer, and a gate layer are respectively arranged in a lower layer with a semiconductor layer sandwiched therebetween, and each TFT of an active matrix type liquid crystal display device. It is provided for each pixel. In each TFT, the drain electrode is formed integrally with the signal electrode of the liquid crystal display, the gate electrode is formed integrally with the scanning electrode, and the source electrode is connected to the pixel electrode.

When the liquid crystal display thus constructed is driven, a constant scanning voltage Vg is applied to the gate electrode of the TFT via the scanning electrodes for each scanning line, and at the same time, the voltage Vds as an image signal is supplied. Corresponds to TF via signal electrode
Applied to the drain electrode of T. In this way, when the gate voltage Vg is applied to the gate electrode of the TFT to which the voltage Vds is applied between the source and drain electrodes, the electric charge attracted by the voltage Vg is applied to the source and drain regions of the semiconductor layer. Occurs in the channel region sandwiched between the two, the electric resistance of the channel region becomes low, a current Ids (ON current) flows in the channel region, and the switch of the corresponding pixel is turned on. In addition, TFT
Is an N-channel TFT that attracts electrons into the channel region, and a P-channel TF that attracts holes.
There is T.

On the other hand, the switch is in the OFF state (Vg = 0)
A small amount of OFF current (leak current) flowing through the semiconductor layer flows between the source and drain electrodes of the TFT in FIG. ON current and OF flowing in the channel region of TFT
The ON / OFF ratio with the F current is usually required to be 10 ⁶ or more, and this ON / OFF ratio is TF
It is an important factor in evaluating the performance of T. Therefore, T
In order to increase the ON / OFF ratio of the FT and improve the performance, it is necessary to keep the leak current low.

FIG. 5 shows an N-channel TFT source,
Apply a constant voltage Vds (15V) between the drain electrodes,
The current Ids flowing between the source and drain regions (channel region) of the semiconductor layer when a gate voltage Vg is applied to the gate electrode is shown. The source and drain regions of the semiconductor layer are of N-type so as to conform to the N-channel type.
It is assumed that

When a small positive voltage Vg is applied to the gate electrode of the N-channel type TFT, electrons are attracted in the channel region, and the current Ids (ON is flowing in the channel region.
Current) increases significantly. For example, a voltage of 20 V
When applied to the gate electrode, an ON current of about 10 ⁻⁵ A flows. On the other hand, when the gate voltage Vg = 0, the leak current is about 10 ^-10 A. Turning on the TFT in this case
The / OFF ratio is about 10 ⁵ and does not reach the required value (10 ⁶ ).

Generally, a T having a good ON / OFF ratio
In order to obtain FT, a reverse voltage (negative voltage in this case) is applied to the gate electrode in the OFF state of the TFT to suppress the leak current low. That is, when a negative voltage is applied to the gate electrode of the N-channel type TFT, holes are attracted to the channel region, but the flow of holes is the N-type doped source.
Block in the drain and drain regions, resulting in
Current can be reduced. Therefore, the conventional N-channel type T
A voltage of about -5 V is applied to the gate electrode of the FT, the leak current is suppressed to about 10 ^-12 , and the ON / OFF ratio of the TFT is raised to about 10 ⁶ .

The TFT mounted on the liquid crystal display is
The leak current may increase due to the influence of the backlight of the display. That is, when the light from the backlight is absorbed in the channel region of the TFT, electric charges may be generated in the channel region to lower the electric resistance of the channel region. When the electric resistance is low as described above, the charge easily flows, and as a result, the leak current is increased. Therefore, a light shielding layer for shielding the light absorbed in the channel region is provided.

[0010]

In the conventional TFT, the leak current is suppressed by applying a reverse voltage to the gate electrode in the OFF state. Therefore, although the TFT is in the OFF state, it is necessary to apply an extra voltage for suppressing the leak current to a low level, which causes a problem that power consumption increases.

The present invention has been made in view of the above points, and an object thereof is to provide a thin film transistor capable of reducing a leak current with a small power consumption and increasing an ON / OFF ratio. .

[0012]

According to the present invention, a so-called
In a thin film transistor having a gate electrode, a drain electrode, a semiconductor layer, an insulating layer, and a gate electrode, a photovoltaic device that blocks light entering the channel region of the semiconductor layer and applies an electric field to the channel region. There is provided a thin film transistor comprising:

[0013]

According to the thin film transistor (TFT) of the present invention, the photovoltaic device is provided at the optical path position where the backlight of the liquid crystal display enters the channel region of the semiconductor layer of the TFT. The photovoltaic device suppresses the generation of charges in the channel region by blocking the light incident on the channel region, and suppresses the leak current in the OFF state to be low.
Also, the light absorbed by the photovoltaic device is converted here into a voltage, which gives an electric field to the channel region. By appropriately selecting the direction of the applied electric field, either electrons or holes are attracted into the channel region to suppress the leak current. Then, a TFT having a good ON / OFF ratio is provided.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings. As shown in FIGS. 1 and 2,
The thin film transistor 1 (hereinafter, referred to as TFT) of the present invention is attached to each pixel 30 of the active matrix type liquid crystal display 20, and is used as a switching element of the pixel 30, for example.

The liquid crystal display 20 has a display screen in which a large number of pixels 30 are arranged in a matrix. Each pixel 30 includes a pixel electrode 22, a number of signal electrodes 24 extending in parallel with each other along the pixel electrode 22, and a number of scanning electrodes 26 extending in parallel along a direction orthogonal to the signal electrode 24. is doing. Each pixel electrode 22 is connected to the signal electrode 24 and the scanning electrode 26 via, for example, a stagger type TFT 1. The liquid crystal display 20 also includes a backlight (not shown).

Each TFT 1 includes a drain electrode 2 formed integrally with the signal electrode 24, a gate electrode 4 formed integrally with the scanning electrode 26, and a source electrode 6 connected to the pixel electrode 22. , The signal electrode 24 acts as a data line for giving an image signal to the drain electrode 2 of the TFT 1, and the scanning electrode 26 gives a scanning signal to the gate electrode 4 of the TFT 1. Acts as an address line for.

The structure of the TFT 1 will be described in detail below. The TFT 1 is formed on the upper surface of a base 10 made of transparent glass or quartz, and the photovoltaic device 4 provided on the upper surface of the base 10 and the upper surface of the base 10 so as to cover the photovoltaic device 4. A transparent insulating layer 14, a source electrode layer 6 and a drain electrode layer 2 provided on the upper surface of the insulating layer 14 so as to be separated from each other, and an upper surface of the insulating layer 14 that is in contact with the source electrode 6 and the drain electrode 2. The semiconductor layer 8 provided in
And the gate insulating layer 16 provided on the upper surface of the semiconductor layer 8.
And the gate electrode 4 provided on the upper surface of the gate insulating layer 16.
And are equipped with.

The semiconductor layer 8 includes a source region 3 located above the source electrode 6, a drain region 5 located above the drain electrode 2, and between the source electrode 6 and the drain electrode 2. It is divided into three regions consisting of the located channel region 7. The source region 3 and the drain region 5 are doped in order to reduce the specific resistance of the source region 3 and to achieve a good ohmic contact with the contacting electrode.
Be pushed. For example, when these regions 3 and 5 are N-type doped, an N-channel type TFT is formed and a P-type is doped.
Then, a P-channel type TFT is formed.

The photovoltaic device 4 includes a TFT 1 through a lower surface of the substrate 10 from a backlight (not shown) of the liquid crystal display 20.
The light acts as a light shielding layer for preventing the light 11 incident on the channel 11 from entering the channel region 7, and also has the function of converting the absorbed light into a voltage.

Next, an N channel type TF is provided for each pixel 30.
The operation of the liquid crystal display 20 equipped with T1 will be described. First, when an image signal is input to the liquid crystal display 20, the image signal is given to the drain electrode 2 of each TFT 1 within one scanning line via the signal electrode 24. The image signal includes an ON signal that applies a voltage to the drain electrode 2 and an O signal that does not apply a voltage.
The TFT1 which is binarized into the FF signal and the ON signal is supplied with the voltage Vds between the source and drain electrodes, and the TFT1 which is supplied with the OFF signal is supplied with the voltage Vds.
ds is not added. At the same time, a scanning signal is applied to the gate electrodes 4 of all the TFTs 1 within this one scanning line via the scanning electrodes 26, and a constant gate voltage Vg is applied. Then, the TFT 1 to which the voltage Vds is applied is turned on by being applied with the gate voltage Vg,
The corresponding pixel 30 is displayed. Similarly, the above operation is performed for all the scanning lines in the display screen to form one screen.

The TFT 1 to which the ON signal as a display command is given to the drain electrode 2 produces a voltage Vds between the source electrode 6 and the drain electrode 2, and is put in a standby state (OFF state). The source region 3 and the drain region 5 of the semiconductor layer 8 are N-type doped and pass the current well, but since the channel region 7 is not doped, the resistivity is high and the current flows. It is hard to pass. Therefore, the TFT 1 in the OFF state has O between the electrodes 2 and 6 via the semiconductor layer 8.
A minute leak current as an FF current is flowing.

When a scanning signal is applied to the gate electrode 4 of the N-channel TFT 1 in the OFF state and a predetermined positive gate voltage Vg is applied, electrons are attracted into the channel region 7 and the channel region 7 Resistivity is reduced. As a result, the electrons pass well in the channel region 7, and the ON current Ids flows between the source electrode 6 and the drain electrode 2. When an ON current flows between the electrodes 2 and 6, the TFT
1 is turned on, and a voltage is generated between the pixel electrode 22 of the corresponding pixel 30 and the counter electrode (not shown) via the source electrode 6. As a result, the orientation of the liquid crystal (not shown) is changed so that the liquid crystal is brought into a display state.

In order to obtain a high performance TFT 1, the above O
It is desirable to increase the ON / OFF ratio between the N current and the OFF current (leak current). Therefore, the TFT of the present invention
In the case of No. 1, the photovoltaic device 12 is provided at the position where the light shielding layer is conventionally provided, so that the leak current is suppressed to a low level.
Increase the ON / OFF ratio of FT1.

FIG. 3 shows an amorphous silicon Schottky barrier solar cell 40 as a first embodiment of the photovoltaic device 12.
(Hereinafter referred to as Schottky solar cell). The Schottky solar cell 40 has a two-layer structure including a metal region 42 and a light absorption region 44. The metal region 42 is formed in a thin film shape of about 100 angstroms and is semitransparent so that the maximum light incident from the lower surface 42a can reach the light absorption region 44. The light absorption region 44 is the lower surface 4 that contacts the upper surface 42b of the metal region.
4a, and is formed from a semiconductor material such as amorphous silicon or crystalline silicon.

In the field of semiconductor manufacturing, it is known that a Schottky barrier can be formed by bringing a metal material into contact with the semiconductor material. In the Schottky solar cell of this embodiment, the metal region 42 and the light absorption region 44 are formed. A Schottky barrier is formed on the boundary surface 42b (44a) of the. The Schottky barrier can be formed by contacting a metal having a high work function with an N-type semiconductor material, or by contacting a metal having a low work function with a P-type semiconductor material. By forming the Schottky barrier, a space charge region is generated in the light absorption region 44 from the boundary surface 42b (44a) toward the upper surface 44b of the light absorption region 44.

Metal region 42 of Schottky solar cell 40
When light is incident on the Schottky barrier from the lower surface 42a of the above, charge carriers are generated in the light absorption region 44, and the charge carriers are normally generated by the electric field in the space charge region. The upper surface 44b of the light absorption region is removed. However, like the Schottky solar cell 40 included in the TFT 1 of the present invention, when it is surrounded by the substrate 10 and the insulating layer 14 as an electrically insulating material, the charge carriers generated in the vicinity of the Schottky barrier. Are accumulated in the light absorption region 44.

For example, as in this embodiment, the light absorption region 4
4 is formed of an N-type semiconductor material, and the metal region 42 is formed of a metal having a high work function such as platinum or palladium.
When light is applied to the barrier, electrons are generated in the light absorption region 44. The generated electrons are accumulated in the light absorption region 44 and generate an electric field. Then, due to this electric field, holes are attracted into the channel region 7 of the semiconductor layer 8 and the channel region 7
It becomes difficult for electrons to pass inside. Therefore, the TFT
When 1 is in the OFF state, the current resistance of the channel region 7 becomes large, and the leak current is reduced.

FIG. 4 shows a PIN solar cell 50 as a second embodiment of the photovoltaic device 12. The PIN solar cell 50 has a P-type semiconductor layer 52 that has a lower surface 52a on which light is incident and is doped in a P-type, and an intermediate layer 54 that has a lower surface 54a that contacts the upper surface 52b of the P-type semiconductor layer 52. , A lower surface 56a contacting the upper surface 54b of the intermediate layer 54
N-type semiconductor layer 56 having N-type and doped with N-type
And has a three-layer structure.

As a result of homogenizing the Fermi level of each layer 52, 54, 56, positive space charge carriers are generated in the N-type semiconductor layer 56 and negative space charge carriers are generated in the P-type semiconductor layer 52. It is well known in the field of PIN solar cell manufacturing that an intrinsic electrical potential is created at the interface between these layers 52, 54 and 54, 56. The space charge region generated in the intermediate layer 54 is considered to exist over the entire thickness of the intermediate layer 54. Therefore, the charge carriers generated in the intermediate layer 54 by absorbing light are focused by the electric field of the space charge region regardless of the polarity of the charge carriers.

For example, the PIN solar cell 50 is provided with a TFT so that light is incident from the direction of the lower surface 52a of the P-type semiconductor layer 52.
When the light is incident on the PIN solar cell 50, the electrons are accumulated in the intermediate layer 54 and holes are attracted to the channel region 7 of the semiconductor layer 8 when the light is incident on the PIN solar cell 50.
Current is reduced.

As described above, by providing the photovoltaic device 12 at the position of the light shielding layer included in the conventional TFT, from the backlight of the liquid crystal display 20 to the semiconductor layer 8 of the TFT 1.
Protects the channel region 7 and absorbs the backlight to apply a desired electric field to the channel region 7 to attract desired charge carriers into the channel region 6,
It is possible to reduce the leak current when the TFT is in the OFF state. As a result, the same effect as in the case of applying a reverse voltage to the gate electrode of the TFT in order to suppress the leak current as in the conventional case can be obtained. Therefore, the leak current can be suppressed to a low level with low power consumption, and the ON / OFF ratio can be increased.

The present invention is not limited to the above embodiments, but can be variously modified without departing from the scope of the invention. For example, as another embodiment of the photovoltaic device 12,
A PN junction solar cell or a heterojunction solar cell may be used, and the structure of the TFT may be an inverted staggered structure, a coplanar structure, or an anticoplanar structure in addition to the staggered structure of this embodiment.

[0033]

As described above, according to the thin film transistor of the present invention, the photovoltaic device is provided at the position of the light shielding layer which shields the backlight incident on the channel region. Therefore, while protecting the channel region from the backlight, it is possible to convert the absorbed light into a voltage and apply a desired electric field to the channel region, reduce the current resistance of the channel region and keep the leak current low. become. Then, ON / OFF of the ON current and the OFF current of the TFT
The OFF ratio can be increased, and a TFT having high performance can be provided.

[Brief description of drawings]

FIG. 1 is a sectional view showing a thin film transistor in an embodiment of the present invention.

FIG. 2 is a partial plan view showing a liquid crystal display equipped with the TFT of FIG.

FIG. 3 is a Schottky circuit included in the TFT of FIG.
Sectional drawing which shows a barrier solar cell.

FIG. 4 is a cross-sectional view showing a PIN solar cell included in the TFT of FIG.

FIG. 5 is a diagram showing a current Ids flowing between a source electrode and a drain electrode when a gate voltage Vg is applied to a gate electrode of a conventional N-channel TFT.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Thin film transistor, 2 ... Drain electrode, 3 ... Source region, 4 ... Gate electrode, 5 ... Drain region, 6 ... Source electrode, 7 ... Channel region, 8 ... Semiconductor layer, 10 ... Substrate, 11 ... Backlight light, 12 ... Photovoltaic device.

Claims (8)

[Claims] 1. A source electrode, a drain electrode, a semiconductor layer,
A thin film transistor including an insulating layer and a gate electrode is provided with a photovoltaic device that blocks light incident on a channel region of the semiconductor layer and applies an electric field to the channel region. Thin film transistor. 2. The thin film transistor according to claim 1, wherein the semiconductor layer is formed of amorphous silicon or crystalline silicon. 3. The thin film transistor according to claim 1, wherein the thin film transistor has one of a stagger structure, an inverted stagger structure, a coplanar structure, and an anticoplanar structure. 4. The thin film transistor according to claim 1, wherein the thin film transistor is formed into an N channel type or a P channel type. 5. The thin film transistor according to claim 1, wherein the photovoltaic device is a Schottky barrier solar cell. 6. The thin film transistor according to claim 1, wherein the photovoltaic device is a PIN solar cell. 7. The thin film transistor according to claim 1, wherein the photovoltaic device is a PN junction solar cell. 8. The thin film transistor according to claim 1, wherein the photovoltaic device is a heterojunction solar cell.