JPH0782746B2 - Dynamic RAM - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a dynamic RAM (random access memory), for example, a technology effective when used for a continuous data read. is there.

[Background technology]

As a dynamic RAM, a column address buffer,
There has been developed a column address selection circuit such as a column address decoder configured by a so-called static type circuit that does not utilize temporary charge accumulation. In this dynamic RAM, the row address is fixed,
When the column address is sequentially switched, the memory cell can be selected according to it. However, in this static column type RAM, when the write enable signal is at the high level, the data output buffer is automatically activated and a signal is sent from the data output terminal Dout. For this reason, it cannot be used in a memory system in which the input terminal Din and the output terminal Dout are connected to a common external data bus, so that its use is limited.

[Object of the Invention]

An object of the present invention is to provide a dynamic RAM having a variety of output functions with a simple structure.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Outline of Invention]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. In other words, in the static column type dynamic RAM,
Of the address signals multiplexed and supplied via the common external terminal, it is formed by a timing identification circuit that identifies the supply timing of the address strobe signal and the write enable signal transmitted to the internal circuit as the column address signal. The identification output indicating that the write enable signal is supplied at a timing earlier than the address strobe signal inhibits the operation of the data output buffer regardless of the write enable signal.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of a dynamic RAM according to the present invention.

In the embodiment circuit shown in the figure, an IGFET (Insulated Gate Field Effect Transistor) typified by an N-channel MOSFET is used.
tor) as an example.

The 1-bit memory cell MC has an address selection MOSFET Qm and one electrode thereof, as shown as a representative.
It consists of an information storage capacitor Cs which is connected to Qm and the other electrode of which is maintained at the power supply voltage level of the circuit. The information of logic "1" and "0" corresponds to whether the capacitor Cs has a charge or not. Will be remembered.

To read information, turn on the MOSFET Qm, connect the capacitor Cs to the common data line DL, and sense how the potential of the data line DL changes according to the amount of charge accumulated in the capacitor Cs. Done by

Although not particularly limited, a dummy cell DC is provided as a reference for detecting such a minute signal. The dummy cell DC is made under the same manufacturing conditions and the same design constants as the memory cell MC, except that the capacitance value of the capacitor Cd is almost half that of the capacitor Cs of the memory cell MC. The capacitor Cd receives the timing signal φd generated prior to the addressing, and is charged to the power supply voltage by the MOSFET Qd ′ arranged between the capacitor Cd and the ground point of the circuit. As described above, the capacitor Cd is set to have a capacitance value that is about half that of the capacitor Cs, so that it forms a reference voltage that is approximately half the read signal from the memory cell MC.

In the figure, SA is a sense amplifier that expands such a potential change difference caused by the addressing to a sense period determined by a timing signal (sense amplifier control signal) φpa, and is a pair of complementary data arranged in parallel. Line D
The input / output node is connected to L, ▲ ▼. This sense amplifier SA is composed of a pair of cross-connected MOSFETs Q1, Q2.
, And by these positive feedback actions, the complementary data line DL,
The small signal appearing in ▲ ▼ is amplified differentially.

The number of memory cells coupled to the complementary data lines DL, ▲ ▼ is made equal to increase the detection accuracy, and one dummy cell is coupled to each of DL and ▲ ▼. Each memory cell MC is coupled between one word line WL and one of the complementary pair data lines. Since each word line WL intersects with both data line pairs, even if the noise component generated in the word line WL is on the data line due to electrostatic coupling, the noise component is generated in both data line pairs DL, ▲ ▼. And appear to be canceled by the differential sense amplifier SA.

In the above addressing, complementary data line pair DL, ▲
One of the pair of dummy word lines DWL, ▲ ▼ is selected so that when the memory cell MC coupled to one of the ▼ is selected, the dummy cell DC is always coupled to the other data line.

During the above addressing, the stored information in the memory cell MC which is about to be destroyed is restored by directly receiving the high level or low level potential obtained by the sensing operation. However, if the high level falls below a certain level with respect to the power supply voltage Vcc as described above, a malfunction occurs where it is read as a logic "0" during repeated reading and rewriting. The active restore circuit AR is provided to prevent this malfunction. This active restore circuit AR
Has a function of selectively boosting the voltage of the power supply voltage Vcc to only the high level signal without affecting the low level signal by the timing signal φrs.

Data line pair DL, which is shown as a representative in the figure, ▲
▼ is connected to the common complementary data line pair CDL, ▲ ▼ through MOSFTEQ3 and Q4 which form the column switch CW. For the data line pairs shown as other representatives, the common complementary data line pair CDL,
Connected to ▲ ▼. This common complementary data line pair CD
L and ▲ ▼ are connected to one terminal of an input / output circuit I / O composed of a data output buffer including a main amplifier and an output circuit and a data input buffer as described later.

The row decoder and column decoder R, C-DCR receives an internal complementary address signal formed by the row address buffer and column address buffer R, C-ADB, and receives one word line, dummy word line, and column switch selection signal. Are formed to address the memory cells and the dummy cells. That is, the row address strobe signal ▲
The row address buffer R-ADB takes in the address signals AX0 to AXn supplied through the external terminals in synchronization with the timing signal .phi.ar formed by .tau., Holds them, and transmits them to the row decoder R-DCR. Row decoder R
-DCR decodes the transmitted address signal and performs a predetermined word line / dummy word line selection operation according to the word line selection timing signal φx.

On the other hand, the column address buffer C-ADB is composed of a static type circuit which is activated by a timing signal .phi.ac generated by the column address strobe signal (). As a result, an internal complementary address signal according to the address signals AY0 to AYn supplied through the external terminals is formed and transmitted to the column decoder C-DCR which is also formed by a static type circuit. The column decoder C-DCR decodes the transmitted address signal and performs a data line selection operation according to the data line selection timing signal φy.

The timing control circuit TC receives the row address strobe signal ▲ ▼, the column address strobe signal ▲ ▼ and the write enable signal ▲ ▼ supplied through the external terminals, and forms the various internal timing signals. In this embodiment, in order to diversify the output function of the RAM, the timing control circuit TC is provided with the following timing identification and control circuit.

FIG. 2 shows a logic circuit diagram of an embodiment of the timing identification and control circuit.

In this embodiment, since two kinds of write modes are set, the write enable signal ▲ ▼ (or the internal signal generated by the write enable signal ▲ ▼) is an edge trigger type flip-flop circuit FF.
Is supplied to the input terminal D of. In addition, the column address strobe signal ▲ ▼ (or an internal signal formed by the column address strobe signal ▲ ▼) may be the clock terminal CK of the flip-flop circuit FF.
Is supplied to. The flip-flop circuit FF takes in the signal supplied to the input terminal D in synchronization with the edge where the timing signal supplied to the clock terminal CK changes from high level to low level.
Therefore, the flip-flop circuit FF performs a timing discrimination operation based on the change timing of the column address strobe signal ▲ ▼ to the low level as a reference before determining whether or not the write enable signal ▲ ▼ has been changed to the low level. Become.

The output signal Q of the flip-flop circuit FF is supplied to one input terminal of the AND gate circuit G as its control signal. The other input terminal of the AND gate circuit G is supplied with the operation control timing core rw ′ of the data output buffer DOB formed according to the level of the write enable signal WE. The timing signal φrw supplied to the data output buffer DOB is sent from the output terminal of the gate circuit G.

Next, an example of the operation will be described with reference to the timing chart shown in FIG.

When the row address strobe signal ▲ ▼ changes from the high level to the low level, a timing signal φar (not shown) is formed, and the address signal supplied from the external terminal is used as the row address signal AX in the row address buffer R-.
Take it into ADB and keep it. The fetched address signal is supplied to the row decoder R-DCR. The row decoder R-DCR decodes the address signal to form a selection signal for one word line and a dummy word line corresponding thereto, and performs its selection operation in synchronization with a word line selection timing signal φx (not shown). To do. After that, the timing signals φpa1 and φpa2 (not shown) of the sense amplifier are formed, and the operation of amplifying the stored information of the memory cell read to the complementary data line DL, ▲ ▼ is performed.

Next, when the column address strobe signal ▲ ▼ changes from the high level to the low level, a timing signal φac (not shown) is formed, and the column address buffer C-ADB fetches the address signal supplied from the external terminal as the column address signal. . Since the address buffer C-ADB is composed of a static type circuit, it is activated by the timing signal .phi.ac while the column address strobe signal ▲ ▼ remains low level. Therefore, as soon as the address signal of the external terminal is switched, in response to this, an internal complementary address signal is formed and supplied to the column decoder C-DCR.

The column decoder C-DCR is a column address buffer C.
Decode the internal complementary address signal supplied from ADB to form the data line select signal. As a result, the selected data line and the common data line are connected.

Although not shown, if the write enable signal ▲ ▼ remains at high level, the data lines are switched one after another in accordance with the switching of the address signal. Therefore, the stored information of the memory cells coupled to the selected data line is stored. Are read one after another.

As shown by the solid line in the figure, the write enable signal ▲ is delayed after the column address strobe signal ▲ ▼.
In the write operation mode where ▼ becomes low level, the second
The output signal Q of the flip-flop circuit FF shown in the figure is at a high level (logic "1" because it holds the high level of the write enable signal ▲ ▼, whereby the gate circuit G is opened. Therefore, the operation timing signal rw ′ of the data output buffer DOB formed according to the level of the write enable signal ▲ ▼ is
Data output buffer as it is as timing signal rw
Informed to DOB. Therefore, as shown in the figure, during the high level period before the write enable signal ▲ ▼ becomes low level, the timing signal rw is formed and the data output buffer DOB is in the operating state, so that data is output from the output terminal Dout. .

Next, when the write enable signal ▲ ▼ is set to the low level, the timing signal φrw is formed instead of the timing signal rw, so that the data input buffer DIB becomes the operating state and the data supplied from the input terminal Din is It is written in the selected memory cell.

After that, while supplying the address signal and the write data,
Each time the write enable signal ▲ ▼ is set to low level, writing is sequentially performed on the selected memory cells.
At this time, the storage information of the selected memory cell is output to the output terminal at each high level of the write enable signal ▲ ▼.
It is output from Dout. In such an operation mode, since the write data is supplied to the input terminal Din one after another,
In order to avoid contention with read data from the output terminal Dout, the input terminal Din and the output terminal Dout are used in a memory system in which they are connected to external data buses provided respectively.

On the other hand, in the write operation mode in which the write enable signal ▲ ▼ is set to the low level prior to the change of the column address strobe signal ▲ ▼ to the low level as shown by the dotted line in the figure, the flip-flop circuit FF of FIG. Since the low level of the write enable signal {circle over ()} is taken in, its output signal Q is set to the low level (logic "0"). Therefore, since the gate circuit G is closed, the timing signal .phi.rw supplied to the data output buffer DOB is set to the low level irrespective of the timing signal rw 'formed according to the write enable signal {circle over ()}. This causes the data output buffer DOB
Sets its output to a high impedance state. In this state, the data input buffer DIB is set to the operating state by the timing signal φrw which is generated at each low level of the write enable signal {circle over ()}, so that continuous writing can be performed by the column static operation similar to the above. In such an operation mode, since the output of the data output buffer DOB is in a high impedance state, it is possible to configure a memory system in which the input terminal Din and the output terminal Dout are connected to a common external bus.

If it is a read operation, the data input buffer DIB
Is to put its output into a high impedance state according to the high level of the write enable signal ▲ ▼, and write data should be supplied to the external data bus to which the input terminal Din and the output terminal Dout are commonly connected. There is no.

After that, when the column address strobe signal ▲ ▼ is once brought to a high level chip non-selected state, the flip-flop circuit FF is reset.

[Effect]

(1) Two types of write operation modes can be realized by identifying the change timing of the write enable signal based on the change timing of the column address strobe signal and controlling the operation of the data output buffer. As a result, it can be used for both a memory system in which the input terminal Din and the output terminal Dout are connected to different external data buses for use and a memory system in which they are connected to a common external data bus for use. The effect is obtained.

(2) Since the application of the dynamic RAM is expanded by the above (1), it is possible to achieve the effect that the mass productivity can be improved.

(3) According to the above (1), RA in static column format
M can be used in a memory system in which its input and output terminals are connected to a common external data bus. This allows
Even in such a common external data bus type memory system, continuous writing / reading, which is a feature of the static column type RAM, can be performed, so that the effect of improving the memory function can be obtained.

(4) Since the timing relationship between the column address strobe signal and the write enable signal can be identified by using the edge trigger type flip-flop circuit, the effects of (1) to (3) above can be obtained by adding an extremely simple circuit. can get.

Hereinafter, the invention made by the present inventor has been specifically described based on examples, but it goes without saying that the present invention is not limited to the above-mentioned examples and can be variously modified without departing from the scope of the invention. Nor. For example, a column address strobe signal ▲ ▼ and a write enable signal ▲
The circuit for determining the timing of ▼ can adopt various embodiments. The name of the column address strobe signal may be any name as long as it identifies the address signal multiplexed and supplied from the substantially common external terminal.

[Field of application]

This invention is a dynamic type of static column format.
It is widely available in RAM.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a dynamic RAM according to the present invention, FIG. 2 is a logic circuit diagram showing an embodiment of a timing identification control circuit included in the timing control circuit, and FIG. FIG. 6 is a timing chart showing an example of the operation. MARY ... Memory array, MC ... Memory cell, DC ... Dummy cell, CW ... Column switch, SA ... Sense amplifier,
AR ... Active restore circuit, R, C-DCR ... Row / column decoder, R, C-ADB ... Row / column address buffer, DOB ... Data output buffer, DIB ... Data input buffer, TC ... Timing Control circuit, FF ... Flip-flop circuit, G ... Gate circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location G11C 11/34 354 A (56) References JP-A-59-75490 (JP, A) JP-A-SHO 58-73080 (JP, A) JP-A-60-246091 (JP, A)

Claims (2)

[Claims] 1. A memory array comprising a plurality of word lines, a plurality of data lines, dynamic memory cells arranged at the intersections of the word lines and the data lines arranged in a matrix, and an external terminal A data input buffer for inputting data and a data output buffer for outputting the data stored in the memory cell to the outside, and a row address in response to a change from the high level to the low level of the first external control signal. A word line corresponding to the row address signal of the memory array is fetched, and a column address signal is fetched in response to the change of the second external control signal from the high level to the low level. This is a static column type dynamic RAM that selects the data line corresponding to the signal. In the recycling, under the condition that the voltage level of the write enable signal received from the outside when the second external control signal changes to the low level is low level, the period until the second external control signal changes from the low level to the high level. Irrespective of the change in the write enable signal, the output of the data output buffer is continuously set to the high impedance state, and the write enable signal is changed from the high level to the low level a plurality of times during the continuous high impedance state. At the time of change, the column address signal is taken in according to the change in the level of the write enable signal, and data is continuously written to the memory array in accordance therewith, and the high impedance state of the output of the data output buffer is controlled. Holding circuit data to do The input is made to respond to the write enable signal, the clock terminal of the holding circuit is made to respond to the second external control signal, and the data output buffer is controlled by the output of the holding circuit. When the voltage level of the write enable signal is low level when changing to low level, the holding circuit is set to the first state, and the output of the holding circuit changes the output of the data output buffer to the high impedance. State, and when the second external control signal changes to a high level, the holding circuit is reset to a second state different from the first state, whereby the output of the holding circuit is reset. A dynamic RAM that eliminates the need to maintain a high-impedance state. 2. In one memory cycle, when the voltage level of a write enable signal received from the outside when the second external control signal changes to low level is high, the second external control signal changes from low level to low level. The data output buffer and the data input buffer are controlled during the period until it changes to the high level, and the column address is changed according to the level change of the write enable signal when the write enable signal changes from the high level to the low level a plurality of times. 2. The dynamic RAM according to claim 1, wherein the dynamic RAM according to claim 1 is adapted to take in a signal and enable continuous reading and writing of data to and from the memory array accordingly.