JPH07109707B2 - Dynamic RAM - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a dynamic RAM, for example, a technology effective for a dynamic RAM having a large storage capacity.

[Background technology]

A 1-bit memory cell in a dynamic RAM is
It is composed of an information storage capacitor Cs and an address selection MOSFET, and information of logic "1" and "0" is stored in the form of whether the capacitor Cs has a charge or not. To read information, turn on the MOSFET, connect the capacitor Cs to the common data line, and sense how the potential of the data line changes according to the amount of charge accumulated in the capacitor Cs. Done by

In the case of a highly integrated and large capacity memory array, memory cells are formed small and many memory cells are connected to a common data line. Accordingly, the ratio of the capacitor Cs to the stray capacitance Co of the common data line, that is, Cs / Co has a very small value. When developing a dynamic RAM with a storage capacity of approximately 1 Mbit, the elements that make up the memory cell are miniaturized, so the above Cs / C
The ratio of o becomes smaller and smaller, which is a bottleneck in increasing the storage capacity.

Then, as a result of studying the stray capacitance of the data line, the inventors of the present application have found that the capacitance value of the stray capacitance Co of the common data line can be reduced by circuit means.
That is, the data line is divided and a common sense amplifier is arranged at the dividing point via the transmission gate MOSFET. As a result, the data line length and the number of memory cells connected to the data line can be reduced by half, and the stray capacitance Co can be reduced by about half.

However, it became clear that the following problems occur when the data line is precharged to a power supply voltage of about 1/2 and the half precharge method that uses it as the read reference voltage is adopted. . That is, the row (X) address is fixed, one word line is selected, the column (Y) address is switched, and continuous reading / writing in the column (Y) direction is performed. In the static column mode, the data line on the non-selected word line side in the floating state holds the half precharge level during this period. In this case, there is a possibility that the precharge level in the data line on the non-selected side may change due to coupling noise or a leak current in the PN junction of the address selection MOSFET coupled to the data line. Since this half precharge level is used as the read reference voltage of the memory cell, it causes the operation margin to deteriorate due to the level fluctuation.

The dynamic RAM is described in, for example,
See Japanese Patent No. 74535. For the dynamic RAM having the static column mode function, see, for example, “Nikkei Electronics”, Nikkei McGraw-Hill Co., July 18, 1983.
Pp. 169-193.

[Object of the Invention]

An object of the present invention is to provide a dynamic RAM whose operation is stabilized.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Outline of Invention]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, a level compensation circuit is provided for each complementary data line divided around the sense amplifier, and a current for compensating the precharge level is supplied to the complementary data line in which the word line is in the non-selected state through the switch gate MOSFET. To do.

[Embodiment] FIG. 1 shows a schematic configuration diagram of a main portion of an embodiment of a memory array portion in a dynamic RAM according to the present invention.

Although not particularly limited, the unit memory array is composed of a pair of memory arrays MARY-L and MARY-R divided in the data line direction, as shown by a broken line in the figure. That is,
Each of the memory arrays MARY-L and MARY-R is divided into left and right in FIG.
SA is provided. The pair of input / output nodes of the sense amplifier SA are connected to the complementary data line D on the left side and the complementary data line on the right side via the transmission gate MOSFETs Q5, Q6 (Q7, Q8) and the transmission gate MOSFETs Q9, Q10 (Q11, Q12), respectively. (Not shown), respectively. As a result, the length of one data line and the number of coupled memory cells are halved, so that the stray capacitance Co (not shown) of the data line can be reduced.
As a result, the read signal level from the memory cell appearing on the data line can be increased.

The sense amplifier SA is composed of a CMOS latch circuit, although not particularly limited. That is, the sense amplifier SA is 2
It is configured by cross-coupling the input and output of two CMOS inverter circuits. The source of the P-channel MOSFET that constitutes the sense amplifier SA is the other sense amplifier SA.
The power supply voltage Vcc is supplied through a P-channel switch MOSFET Q15 which is shared by the sources of the similar P-channel MOSFETs. The source of the N-channel MOSFET constituting the sense amplifier SA is shared with the sources of the similar N-channel MOSFETs of the other sense amplifiers SA, and the ground potential of the circuit is supplied via the N-channel type switch MOSFET Q14. The sense amplifier SA is put into operation by being supplied with the power supply voltage Vcc and the ground potential of the circuit via the switch MOSFETs Q15 and Q14 as described above.

The 1-bit memory cell has an information storage capacitor Cs and an address selection MOSFET Qm as shown as a representative.
The information of logic "1" and "0" is stored in the form of whether the capacitor Cs has a charge or not. To read information, the MOSFET Qm is turned on to connect the capacitor Cs to the common data line D or, and how the potential of the data line D (or) changes depending on the amount of charge accumulated in the capacitor Cs. Is done by sensing. That is, when the word line of the left memory array MARY-L is selected, the left transmission gate MOSFETs Q5 to Q8 are turned on by the high level of the timing signal φL, so that the sense amplifier SA operates as the left memory array MARY. It is coupled to the -L data line and amplifies a potential change according to the amount of charge accumulated in the capacitor Cs of the selected memory cell.

In order to detect a minute signal from such a memory cell, the complementary data line D, is precharged to the power supply voltage Vcc / 2 of about 1/2. That is, between the pair of input / output nodes of the sense amplifier SA, a precharge MOSF that shorts them
ETQ16 and Q17 are provided. Further, in order to compensate for the precharge level during the chip non-selection period, the voltage of Vcc / 2 formed by the voltage dividing resistors R3 and R4 is applied to the pair of operating voltage supply lines of the sense amplifier SA via the MOSFET Q18. Supplied. When the MOSFET Q18 is turned on by the timing signal p, the operating voltage supply terminal of the sense amplifier SA is short-circuited by the short-circuit MOSFET Q13. However, when accessing the data only by changing the column address, the data lines of the non-selected memory array are kept in a floating state for a longer period than in the normal mode. Therefore, both ▲ ▼ and ▲ ▼ The level fluctuation from the Vcc / 2 precharge level during standby, which is high level, is also larger than in normal mode. Therefore, with this level compensation alone, in the first page mode and the static column mode, there occurs a problem that the waiting time for column-based access becomes long. Further, if the capacity of the circuit is increased to solve this problem, the current consumption increases. Therefore, in this embodiment, in the access of the memory cell, the data lines of the memory arrays MARY-L and MARY-R whose word lines are not selected are brought into a floating state, so that their precharge levels are coupled or The following level compensating circuit is provided in order to prevent the level from changing due to the leak current.

That is, the memory array on the left shown as a representative
The complementary data line D of MARY-L is connected via switch gate MOSFETs Q1 to Q4 controlled by the timing L '.
The divided voltage of Vcc / 2 formed by the voltage dividing resistors R1 and R2 is supplied. The memory array MARY-R on the right side is also provided with a level compensation circuit similar to the above (not shown).

An address decoder for selecting the memory cells of the memory arrays MARY-L and MARY-R, an address buffer for receiving an address signal from an external terminal and supplying an internal address signal to the address decoder, and control from an external terminal. The timing control circuit that forms various timing signals necessary for the operation of the internal circuit according to the signal is configured by a circuit similar to a known circuit. Although not particularly limited, the address signal is supplied in a time-series manner from the common external terminal in synchronization with the address strobe signals ▲ ▼ and ▲ ▼. A well-known type circuit is used for the column address buffer and the address decoder.

An example of the operation of this embodiment circuit will be described below with reference to the timing chart shown in FIG.

In the chip unselected state in which the row address strobe signal ▲ ▼ and the column address strobe signal ▲ ▼ are at the high level, the precharge signal p is set to the high level. Further, the timing signals .phi.L and .phi.R are both set to the high level, so that the sense amplifier SA is connected to the complementary data lines of the selectively divided memory arrays MARY-L and MARY-R. Q9 ~ Q1
Both 2 are turned on. When the selected memory array MARY-L or MARY-R is in the non-selected state, the operation timing signal φpa of the sense amplifier SA becomes low level,
The timing signal pa is set to high level, so switch
MOSFETs Q14 and Q15 are both turned off. This allows
The input / output node of the sense amplifier SA is set to a high impedance state. After that, the precharge MOSFETs Q16 and Q17 are turned on by the precharge signal p which is set to the high level. As a result, the high level and the low level of the complementary data line D, in the memory array on the selected side are short-circuited by the read / write operation, so that the precharge level is formed. Further, the complementary data lines of the memory array on the non-selected side remain at the precharge level.

When the chip is not selected for a relatively long time, the precharge level of the complementary data line is lowered by the leak current. To prevent this, the divided voltage of Vcc / 2 formed by the voltage dividing resistors R3 and R4 is M
It is supplied to the complementary data line D, via the operating voltage supply line (common source line) with the OSFETs Q13 and Q18 and the amplification MOSFET that constitutes the sense amplifier SA.

For example, in the read operation, the row address buffer takes in the address signal X1 supplied from the external terminal in synchronization with the falling edge of the row address strobe signal ▲ ▼ and transmits it to the address decoder. According to the address designated by the address signal X1, for example, when the memory cell of the memory array MARY-R on the right side is selected, the timing signal φL is set to the low level. As a result, the transmission gate MOSFETs Q5 to Q8 connecting the sense amplifier SA and the complementary data line of the memory array MARY-L on the left side are turned off. The timing signal φR is kept at the high level as shown by the dotted line in the figure.

The one word line W on the right side designated by the address signal X1 is set to the high level. As a result, the MO for selecting the address of one of the complementary data lines D, is selected.
The SFETQm is turned on, and the charge of the storage capacitor Cs is read to the data line. After that, the timing signal φpa is set to the high level and the timing signal pa is set to the low level, so that the power switch MOSFET Q1
Since 4 and Q15 are turned on, the sense amplifier SA amplifies the level difference between the complementary data lines on the right side.

Next, when the column address strobe signal ▲ ▼ is set to the low level, the column address buffer and the address decoder are activated, the address signal Y1 supplied from the external terminal is taken in, and one of the sense amplifiers SA is selected. Supply two amplified outputs through the input / output line (I / O), main amplifier and output buffer (not shown)
Send out as read data D1 from out. In this embodiment, since the column circuit is composed of a static type circuit, when the address signal is changed from Y2 to Y4, each of the circuits responds to this by a common input with the sense amplifier SA. Switch the connection of the output line (I / O),
The output signals D2 to D4 are transmitted one after another. With such a static column mode, for example, in a dynamic RAM having a storage capacity of about 1 Mbit, data of up to 1024 bits can be continuously read.

In such a static column mode, when the complementary data lines of the memory array MARY-L on the left side are left in a floating state for a relatively long time, the half precharge level is changed due to coupling or leakage current. I will end up. In the circuit of this embodiment, when the timing signal .phi.L is brought to the low level by the row address instruction, the timing signal L'is brought to the high level. This allows the switch gate MOSFETs Q1 to Q4
Is turned on and Vcc / formed by the voltage dividing resistors R1 and R2
Supply voltage of 2 to each data line. The similar timing signal R'in the selected memory array MARY-R is kept at the low level as shown by the dotted line and has no influence on the read operation of the memory cell.

[Effect]

(1) One of the memory arrays divided in the data direction is continuously accessed in a static column mode or a page mode, and the data line of the memory array is in a floating state for a relatively long time. Even if kept at the same level, the level compensation circuit keeps supplying the half precharge level to the complementary data line of the other non-selected side memory array, thereby keeping the half precharge level as the read reference voltage of the memory cell constant. Therefore, it is possible to obtain the effect of stabilizing the operation.

(2) Due to the above (1), even if the power supply voltage fluctuates during operation, the precharge level as the reference voltage can be obtained according to the fluctuation, so that stable operation can be performed even when the power supply voltage fluctuates. The effect that can be obtained is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention. Nor. For example, the column circuit may be a dynamic circuit. In this case, the column address strobe signal ▲
A similar continuous access (page mode) can be performed by setting ▼ to a high level and then to a low level to take in column address signals one after another. The row address signal and the column address signal may be supplied from independent external terminals. In this case, the selection / non-selection is controlled by the chip selection signal instead of the address strobe signal. Alternatively, an internal synchronous system may be adopted in which a change in the address signal is detected and a series of timing signals required for the internal circuit is formed based on the change.

[Field of application]

The present invention is widely applied to a dynamic RAM in which a unit memory array is disassembled, a common sense amplifier is selectively connected to complementary data lines of both memory arrays, and a read reference voltage of a memory cell is formed by half precharge. It is available.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing an embodiment of a memory array in a dynamic RAM according to the present invention, and FIG. 2 is a timing chart for explaining an example of its operation. MARY-L, MARY-R ... Memory array, SA ... Sense amplifier

Claims (1)

[Claims] 1. A plurality of memory cells each of which is provided at an intersection of a pair of divided complementary data lines and a word line and includes an address selecting MOSFET and an information storage capacitor, and the divided complementary data lines. Transmission gate MOSFET
A common sense amplifier coupled through the precharge circuit, a precharge circuit for precharging the complementary data line to a power supply voltage of about 1/2 via the transmission gate MOSFET, and a separate complementary data line. And a level compensation circuit for compensating the leak current through a switch gate MOSFET on the complementary data line side where the word line is not selected.