JPH07226507A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [Object] To improve a semiconductor device having a MIS structure and a method for manufacturing the same, and to improve operation speed and uniformity of characteristics. [Structure] In a semiconductor device having a MIS structure, the gate electrode 5G has a structure including an α-Ta film 5α, and the gate electrode is TiN.
A structure in which a gate insulating film is made of polycrystalline SiC and a gate electrode is made of an α-Ta film,
And a step of selectively forming only the gate electrode region of the sputtered β-Ta film as α-Ta, and patterning the α-Ta gate electrode from the Ta film using the selective etching property of α-Ta and β-Ta. A method of manufacturing the semiconductor device, including:

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a MIS type semiconductor device and its manufacturing method.

Due to the increase in the degree of integration in VLSI and the like,
The design rules of circuit patterns are becoming more and more miniaturized, and the widths of electrodes and wirings arranged inside a VLSI or the like are extremely miniaturized. In such a situation, there is a problem of delay in operation of VLSI due to increased resistance of miniaturized electrodes and wiring, and a technique for forming a fine and low-resistance gate electrode in a MIS type semiconductor element that constitutes the VLSI. Is strongly desired.

[0003]

2. Description of the Related Art Conventionally, a MOS type semiconductor device in which a gate insulating film is made of a silicon oxide (SiO ₂ ) film formed by thermal oxidation has been used in many MIS type semiconductor devices.
In order to reduce the resistance of the gate electrode of the S-type semiconductor device and prevent operation delay, a gate electrode having a polycide structure has been often used.

FIG. 5 shows an M having a conventional polycide gate.
FIG. 1 is a schematic cross-sectional view showing a main part of a typical example of an OS type semiconductor device (MOSFET), in which 51 is, for example, p type silicon (Si).
Substrate, 52 element region, 53 field oxide film, 54 gate oxide film, 55A poly-Si film, 55B tungsten silicide (WSi _x ) film, 55 tungsten polycide gate electrode, 56S n ⁺ type source region , 56D are n ⁺ type drain regions.

Then, the above MOSFET was formed by the method described below with reference to the process sectional view of FIG. See Fig. 6 (a). That is, by the usual selective oxidation (referred to as LOCOS method) means.
A field oxide film 53 that defines and separates the element region 52 is formed on the main surface of the Si substrate 51, and then a gate oxide film 54 having a thickness of, for example, about 10 nm is formed on the element region 52 by a normal thermal oxidation means.

Next, referring to FIG. 6 (b), a poly Si film 55A having a thickness of, for example, about 100 nm is formed on the above substrate by a normal vapor phase growth means.
A high concentration of, for example, an n-type impurity is introduced into 55A.

Next, referring to FIG. 6 (c), a WSi _x film 55B having a thickness of, for example, about 100 nm is formed on the poly Si film 55A by an ordinary sputtering means.
And then subjecting the WSi _x film 5 to a predetermined high temperature heat treatment.
Lower resistance of 5B.

Next, as shown in FIG. 6D, a resist pattern 61 having a pattern shape corresponding to the gate electrode is formed on the WSi _x film 55B by an ordinary lithography means.

Next, referring to FIG. 6 (e), using the resist pattern 61 as a mask, reactive ion etching (R
The WSi _x film 55B and the poly Si film 55A are collectively patterned by an IE) process to form a tungsten polycide gate electrode 55 in which the poly Si film 55A and the WSi _x film 55B are stacked.

Next, after removing the resist pattern 61, the tungsten polycide gate electrode 55 is used as a mask for the Si substrate 51.
In this method, arsenic (As) is ion-implanted at a high concentration on the surface of the element region 52 to form the n ⁺ type source region 56S and the drain region 56D.

[0011]

However, in the conventional MOSFET formed by the above method, the wiring resistivity of the gate electrode 55 of the tungsten polycide structure is 200 μm.
By having a relatively high value of about Ω · cm, when the wiring width is extremely reduced, the wiring resistance is increased due to the above-mentioned relatively high resistivity, so that a VLSI or the like configured by using the MOSFET There is a problem that the operating speed of the device decreases beyond the allowable range.

Further, in the above manufacturing method, as described with reference to FIG. 6E, when forming the polycide gate, a thick laminated film composed of the lower poly-Si film 55A and the upper-layer WSi _x film 55B. But the resist pattern with the same mask
Since the patterning is performed in line with 61, if the wiring width is extremely reduced, the pattern accuracy will be greatly affected by the side etching during the above patterning, and the operation will be affected by the fluctuations in channel length and wiring resistance. There was also the problem of speed variations.

Therefore, the present invention provides a method of forming a gate electrode having a low wiring resistivity and high pattern accuracy, and a semiconductor device having a fine and low resistance gate electrode formed by the method, and a VLSI It is intended to improve the operation speed of the above and the reliability thereof.

[0014]

According to the present invention, there is provided a MIS structure in which a gate electrode is provided on a semiconductor substrate via a gate insulating film, and the gate electrode is formed of an α-tantalum film. Or a MI in which a gate electrode is arranged on a semiconductor substrate via a gate insulating film.
The semiconductor device according to the present invention has an S structure and the gate electrode has a two-layer structure in which an α-tantalum film is laminated on a titanium nitride film, or a gate electrode is arranged on a semiconductor substrate via a gate insulating film. Has a MIS structure provided, the gate insulating film is made of a silicon carbide film, and the gate electrode is α
A step of forming a gate insulating film on a semiconductor device or a semiconductor substrate of the present invention made of a tantalum film, a step of forming a β-tantalum film on the gate insulating film,
Ions of an inactive substance are selectively implanted into a region of the tantalum film corresponding to the gate electrode to remove β-tantalum in the region from α-.
A method for manufacturing a semiconductor device according to the present invention, which includes a step of transforming into tantalum, a step of selectively removing the β-tantalum film by an entire surface etching means and forming a gate electrode of the remaining α-tantalum film, or A step of forming a gate insulating film, a step of forming a titanium nitride film on the gate insulating film, a titanium nitride film having a shape corresponding to a gate electrode on the gate insulating film by selectively etching away the titanium nitride film Forming a pattern,
A step of forming a tantalum film on the gate insulating film having the titanium nitride film pattern, in which the titanium nitride film pattern is selectively α-tantalum and the gate insulating film is β-tantalum, the tantalum is formed by a full etching means. Membrane β
Selectively removing the tantalum region and removing the titanium nitride film and α
A method of manufacturing a semiconductor device according to the present invention, which includes a step of forming a gate electrode having a tantalum film laminated thereon, or a step of growing a polycrystalline silicon carbide film to be a gate insulating film on a semiconductor substrate, A step of amorphizing the surface portion of a region of the silicon carbide film other than the portion where the gate electrode is provided by ion implantation of an inert material, β on the amorphized region on the silicon carbide film A step of forming a tantalum film which becomes α-tantalum in the gate arrangement portion which becomes tantalum and has a polycrystalline structure, a β tantalum region of the tantalum film is selectively removed by an etching means for the entire surface, and the gate made of silicon carbide This is achieved by the method for manufacturing a semiconductor device according to the present invention, which has a step of forming a gate electrode made of an α-tantalum film on an insulating film.

[0015]

In the semiconductor device according to the present invention, α-tantalum (Ta) is used for the conductive film forming the gate electrode.
α-Ta is a stable gate material having a high melting point and high chemical resistance, and at the same time, its resistivity is about 20 μΩ · cm, which is about 1/10 of that of ordinary tungsten polycide.
Therefore, by using this α-Ta for the gate electrode, the reliability of the gate can be improved and at the same time, the gate delay can be reduced to at least about 1/10 of that in the conventional case, and a high-speed MIS type semiconductor device can be formed.

A thin film of Ta is usually formed by a sputtering method in a vacuum at room temperature. A thin Ta film formed on an insulating film by this method is usually a β-Ta film having a columnar crystal structure. It is called, and has a different crystal structure from α-Ta, which has a massive crystal structure. Therefore, a large difference appears in electrical and chemical properties between α-Ta and β-Ta.

In terms of electrical properties, the resistivity of α-Ta has a low resistivity of about 20 μΩ · cm as described above, whereas the resistivity of β-Ta can only be reduced to about 200 μΩ.

In terms of chemical properties, β-Ta is easily etched by plasma etching using chlorine (Cl), whereas α-Ta is extremely inactive and very difficult to be etched. Therefore, if α-Ta can be selectively formed in the pattern region to be the gate electrode, β-Ta is selectively removed by dry etching using chlorine-based plasma to form the gate electrode made of α-Ta. It becomes possible to do.

FIG. 4 shows that for α-Ta and β-Ta,
Mixed gas of chlorine and trichloromethane (chloroform)
(Cl ₂ / CHCl ₃ ) with reactive ion etching (R
(IE) is a diagram showing the etching rate when treated, the vertical axis is the etching rate, the horizontal axis is included in the above mixed gas
The ratio of CHCl ₃ is shown.

From this figure, for example, the mixing ratio of CHCl ₃
Near 0.2, the etching rate of α-Ta is less than 100 nm / min, while the etching rate of β-Ta is 1000 nm.
It can be seen that a large etching selectivity ratio of 10 or more can be obtained at a value of / min or more.

On the other hand, a portion of the β-Ta film is selectively α-T
It was experimentally confirmed that it is possible to form a. That is, since the crystal structure of β-Ta is a metastable state, a uniform β-Ta film can be formed only by the sputtering means under special conditions. For example, the purity of the sputtering gas, the degree of vacuum in the preliminary vacuuming of the vacuum container used for sputtering film formation are good, the surface condition of the substrate on which the film is formed is appropriate, and the substrate temperature does not rise during film formation. That is, high energy is not applied after the film formation. Therefore, if these conditions are not satisfied, β-Ta cannot be obtained, and the formed Ta is transformed into α-Ta.

The conditions under which α-Ta is experimentally confirmed will be described below. (1) Although Ta formed on a cooled (avoid heat generation due to ion bombardment) mirror-like silicon (Si) wafer is β-Ta, it is sputtered with high power without cooling, and the substrate temperature is high. Is intentionally increased, α-Ta is formed. (2) Ta that is normally formed on titanium nitride (TiN) is α-
It is Ta. Also, a T film formed on a polycrystalline silicon carbide (SiC) film heteroepitaxially grown on a Si wafer.
a is α-Ta. On the other hand, Ta formed on the surface of the SiC film which has been made amorphous by subjecting the surface of the SiC film to, for example, sputter etching is β-Ta. (3) When the formed β-Ta is subjected to high-energy ion implantation, it is transformed into α-Ta.

Although the reproducibility of the film quality is often low when forming α-Ta, the film quality of α-Ta formed by the methods (1) to (3) above is stable. If the various properties of Ta confirmed by the above experiments are effectively used, β-T
α-Ta is selectively grown on a part of a, or β
It becomes possible to selectively transfer part of -Ta to α-Ta.

In the present invention, the property of Ta described above is utilized, for example, a partial region corresponding to the gate electrode on the gate oxide film is selectively α-Ta and the other region is β-T.
A Ta film made of a is formed, and then the β-T in the Ta film is utilized by utilizing the large etching selectivity of β-Ta with respect to α-Ta in the RIE process using the chlorine-based gas.
The portion a is selectively removed by etching, and the remaining α-T
The gate electrode is formed by the portion a.

As described above, according to the method of the present invention, the patterning of the gate electrode is not performed by the selective etching through the etching mask, but high etching of the α structure and the β structure of the Ta film of the gate electrode material is performed. The pattern transfer accuracy is improved and the pattern deformation due to side etching is also prevented, so that it is possible to form a fine gate electrode pattern with high accuracy.

Further, since the gate electrode is formed of α-Ta having an extremely low resistivity, the wiring resistance of the gate electrode is reduced and the MIS type semiconductor device can be speeded up.

[0027]

EXAMPLES The present invention will be described in detail below with reference to illustrated examples. 1 is a process sectional view of a first embodiment of the present invention, FIG. 2 is a process sectional view of a second embodiment of the present invention, and FIG. 3 is a process sectional view of a third embodiment of the present invention. The same object is denoted by the same reference numeral throughout the drawings.

In the first embodiment of the present invention shown in FIG. 1, α-is formed on a gate insulating film made of, for example, silicon oxide (SiO ₂ ).
This is an embodiment corresponding to claims 1 and 4 (including 7 and 8) in which a gate electrode made of Ta is provided.

Referring to FIG. 1 (a), a device region 2 is formed on a p-type Si substrate 1 according to a conventional method.
A field oxide film 3 which separates and defines the gate SiO ₂ film 4 having a thickness of about 10 nm is formed on the element region 2.

Referring to FIG. 1 (b), β-Ta is then sputtered on the above substrate.
A Ta film 5 having a thickness of about 100 nm was formed under the above conditions. The sputtering conditions are as follows.

Target High-purity Ta sputtering gas Argon (Ar) Gas pressure in film forming chamber 20 mTorr Sputtering power (DC) 1 KW Substrate temperature <70 ° C. Under the above conditions, a uniform β-Ta film 5β is formed. The temperature of the substrate 1 during the above sputtering was 70 ° C. at the maximum. Therefore, the local transition to α-Ta due to the temperature rise of the Ta film 5 does not occur, and the formed β-T
The a film 5β has a uniform crystal structure.

Next, referring to FIG. 1C, Ar ions are selectively ion-implanted into the region corresponding to the gate electrode to be formed in the β-Ta film 5β by, for example, scanning means, and this ion implantation is carried out. The β-Ta film 5β in the region was selectively transferred to the α-Ta film 5α.

It is desirable that the transition to the α-Ta film 5α is completely performed up to the bottom surface of the Ta film. In this embodiment having a film thickness of about 100 nm, Ar ion implantation is performed at an accelerating voltage of 200 KV and ion implantation. 10 or more under current of 400 μA or more
The dose was ¹⁶ ions / cm ³ . At the time of this ion implantation, the Ta film in the ion-implanted region is selectively heated to 170 ° C. or higher by the energy of the ion implantation. Therefore, β-Ta to α-T in this ion-implanted region is increased.
The transition to a is promoted by the impact energy of ions and the temperature rise.

Here, the ion implantation method may be any method as long as the above-mentioned implantation conditions are satisfied and the implantation can be performed with high pattern accuracy. As a currently used apparatus, a focused ion beam apparatus is used. , An ion projection exposure apparatus and the like. Further, ion implantation may be selectively performed on the gate electrode region by using an ordinary ion implantation apparatus using an implantation mask.

See FIG. 1 (d). Then, the above-mentioned CHCl ₃ mixture ratio of about 0.2 [Cl ₂ / CH
Cl ₃ ] RIE process using mixed gas as etching gas (α-
The Ta film 5 is entirely etched with a selective etching ratio of β-Ta to Ta of 10 or more) to selectively remove the β-Ta region (5β) by etching to remove the gate SiO ₂
A gate electrode 5G made of α-Ta (5α) is left on the film 4. The conditions in the RIE process are as follows, for example.

Etching gas Cl ₂ 160 sccm CHCl ₃ 49 sccm Etching gas pressure 200 mTorr Etching temperature 50 ° C. Etching power (RF) 0.8 W / cm ² See FIG. 1 (e) Next, using the α-Ta gate electrode 5G as a mask For example, arsenic (As) is ion-implanted into the element region 2 to form an n ⁺ type source region 6S and a drain region 6D, and a MOS type semiconductor device according to claims 1 and 4 (including 7 and 8) of the present invention is provided. Complete.

The second embodiment of the present invention shown in FIG. 2 has the two-layer structure of a gate electrode of titanium nitride (TiN) and α-Ta (including 7 and 8). It is a corresponding example.

As shown in FIG. 2 (a), as in the previous embodiment, for example, a field oxide film 3 for demarcating and separating the element region 2 is formed on the surface of the p-type Si substrate 1, and then a thickness of about 10 nm is formed on the element region 2. After forming a gate oxide film, a refractory metal Si ₃ N ₄ film that becomes a diffusion barrier by sputtering on this substrate, for example, TiN with a thickness of about 50 nm.
The film 7 is formed. The film forming conditions are as follows, for example.

Target TiN Sputtering gas Ar Gas pressure in film forming chamber 10 mTorr Sputtering power (DC) 1 KW See FIG. 2 (b) Next, the above TiN film 7 is formed by using ordinary photolithography.
A resist pattern 8 having a pattern shape corresponding to the gate electrode is formed thereon.

Next, referring to FIG. 2 (c), using the resist pattern 8 as a mask, for example, 3
The TiN film 7 is etched to the bottom by RIE treatment with nitrogen fluoride (NF ₃ ) using an etching gas, and a TiN electrode pattern 7G having a pattern shape corresponding to the gate electrode is formed on the gate SiO ₂ film 4 in the device region 2. After being formed, the resist pattern 8 is removed by a method such as O ₂ ashing.

Referring to FIG. 2 (d), the condition for forming β-Ta is satisfied on this substrate, and a thickness of 1
A Ta film of about 00 nm is formed.

The conditions for sputter film formation are, for example, as follows. Target Ta Sputtering gas Ar Gas pressure in deposition chamber 20 mTorr Sputtering power (DC) 1 KW Substrate temperature <70 ℃ Ta film 5 formed under these conditions is TiN electrode pattern 7G
The upper part is transferred to α-Ta (5α), and the upper part of the gate oxide film 4 becomes a film made of β-Ta (5β).

Referring to FIG. 2 (e), RI is used as an etching gas, which is similar to the above-mentioned embodiment, for example, [Cl ₂ / CHCl ₃ ] mixed gas having a mixing ratio of CHCl ₃ of about 0.2.
The Ta film 5 is entirely etched by E treatment (selection ratio of β-Ta to α-Ta of 10 or more), the β-Ta region (5β) is selectively removed by etching, and the TiN electrode pattern 7G is formed. A gate electrode 9 is formed by laminating α-Ta (5α). Then, after that, using the gate electrode 9 as a mask, for example, arsenic (As) is ion-implanted into the element region 2 to form an n ⁺ type source region 6S and a drain region 6D. , Including 8)
The MOS semiconductor device according to the present invention is completed.

In the third embodiment of the present invention shown in FIG. 3, SiC is used for the gate insulating film.
Is included). Refer to FIG. 3 (a) When forming the MIS type semiconductor device having the above structure,
For example, after forming a field oxide film 3 for defining and separating the element region 2 on the surface of a p-type Si substrate 1, a thickness of 10 nm is formed on this substrate under the condition that heteroepitaxial growth is performed on Si.
A SiC film 10 to be a gate insulating film was formed to some extent. The film forming conditions are as follows, for example.

Growth gas Dichlorosilane (SiH ₂ Cl ₂ ) 700 sccm Propane (C ₃ H ₈ ) 30 sccm Hydrogen (H ₂ ) 7 slm Growth gas pressure 300 mTorr Growth temperature (substrate temperature) 1000 ° C. On the exposed element region 2, a polycrystalline SiC film 10P is grown by heteroepitaxial growth,
An amorphous SiC film 10A grows on the field oxide film 3.

Next, referring to FIG. 3 (b), using the ordinary photolithography technique, the above SiC
A resist pattern 12 having a pattern shape of the gate electrode is formed on a region 11 of the film 10 where the gate electrode is to be formed, and then the resist pattern 12 is used as a mask to sputter-etch with Ar gas to form a region other than the gate electrode forming region.
The surface of the SiC film 10 is selectively and slightly etched. The etching conditions are as follows, for example.

Etching gas Ar Etching gas pressure 200 mTorr Etching power (RF) 0.8 W / cm ^{2 By} this sputter etching, polycrystal on the device region 2
The surface of the region of the SiC film 10P not masked by the resist pattern 12 is selectively made amorphous. 10AA indicates a region which is newly amorphized by the sputter etching.

Next, as shown in FIG. 3 (c), after removing the resist pattern 12 by O ₂ ashing means or the like, the above-mentioned β-Ta is formed on the SiC film 10 under the condition (see FIG. 1 (b)). Thickness by sputtering
A Ta film 5 of about 100 nm is formed. Note that here, the SiC film
The α-Ta film 5α is deposited on the gate forming region 11 which maintains the state of the polycrystalline SiC film 10P up to the surface of the region 10, and the surface 10AA in which the surface of the SiC film 10 is amorphized. A β-Ta film 5β is deposited on the region 10A grown in the amorphous state.

Next, as shown in FIG. 3 (d), the mixing ratio of, for example, CHCl ₃ similar to the above-mentioned embodiment is 0.2
Use a mixed gas of [Cl ₂ / CHCl ₃ ] as an etching gas
The Ta film 5 is entirely etched by RIE treatment (selection ratio of β-Ta to α-Ta is 10 or more), and the β-Ta region (5β) is selectively removed by etching to form a gate insulating film. A Ta gate electrode 10G composed of an α-Ta film (5α) is left on the region 10P which maintains the polycrystalline state up to the surface of the SiC film 10.

After that, the field oxide film 3 and the above α-
Gate electrode consisting of Ta film (5α)
Arsenic (As) is ion-implanted into the Si substrate 1 through the film 10 (the region having the amorphized region 10AA on the surface) to form the n ⁺ type source region 6S and the drain region 6D. The MOS type semiconductor device according to claim 3 and claim 6 (including 7 and 8) is completed.

As shown in the above first to third embodiments,
According to the present invention, it is possible to easily form a gate electrode having a low wiring resistance by using α-Ta having an extremely low resistivity, and the patterning of the gate electrode is performed by selective etching through an etching mask. In addition, since the Ta film of the gate electrode material is formed by the high etching selectivity of the α structure and the β structure, the pattern transfer accuracy is improved and the pattern deformation due to side etching is prevented, so that the gate electrode pattern is highly accurate and fine. Can be formed.

[0052]

As described above, according to the present invention, it becomes possible to form a fine gate electrode with high accuracy using α-Ta having an extremely low resistivity.

Therefore, the present invention largely contributes to the improvement of the operation speed and the uniformization of the characteristics of the VLSI or the like whose wiring width is extremely reduced due to high integration.

[Brief description of drawings]

FIG. 1 is a process sectional view of a first embodiment of the present invention.

FIG. 2 is a process sectional view of a second embodiment of the present invention.

FIG. 3 is a process sectional view of a third embodiment of the present invention.

FIG. 4 Etching rate of α-Ta and β-Ta for Cl ₂ / CHCl ₃ plasma

FIG. 5 is a schematic sectional view of a conventional MOS semiconductor device.

FIG. 6 is a sectional view of a conventional MOSFET manufacturing process.

[Explanation of symbols]

1 p-type Si substrate 2 element region 3 field oxide film 4 gate SiO ₂ film 5 Ta film 5α α-Ta film 5β β-Ta film 5G α-Ta gate electrode 6S n ⁺ type source region 6D n ⁺ type drain region

Claims (8)

[Claims] 1. A semiconductor device having a MIS structure in which a gate electrode is provided on a semiconductor substrate via a gate insulating film, and the gate electrode is formed of an α-tantalum film. 2. A MIS structure in which a gate electrode is provided on a semiconductor substrate via a gate insulating film, and the gate electrode has a two-layer structure in which an α-tantalum film is laminated on a barrier film. A semiconductor device characterized by: 3. A MIS structure in which a gate electrode is provided on a semiconductor substrate via a gate insulating film, the gate insulating film is made of a silicon carbide film, and the gate electrode is made of an α-tantalum film. A semiconductor device characterized by the above. 4. A step of forming a gate insulating film on a semiconductor substrate, a step of forming a β-tantalum film on the gate insulating film, and a selective inertness in a region of the β-tantalum film corresponding to a gate electrode. There is a step of ion-implanting a substance to transform β-tantalum in the region into α-tantalum, and a step of selectively removing the β-tantalum film by a whole surface etching means to form a gate electrode by the remaining α-tantalum film. A method of manufacturing a semiconductor device, comprising: 5. A step of forming a gate insulating film on a semiconductor substrate, a step of forming a titanium nitride film on the gate insulating film,
A step of selectively removing the titanium nitride film by etching to form a titanium nitride film pattern having a shape corresponding to a gate electrode on the gate insulating film; and the titanium nitride film having the titanium nitride film pattern on the gate insulating film. A step of forming a tantalum film in which the film pattern is selectively made to be α-tantalum and the gate insulating film is made to be β-tantalum, and the β-tantalum region of the tantalum film is selectively removed by an etching means for the entire surface to perform the nitriding. A method of manufacturing a semiconductor device, comprising a step of forming a gate electrode in which a titanium film and an α-tantalum film are laminated. 6. A step of growing a polycrystalline silicon carbide film to be a gate insulating film on a semiconductor substrate, and a portion of the silicon carbide film where a gate electrode is provided by selective ion implantation of an inert material. A step of amorphizing the surface portion of the removed region,
A step of forming a tantalum film which becomes β-tantalum on the amorphized region on the silicon carbide film and becomes α-tantalum in the gate arrangement portion having a polycrystalline structure, and the tantalum film of the entire surface is etched by an etching means. A method of manufacturing a semiconductor device, comprising the step of selectively removing a region of β tantalum and forming a gate electrode made of an α-tantalum film on the gate insulating film made of silicon carbide. 7. The method for forming the tantalum film is a sputtering method.
A method for manufacturing a semiconductor device as described above. 8. The method of manufacturing a semiconductor device according to claim 4, wherein the means for etching the entire surface of the tantalum film is a dry etching method using plasma of a gas containing chlorine.