JPH07161924A - Method of manufacturing semiconductor device and semiconductor device - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to a method for manufacturing a semiconductor device in which a plurality of semiconductor chips are stacked and arranged, and to improve the yield. [Structure] A carrier forming a carrier 3 including a chip mounting portion 10, a plurality of V-shaped grooves 9 provided in a side wall portion 5, and a flange-shaped extending portion 7 in which a plurality of electrode portions 12 are formed. Forming process and semiconductor chip on chip mounting part 10 of carrier 3
Chip mounting process for mounting 1 and wire bonding process for forming the carrier unit 13 by disposing the wire 11 between the electrode pad 2 and the electrode portion 12 formed on the semiconductor chip 1 through the V-shaped groove 9. A stacking step in which a plurality of carrier units 13 are stacked and fixed using a fixing material 22 and integrated to form a semiconductor device block 23; and a wire 11 positioned in the V-shaped groove 9 is removed to the outside by removing unnecessary portions. A semiconductor device is manufactured by an unnecessary portion removing step of exposing and forming the semiconductor device 24.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method and a semiconductor device, and more particularly to a semiconductor device manufacturing method and a semiconductor device in which a plurality of semiconductor chips are stacked.

In recent years, in order to improve the packaging density of semiconductor chips, a semiconductor device having a structure in which semiconductor chips are stacked (so-called three-dimensional semiconductor device) has been proposed. By stacking the semiconductor chips in this manner, it is possible to arrange a high-density semiconductor device in a small mounting space.

On the other hand, a semiconductor device is subjected to a reliability test such as a burn-in test before shipment. In a semiconductor device having a structure in which a plurality of semiconductor chips are laminated, it is necessary to perform a reliability test on each semiconductor chip.

Therefore, there is a demand for a method of manufacturing a semiconductor device capable of efficiently performing a reliability test on a three-dimensional semiconductor device.

[0005]

2. Description of the Related Art Conventionally, a method disclosed in US Pat. No. 5025306 or US Pat. No. 4525921 is known as a method for realizing a high density so-called three-dimensional semiconductor device by stacking a plurality of semiconductor chips. There is.

The three-dimensional semiconductor device disclosed in each of these publications is generally structured such that wiring is formed on the surface of a semiconductor chip, a plurality of wirings are laminated and then fixed by a fixing material (adhesive material or the like). It was Further, the wiring formed on the surface of the semiconductor chip is drawn out to the side portion of the semiconductor device in units of each semiconductor chip, and is connected to an external circuit or the like at this side portion position.

[0007]

Generally, a semiconductor device is
Perform reliability tests such as burn-in tests before shipment. This reliability test is carried out in the semiconductor device manufacturing process. Therefore, also in the conventional three-dimensional semiconductor device, the reliability test is performed on the completed semiconductor device by stacking and fixing a plurality of semiconductor elements.

In a normal semiconductor device in which one semiconductor chip is arranged in one package, this test method causes no particular problem, but a three-dimensional semiconductor in which a plurality of semiconductor chips are stacked to form one semiconductor device The following problems occur in the device.

That is, since the three-dimensional semiconductor device has a structure in which a plurality of semiconductor chips are stacked, the semiconductor device is considered to be defective even when only one of the plurality of semiconductor chips has an abnormality. Will be discarded. In this case, the semiconductor chips other than the semiconductor chip in which the abnormality has occurred are discarded although they are normal.

As described above, the yield of the three-dimensional semiconductor device is the product of the yields of the individual semiconductor chips. Therefore, the yield of the conventional three-dimensional semiconductor device in which the reliability test is performed after the semiconductor chips are stacked has a low yield and is normal. There is a problem that it is not possible to efficiently use various semiconductor chips.

Further, in the conventional structure in which the wiring is arranged on the upper surface of the semiconductor chip, it is difficult to position the wiring at a predetermined position with high accuracy, and a special jig or equipment is required to perform this positioning. There is a problem that manufacturing of a semiconductor device is troublesome.

The present invention has been made in view of the above points, and an object of the present invention is to provide a method of manufacturing a semiconductor device and a semiconductor device capable of improving the yield of the semiconductor device.

[0013]

[Means for Solving the Problems] The above problems can be solved by taking the following measures.

According to the first aspect of the present invention, a chip mounting portion on which a semiconductor chip is mounted, a plurality of groove portions provided on the side wall portion of the chip mounting portion, and a flange-like shape extending outward from the chip mounting portion are formed. And wire-bonding: a carrier forming step of forming a carrier having a collar-shaped portion formed with a plurality of electrode portions and a chip mounting step of mounting a semiconductor chip on the chip mounting portion of the carrier. A wire bonding step of forming a carrier unit by arranging a wire through the groove between the electrode pad formed on the semiconductor chip and the electrode portion formed on the collar-shaped portion, and the carrier unit. A plurality of carrier units are stacked, and the plurality of stacked carrier units are fixed and integrated with a fixing material to form a semiconductor device block. By removing the unnecessary portions of the carrier and the fixing material that form the semiconductor device block, the wires located at least in the groove formed in the side wall portion are exposed to the outside to form the semiconductor device. A semiconductor device is manufactured by a removing step.

The invention according to claim 2 is characterized in that after the wire bonding step is completed, a reliability test of the semiconductor chip is conducted using the electrodes.

Further, in the invention of claim 3, after the unnecessary portion removing step is finished, the exposed wire is processed so as to be slightly discharged onto the side wall portion, and the conductive paste is disposed on the slightly discharged wire. It is characterized by being used as a connection electrode portion.

Further, in the invention of claim 4, after the unnecessary portion removing step is completed, the exposed wire is provided with a solder and a material of the wire together with a metal material having good bonding property, and the solder is provided on the metal material. To form a connection electrode portion.

According to a fifth aspect of the present invention, in the wire bonding step, a wire body made of a conductive material is coated on the outside with an insulating material, and a plurality of wires are crossed with each other. It is characterized in that it can be arranged between the electrode pad and the electrode portion.

According to the invention of claim 6, in the step of removing the unnecessary portion, the carrier and the fixing material are removed so that the side surface of the semiconductor chip is exposed to the outside except the side surface facing the side wall portion. It is a thing.

Further, the invention of claim 7 is characterized in that the groove portion formed in the side wall portion is a V-shaped groove.

According to the invention of claim 8, a semiconductor chip, a bottom plate portion on which the semiconductor chip is mounted, a side wall portion standing on the bottom plate portion and facing one side surface of the semiconductor chip, and the side wall portion. A semiconductor device formed by stacking a plurality of carrier units each including a carrier having a groove portion in which a wire connected to an electrode pad formed on a semiconductor chip is interposed,
The plurality of carrier units are fixed in a stacked state by a fixing material, the side wall portion is exposed to the outside, and the end portion of the wire interposed in the groove is exposed to the outside. Semiconductor device.

Further, the invention of claim 9 is characterized in that at least the bottom surface of the carrier is made of a material having a good thermal conductivity.

[0023]

Functions Each of the above means has the following functions.

According to the first, second and eighth aspects of the invention, since the carrier unit having the individual semiconductor chips mounted thereon and having the electrode portions connected to the semiconductor chips by the wires is formed before the laminating step, the individual carrier units are formed. The reliability test can be performed for each carrier unit. Therefore, defective semiconductor chips can be removed before the stacking step, and only good semiconductor chips are stacked in the stacking step, so that the yield of manufactured semiconductor devices can be improved. .

According to the third and fourth aspects of the invention, since the connecting electrode portion is formed on the wire with the conductive paste or solder, the semiconductor device can be easily and surely mounted on the circuit board or the like.

According to the fifth aspect of the present invention, the wire is made of a conductive material and has a structure in which an insulating material is coated on the outside of the wire main body, and the plurality of wires intersect each other. Since it can be disposed between the wire and the portion, the degree of freedom in drawing the wire can be improved.

According to the sixth aspect of the invention, since the area of the side surface exposed to the outside of the semiconductor chip is increased, the heat dissipation efficiency can be improved.

Further, according to the invention of claim 7, the groove formed in the side wall portion is a V-shaped groove, so that the wire is automatically inserted by being inserted in the bottom portion (pointed portion) of the V-shaped groove. Positioning of the wire can be easily performed because the wires are positioned.

According to the invention of claim 9, at least the bottom surface of the carrier is made of a material having a good thermal conductivity, so that the heat radiation efficiency can be improved.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.

In FIG. 1, 1 is a semiconductor chip,
A plurality of electrode pads 2 are formed near the side edges of the upper surface. Further, 3 is a carrier for mounting the semiconductor chip 1.

The carrier 3 is made of hard resin, insulating metal or the like, and has a bottom plate portion 4, side wall portions 5, and the like.
6, the collar-shaped extending portions 7, 8 and the like are integrally formed. The side wall portions 5 and 6 have a structure erected on the bottom plate portion 4, and the bottom plate portion 4 and the side wall portions 5 and 6 cooperate to form the chip mounting portion 10. This chip mounting part 1
0 has a U-shape when viewed from the side.

Of the side walls 5 and 6, the chip mounting portion 10
Electrode pad 2 formed on semiconductor chip 1 mounted on
A plurality of V-shaped grooves 9 are formed in the side wall portion 5 on the side close to the. The number of the V-shaped grooves 9 is equal to or larger than the number of the electrode pads 2. Further, the V-shaped groove 9 is formed at a fixed position of the wire 11 described later with high precision.

The brim-shaped extending portions 7 and 8 are formed to extend outward from the side wall portions 5 and 6 so as to be substantially flush with the bottom plate portion 4. The collar-shaped extending portion 7 is formed to extend outward from the side wall portion 5 in which the V-shaped groove 9 is formed, and the extension length thereof is set longer than that of the other collar-shaped extending portion 8. ing. Further, an electrode portion 12 in which a conductive metal is arranged in a strip shape is formed on the upper portion of the brim-shaped extending portion 8, and the formation position and the number thereof are configured to correspond to the V-shaped groove 9. .
Further, the collar-shaped extending portions 7 and 8 are provided with positioning holes 7a and 8 at two corner positions diagonally opposed to each other when the carrier 3 is seen in a plan view.
a is provided.

To manufacture a semiconductor device, first, the semiconductor chip 1 is mounted on the chip mounting portion 10 formed on the carrier 3. An adhesive (not shown) having non-conductivity and heat dissipation is applied to the chip mounting portion 10 in advance, and the semiconductor chip 1 is fixed to the chip mounting portion 10 of the carrier 3 by this adhesive. FIG. 2 shows a state in which the semiconductor chip 1 is fixed to the carrier 3.

As described above, the semiconductor chip 1 is the carrier 3
Then, wire bonding is performed between the electrode pad 2 formed on the semiconductor chip 1 and the electrode portion 12 formed on the flange-shaped extension portion 7, and the wire 11 is attached.
Is provided. FIG. 3 shows the carrier 3 in which the semiconductor chip 1 is mounted and the wires 11 are arranged between the electrode pads 2 and the electrode portions 12. The wire 11 is a gold wire and can be arranged (wired) by using a wire bonding device used in a normal semiconductor device manufacturing process.

When the wire 11 is arranged by using the wire bonding apparatus, the electrode pad 2,
Since the V-shaped groove 9 and the electrode portion 12 are formed corresponding to each other, the arranged wire 11 is interposed in the V-shaped groove 9. Further, in the wire bonding by the wire bonding apparatus, since a certain amount of tension is applied to the wire 11, the wire 11 is positioned at the bottom (pointed portion) of the V-shaped groove 9 when it is interposed. Become.

Further, since the V-shaped groove 9 is formed at the wire fixing position with high precision as described above, by performing the wire bonding process as described above,
The wire 11 is automatically positioned at a predetermined fixed position.
Therefore, the positioning of the wire 11 can be performed extremely easily and reliably. The semiconductor chip 1 and the carrier 3 joined by the wire 11 as described above will be collectively referred to as a carrier unit 13 hereinafter.

In FIG. 4A, not the gold wire 11 but the covered wire 14 in which the gold wire 15 shown in FIG. 4B is covered with the insulating material 16 such as resin is used as the wire to be wire-bonded. The carrier unit 13 is shown.
As described above, by adopting the covered wire 14, it becomes possible to cross the covered wires 14 with each other when the covered wires 14 are routed as shown in FIG. 4A, and the coated wires 14 can be freely routed. Therefore, the wiring design can be facilitated.
In FIG. 4, the structure other than the covered wire 14 is the same as that of the carrier unit 13 shown in FIG.

Here, the carrier unit 13 formed as described above will be considered.

Carrier unit 1 formed as described above
3 is in a state before being stacked, and each carrier unit 13 has one semiconductor chip 1 mounted thereon. Moreover, the electrode pad 2 formed on the semiconductor chip 1 is connected to the electrode portion 12 by the wire 11. Therefore, for each carrier unit 13,
In other words, the burn-in test (reliability test) can be performed on each semiconductor chip 1.

Therefore, in the method of the present invention, the burn-in test is performed at the stage when the carrier unit 13 is manufactured as shown in FIG. In the figure, 17
Is a probe needle for performing a burn-in test. Since the carrier unit 13 has the strip-shaped electrode portion 12 connected to the semiconductor chip 1 formed on the long extended collar-shaped extension portion 7, the probe needle 17 is contacted and connected to the electrode portion 12. The burn-in test can be carried out by.

As a result, the reliability test of the semiconductor chip 1 can be performed before the carrier unit 13 is stacked, and the defective semiconductor chip 1 can be removed before the carrier unit 13 is stacked. Therefore, in the manufacturing process of the semiconductor device after the stacking process performed after manufacturing the carrier unit 13, only the good semiconductor chip 1 is used, and the yield of the manufactured semiconductor device can be improved. it can. Further, it is possible to prevent the three-dimensional semiconductor device in which defective semiconductor chips and non-defective semiconductor chips are mixed, which has been conventionally performed, from being discarded, and it is possible to efficiently use non-defective semiconductor chips.

As a result of the reliability test shown in FIG. 5, the carrier unit 13 having the semiconductor chip 1 determined to be a non-defective product is subsequently subjected to the stacking process. In this embodiment, a method of manufacturing a semiconductor device having a structure in which two carrier units 13 are laminated will be described as an example.

To stack the carrier units 13, a positioning jig 18 as shown in FIG. 6 is used. The positioning jig 18 has a structure in which positioning shafts 20 and 21 are erected on a base 19. As described above, the collar-shaped extending portions 7 and 8 are provided with positioning holes 7 at two corner positions diagonally opposed to each other when the carrier 3 (carrier unit 13) is viewed in plan.
Although a and 8a are bored, the positioning shafts 20 and 21 are provided corresponding to the positioning holes 7a and 8a.

Therefore, by mounting the two carrier units 13 to be stacked on the positioning jig 18 so that the positioning holes 7a and 8a are inserted into the positioning shafts 20 and 21, respectively, the two carrier units 13 are mutually attached. Can be positioned. Since this positioning work can be performed by simply mounting the two carrier units 13 on the positioning jig 18, it can be performed extremely easily.

Two carrier units 1 as described above
When the positioning of 3 is performed, temporary fixing is performed between the two carrier units 13. FIG. 7 shows a state in which temporary fixing is performed between the two carrier units 13. In this state, since each semiconductor chip 1 is still exposed, each semiconductor chip 1 is sealed by using the fixing material 22 (shown by satin in FIG. 8) and the two carrier units 13 are fixed, Semiconductor device block 23 shown in FIG.
To form. At this time, it is conceivable to use resin or glass as the fixing material 22.

When the two carrier units 13 are fixed in a stacked state by the fixing material 22 to form the semiconductor device block 23, the carrier 3 and unnecessary portions of the fixing material 22 are subsequently removed. Specifically, the position shown by the arrow AA in FIG. 8 and the position shown by the arrow BB are removed.
Here, the position shown by the arrow AA in FIG. 8 is the position of the outer side surface of the side wall portion 5. Further, the position shown by the arrow BB in FIG. 8 is the position of the side surface facing the side wall portion 6 among the four outer peripheral side surfaces of the semiconductor chip 1. Further, as a method of removing the unnecessary portion, for example, a polishing method can be considered.

FIG. 9 shows a three-dimensional semiconductor device 24 formed by removing unnecessary portions. As shown in the figure, since the semiconductor device block 23 is removed to the position of the outer side surface of the side wall portion 5, the outer side surface of the side wall portion 5 is exposed to the outside. Further, since the wire 11 is interposed in the V-shaped groove 9 formed in the side wall portion 5 as described above, the end portion 11a of the wire 11 is also exposed to the outside. Therefore, the end 11a of the wire 11 can be used for electrical connection with the semiconductor chip 1.

Further, since the V-shaped groove 9 is formed at a wire fixing position with high accuracy, the wire 11 interposed at the lower end (pointed portion) of the V-shaped groove 9 is also fixed to a predetermined position. It is in the state of being positioned with high accuracy. Therefore, the position of the end 11a of each wire 11 in the semiconductor device 24 is also positioned at a predetermined position with high accuracy, and the mountability with the circuit board at the time of mounting to be described later can be improved.

Further, in the above-mentioned unnecessary portion removing step, the semiconductor device block 23 is removed to the positions of the side surfaces facing the inner side wall portions 6 of the four outer peripheral side surfaces of the semiconductor chip 1, so that the side wall portions of the semiconductor chip 1 are removed. The three side surfaces except the side surface facing 5 are exposed to the outside. Therefore, the heat dissipation characteristics of the semiconductor chip 1 can be improved, and the reliable operation of the semiconductor chip 1 can be ensured.

As another structure for improving the heat dissipation characteristic, it is conceivable to form the carrier 3 with a metal having a good heat dissipation property (high heat conductivity). At this time, when a conductive metal is used as the material of the carrier 3, the electrode portion 1
When forming 2, the insulating film (resin film or the like) may be formed on the flange-shaped extending portion 7 and the electrode portion 12 may be formed on the insulating film.

The semiconductor device 24 manufactured as described above is
The side portions 24a have a structure in which the end portions 11a of the plurality of wires 11 are viewed in a state of being flush with the side portions 24a.
In this structure, the end portion 11a of the wire 11 is connected to the side surface portion 24a.
Since it does not protrude from the circuit board, a connection structure such as a bump must be provided on the circuit board side, and the mountability at the time of mounting on the circuit board or the like deteriorates. Therefore, it is conceivable to form a connection electrode on the end portion 11a of the wire 11 viewed through the side surface portion 24a. Hereinafter, a method of forming the connection electrode on the end portion 11a of the wire 11 will be described.

10 and 11 show connection electrodes 25 and 26.
As an example, a silver (Ag) paste is used. In the method of forming the connection electrode 25 shown in FIG. 10, first, the end portion 11 a of the wire 11 of the semiconductor device 24 is viewed through the side surface portion 24.
The wire 11 is slightly projected by thinly etching a. The amount of protrusion at this time is, eg, about 30 μm. Then, as shown in FIG. 10 (A), Ag paste 2
The protruded wire 11 is immersed in a bath 28 containing 7 (shown in satin). Thus, as shown in FIG. 10B, the connection electrode 25 made of the Ag paste 27 can be formed on the semiconductor device 24.

Further, in the method of forming the connection electrode 26 shown in FIG. 11, the side surface portion 24a where the end portion 11a of the wire 11 of the semiconductor device 24 is viewed is thinly etched similarly to the method described with reference to FIG. By doing so, the wire 11 is slightly projected. Then, the Ag paste supply device 29
The Ag paste is discharged onto each wire 11 by using the nozzle 30 connected to the connection electrode 26 to form the connection electrode 26.

On the other hand, FIG. 12 shows a method of forming the connection electrode 30 by solder dipping. When this solder dip is used, the wire 11 is attached to the side surface 24
The etching for projecting from a is not performed, but the solder dip is directly formed on the upper portion of the wire end portion 11a as viewed. However, when gold (Au) is used as the wire 11, the solder is not well compatible with gold as is well known. Therefore, in order to form the connection electrode 30 by solder dip, first, the first connection layer 31 of titanium (Ti) or chromium (Cr) is formed on the end 11a of the wire 11, and copper (Cu) or the like is formed on the first connection layer 31. Second connection layer 32 is formed, and a third connection layer 33 of nickel (Ni) or the like is further formed on the second connection layer 32.
Then, the solder bumps 34 (shown in satin) are formed on the upper part of the first to third connection layers 31 to 33. The connection electrode 30 formed in this manner can also improve the mountability of the semiconductor device 24 on the circuit board.

FIG. 13 shows a state in which the semiconductor device 24 having the connection electrodes (the example in which the connection electrodes 25 are formed) is formed on the circuit board 35 as described above. Connection pads 36 are formed on the circuit board 35 so as to correspond to the connection electrodes 25 formed on the semiconductor device 24.

FIG. 14 is an enlarged view showing the vicinity of the arrangement position of the semiconductor device 24 (shown by a chain line in the figure) on the circuit board 35. As shown in the figure, the connection pad 36 is connected to a wiring 37 obtained by firing a conductive paste.
Here, in each semiconductor chip 1 (two in the case of this embodiment), the ground connection electrode 25a and the power supply connection electrode 2 are provided.
5b can be commonly used.

Therefore, in the circuit board 35, the connection pads 36a and 36b connected to the ground connection electrodes 25a and the power supply connection electrodes 25b are connected to the common wirings 37a and 37, respectively.
The connection is made by b. With this configuration, the connection pads 36a and 36b are individually connected to the wirings 37a,
The number of wirings on the circuit board 35 can be reduced as compared with the configuration in which 37b is pulled out, the degree of freedom in designing the wirings 37, 37a, 37b can be improved, and the circuit board 35 can be effectively used.

[0060]

As described above, according to the present invention, the following effects can be realized.

According to the first, second and eighth aspects of the present invention, the reliability test can be carried out in units of individual carrier units, and therefore defective semiconductor chips can be removed before the stacking step. Since only non-defective semiconductor chips are stacked in the stacking process, the yield of manufactured semiconductor devices can be improved.

According to the third and fourth aspects of the present invention, since the connecting electrode portion is formed on the wire with the conductive paste or solder, the semiconductor device can be easily and surely mounted on the circuit board or the like.

According to the fifth aspect of the invention, the wire is made of a conductive material and has a structure in which an insulating material is coated on the outside of the wire main body. Since it can be disposed between the wire and the portion, the degree of freedom in drawing the wire can be improved.

According to the sixth aspect of the invention, since the area of the side surface exposed to the outside of the semiconductor chip is increased, the heat dissipation efficiency can be improved.

According to the invention of claim 7, the positioning accuracy of the wire can be improved and the mountability can be improved.

Further, according to the invention of claim 9, the heat radiation efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a process of mounting a semiconductor chip on a carrier in one embodiment of the method of the present invention.

FIG. 2 is a diagram for explaining a process of mounting a semiconductor chip on a carrier in one embodiment of the method of the present invention.

FIG. 3 is a diagram for explaining a wire bonding process in one embodiment of the method of the present invention.

FIG. 4 is a diagram for explaining a method of performing wire bonding with a wire in which a gold wire is covered with an insulating material.

FIG. 5 is a diagram for explaining a step of performing a reliability test in one example of the method of the present invention.

FIG. 6 is a diagram for explaining a method of positioning a carrier unit to be stacked in one embodiment of the method of the present invention.

FIG. 7 is a diagram for explaining a method for positioning carrier units to be stacked in one embodiment of the method of the present invention.

FIG. 8 is a diagram for explaining a step of forming a semiconductor block in one embodiment of the method of the present invention.

FIG. 9 is a diagram showing a semiconductor device manufactured by an embodiment of the method of the present invention.

FIG. 10 is a diagram illustrating a method of forming a connection electrode in a semiconductor device manufactured by an embodiment of the method of the present invention.

FIG. 11 is a diagram illustrating a method of forming a connection electrode in a semiconductor device manufactured by an embodiment of the method of the present invention.

FIG. 12 is a diagram illustrating a method of forming a connection electrode in a semiconductor device manufactured by an embodiment of the method of the present invention.

FIG. 13 is a diagram showing a state in which a semiconductor device manufactured by an embodiment of the method of the present invention is mounted on a circuit board.

FIG. 14 is a diagram showing a circuit board having a structure in which connection pads connected to a ground connection electrode and a power supply connection electrode are connected by a common wiring.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Electrode pad 3 Carrier 4 Bottom plate part 5,6 Side wall part 7,8 Collar-shaped extension part 7a, 8a Positioning hole 9 V-shaped groove 10 Chip mounting part 11 Wire 11a End part 12 Electrode part 13 Carrier unit 14 Coating Wire 15 Gold wire 16 Insulating material 17 Probe needle 18 Positioning jig 22 Fixing material 23 Semiconductor device block 24 Semiconductor device 25, 26, 30 Connection electrode 25a Ground connection electrode 25b Power supply connection electrode 27 Ag paste 29 Ag paste supply device 34 Solder bump 35 Circuit board 36, 36a, 36b Connection pad 37, 37a, 37b Wiring

Claims (9)

[Claims] 1. A chip mounting part (10) on which a semiconductor chip (1) is mounted, a plurality of groove parts (9) provided in a side wall part (5) of the chip mounting part (10), and the chip mounting part. (10) A carrier forming step of forming a carrier (3) including a collar-shaped portion (7) formed by extending a collar-shaped portion outwardly of the collar and having a plurality of electrode portions (12) formed thereon, A chip mounting step of mounting the semiconductor chip (1) on the chip mounting portion (10) of the carrier (3) and an electrode pad (2) formed on the semiconductor chip (1) by performing wire bonding. A wire bonding step of forming a carrier unit (13) by disposing a wire (11) between the electrode portion (12) formed on the collar-shaped portion (7) and the groove portion (9). , Stacking a plurality of carrier units (13) A plurality of carrier units (13) that are stacked and stacked.
Of the carrier (3) and the fixing material (22) forming the semiconductor device block (23), and a step of stacking the semiconductor device block (23) by fixing and integrating the same with a fixing material (22). By removing the unnecessary portion, at least the wire (11) located in the groove (9) formed in the side wall (5) is exposed to the outside,
And a step of removing an unnecessary portion for forming a semiconductor device (24). 2. After the wire bonding step is completed,
The method of manufacturing a semiconductor device according to claim 1, wherein a reliability test of the semiconductor chip (1) is performed using the electrode (12). 3. After completion of the unnecessary portion removing step, the exposed wire (11) is processed so as to be discharged slightly to the side wall portion (5), and the wire (1) discharged slightly.
1) The conductive paste (27) is arranged on the connection electrode part (2)
5. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein 4. After completion of the unnecessary portion removing step, a metal material (31 to 33) having good bondability is disposed on the exposed wire (11) together with solder and the material of the wire (11). 3. The method of manufacturing a semiconductor device according to claim 1, wherein solder is formed on the metal material (31 to 33) to form a connection electrode portion (30). 5. A wire body (1) made of a conductive material as the wire (14) in the wire bonding step.
5) a structure in which an insulating material (16) is coated on the outside, and the plurality of wires (14) are arranged between the electrode pad (2) and the electrode part (12) in a state where they cross each other. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is configured to be installed. 6. The carrier (3) and the fixing material (22) are exposed so that the side surface of the semiconductor chip (1) is exposed to the outside except the side surface facing the side wall portion (5) in the unnecessary portion removing step. 6. The method for manufacturing a semiconductor device according to claim 1, wherein the method is removed. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the groove portion formed in the side wall portion is a V-shaped groove (9). 8. A semiconductor chip (1), a bottom plate portion (4) on which the semiconductor chip (1) is mounted, and one side surface of the semiconductor chip (1) provided upright on the bottom plate portion (4). A groove part (6) in which a side wall (5) facing each other and a wire (11) formed on the side wall (5) and connected to an electrode pad (2) formed on the semiconductor chip (1) are interposed. A semiconductor device in which a plurality of carrier units (13) each composed of a carrier (3) provided with 9) are laminated, and the plurality of carrier units (13) are laminated by a fixing material (22). The side wall (5) is configured to be exposed to the outside, and the end (11a) of the wire (11) interposed in the groove (9) is exposed to the outside. A semiconductor device characterized by the following. 9. The semiconductor device according to claim 8, wherein at least the bottom surface of the carrier (3) is made of a material having good thermal conductivity.