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JP2003007899A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

Info

Publication number
JP2003007899A
JP2003007899A JP2001195087A JP2001195087A JP2003007899A JP 2003007899 A JP2003007899 A JP 2003007899A JP 2001195087 A JP2001195087 A JP 2001195087A JP 2001195087 A JP2001195087 A JP 2001195087A JP 2003007899 A JP2003007899 A JP 2003007899A
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit chip
electrodes
wiring board
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001195087A
Other languages
Japanese (ja)
Inventor
Hiroyuki Fukazawa
博之 深澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP2001195087A priority Critical patent/JP2003007899A/en
Publication of JP2003007899A publication Critical patent/JP2003007899A/en
Pending legal-status Critical Current

Links

Classifications

    • H10W72/884
    • H10W90/734
    • H10W90/754

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】 【課題】 集積回路チップの平面的寸法よりも僅かに大
きいだけの、そしてピッチの広い外部接続電極を裏面に
備えた半導体装置及びその製造方法を得ること。 【解決手段】 本発明の半導体装置50は、集積回路チ
ップSのバンプ(電極)1に対応して複数の内部電極3
21が内方に、それら内部電極321に接続された外部
電極322が外方に形成されている複数の配線32が形
成されており、内部電極321と外部電極322とを除
く部分が絶縁保護膜34で覆われたフレキシブル配線基
板30とからなり、集積回路チップSのバンプ1が内部
電極321にそれぞれ直接接続され、集積回路チップS
の側面及び裏面がフレキシブル配線基板30で覆われ
て、外部電極322が前記集積回路チップの裏面側に比
較的広いピッチで外部接続電極として形成されている。
An object of the present invention is to provide a semiconductor device having an external connection electrode on the back surface which is slightly larger than a planar dimension of an integrated circuit chip and has a wide pitch, and a method of manufacturing the same. SOLUTION: A semiconductor device 50 of the present invention has a plurality of internal electrodes 3 corresponding to bumps (electrodes) 1 of an integrated circuit chip S.
A plurality of wirings 32 are formed on the inner side and external electrodes 322 connected to the internal electrodes 321 are formed on the outer side, and a portion excluding the internal electrodes 321 and the external electrodes 322 is an insulating protective film. 34, the bumps 1 of the integrated circuit chip S are directly connected to the internal electrodes 321, respectively.
Are covered with a flexible wiring board 30, and external electrodes 322 are formed as external connection electrodes at a relatively wide pitch on the back side of the integrated circuit chip.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は集積回路チップの裏
面で接続可能な、特に複数個の集積回路チップを上下に
積み重ねた積層半導体装置を得る場合に好適な裏面に外
部接続電極を備えた配線接続構造の半導体装置及びその
製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring which can be connected on the back surface of an integrated circuit chip, and which is particularly suitable for obtaining a laminated semiconductor device in which a plurality of integrated circuit chips are stacked one above the other and having an external connection electrode on the back surface. The present invention relates to a semiconductor device having a connection structure and a manufacturing method thereof.

【0002】[0002]

【従来の技術】先ず、図7乃至図9を参照しながら、従
来技術の半導体装置を説明する。
2. Description of the Related Art First, a conventional semiconductor device will be described with reference to FIGS.

【0003】図7は従来技術の裏面に外部接続電極が形
成されている半導体装置を示す半断面図、図Yは裏面に
外部接続電極が形成されている他の半導体装置を示す半
断面図、そして図9は図Yに示した半導体装置を複数個
積み重ねた積層半導体装置の断面図である。
FIG. 7 is a half sectional view showing a semiconductor device having an external connection electrode formed on the back surface of the prior art, and FIG. Y is a half sectional view showing another semiconductor device having an external connection electrode formed on the back surface. 9 is a sectional view of a stacked semiconductor device in which a plurality of semiconductor devices shown in FIG. Y are stacked.

【0004】従来、集積回路チップと配線基板とを集積
回路チップの裏面側で電気的に接続する半導体装置の構
造としては、米国特許第5,216,278号や、AS
IC& EDAP ページ9〜15、March,19
93に開示されているMotorola社の“OMPA
C”など、図7に半分断面で示したような半導体装置6
00がある。この半導体装置600は、集積回路チップ
Sがプリント配線基板610の表面に接着剤などを用い
て搭載されている。プリント配線基板610の表面には
複数の上部ランド611が、裏面には外部接続電極61
2が、そしてヴァイアホール613が形成されていて、
集積回路チップSは、その複数の電極上に形成されてい
る半田、金などのバンプ1がそれらに対応する上部ラン
ド611に金などの金属ワイヤ614を用いて電気的に
接続されている。そして、この集積回路チップSと金属
ワイヤ114を保護するために上面部にエポキシ樹脂な
どの封止材615で封止した構造のものである。なお、
プリント配線基板610の裏面の外部電極612は、周
辺配列或いは格子配列状に設けられている。
Conventionally, as a structure of a semiconductor device for electrically connecting an integrated circuit chip and a wiring substrate on the back side of the integrated circuit chip, US Pat. No. 5,216,278 and AS
IC & EDAP pages 9-15, March, 19
93 disclosed by Motorola "OMPA"
A semiconductor device 6 such as C ″ shown in a half cross section in FIG.
There is 00. In this semiconductor device 600, an integrated circuit chip S is mounted on the surface of a printed wiring board 610 using an adhesive or the like. A plurality of upper lands 611 are provided on the front surface of the printed wiring board 610, and external connection electrodes 61 are provided on the back surface.
2 and then via hole 613 is formed,
In the integrated circuit chip S, the bumps 1 such as solder and gold formed on the plurality of electrodes are electrically connected to the corresponding upper lands 611 using metal wires 614 such as gold. Then, in order to protect the integrated circuit chip S and the metal wire 114, the upper surface is sealed with a sealing material 615 such as epoxy resin. In addition,
The external electrodes 612 on the back surface of the printed wiring board 610 are provided in a peripheral arrangement or a lattice arrangement.

【0005】しかしながら、この半導体装置600の構
造であると、金属ワイヤ614で接続するために必要な
集積回路チップSとこの半導体装置600の端面との間
隔は、最低でも0.5mm程度必要となる。従って、半
導体装置600の平面的寸法が、集積回路チップSの平
面的寸法よりも1mm以上大きくなってしまうといった
課題があった。
However, in the structure of the semiconductor device 600, the distance between the integrated circuit chip S required for connection with the metal wire 614 and the end face of the semiconductor device 600 is required to be at least about 0.5 mm. . Therefore, there is a problem that the planar size of the semiconductor device 600 becomes larger than the planar size of the integrated circuit chip S by 1 mm or more.

【0006】この課題を解決するために、本発明者が発
明し、本出願人が出願したNo.01002717 &
No.01002718(出願番号を調べて記入す
る)に開示した半導体装置700がある。この先願の半
導体装置700は、図Yに示したように、集積回路チッ
プSの裏面に予め電気的絶縁層2を形成しておき、この
集積回路チップSの側面に、複数本の細い導電線731
を樹脂732で固めた厚さの薄いコの字型の導通部品7
30をはめ込み、その側面に密着させて集積回路チップ
Sの複数のバンプ1にそれぞれ対応する導電線731の
上部先端233を接続し、それらの上部からキヤピラリ
ー(不図示)と呼ばれる細い棒で、超音波振動および熱
を加えて圧着、接続し、導電線731の下部先端734
を集積回路チップSの裏面に配設した構造のものであ
る。
In order to solve this problem, the No. No. filed by the present inventor and filed by the present applicant was applied. 01002717 &
No. There is a semiconductor device 700 disclosed in 01002718 (look up and fill in application number). In the semiconductor device 700 of this prior application, as shown in FIG. Y, an electrical insulating layer 2 is formed in advance on the back surface of the integrated circuit chip S, and a plurality of thin conductive wires are formed on the side surface of the integrated circuit chip S. 731
Thin conductive U-shaped conductive component 7 made by hardening resin with resin 732.
30 is fitted, and the upper ends 233 of the conductive wires 731 respectively corresponding to the plurality of bumps 1 of the integrated circuit chip S are connected to the side surfaces of the integrated circuit chips S, and from the upper part thereof, a thin rod called a capillary (not shown) The lower end 734 of the conductive wire 731 is connected by crimping and connecting by applying sonic vibration and heat.
Is disposed on the back surface of the integrated circuit chip S.

【0007】このように半導体装置700は、コの字型
の導通部品730を集積回路チップSの外周面に沿って
装着できるので、半導体装置700そのものをコンパク
トに仕上げることができる。
As described above, in the semiconductor device 700, since the U-shaped conductive component 730 can be mounted along the outer peripheral surface of the integrated circuit chip S, the semiconductor device 700 itself can be made compact.

【0008】そして、この半導体装置700は単体で電
子機器に組み込まれるプリント配線基板に実装して用い
ることもでき、また、図9に示したように、最下層の半
導体装置700Aの導電線231の上部先端733に、
その半導体装置700Aの上方に積層した半導体装置7
00Bの導電線731の下部先端734を直接接続し、
以下、同様に積層した半導体装置700を、このように
電気的接続を行うことにより複数個の半導体装置700
を多段に積層でき、積層部品として用いることができ
る。
The semiconductor device 700 can also be used alone by mounting it on a printed wiring board incorporated in an electronic device. Further, as shown in FIG. 9, the conductive wire 231 of the lowermost semiconductor device 700A can be used. At the top tip 733,
A semiconductor device 7 stacked above the semiconductor device 700A
Directly connect the lower tip 734 of the conductive wire 731 of 00B,
Hereinafter, the semiconductor devices 700 stacked in the same manner are electrically connected in this manner to form a plurality of semiconductor devices 700.
Can be laminated in multiple stages and can be used as a laminated component.

【0009】[0009]

【発明が解決しようとする課題】しかし、前記のような
構造の半導体装置700であると、図7に示した半導体
装置600の構造上の課題であった集積回路チップSと
その半導体装置600の端面との間隔は、0.05mm
程度にまで短縮することができるが、導通部品730の
製法上、半導体装置700の外部接続電極となる導電線
731の下部先端734が集積回路チップSの周辺配列
のみとなってしまい、外部接続電極のピッチを広く設計
できる格子配列の外部接続電極を有する半導体装置が実
現できないという課題が残った。
However, in the semiconductor device 700 having the above-described structure, the integrated circuit chip S and the semiconductor device 600 which are the structural problems of the semiconductor device 600 shown in FIG. The distance from the end face is 0.05 mm
Although it can be shortened to some extent, the lower tip 734 of the conductive wire 731, which becomes the external connection electrode of the semiconductor device 700, is only the peripheral arrangement of the integrated circuit chip S due to the manufacturing method of the conductive component 730, and the external connection electrode The problem remains that a semiconductor device having a grid array of external connection electrodes that can be designed with a wider pitch cannot be realized.

【0010】従って、本発明は、前記のような課題を解
決しようとするものであって、集積回路チップの側面及
び裏面の絶縁封止材による封止を必要とせず、しかも集
積回路チップの平面的寸法よりも僅かに大きいだけの、
そしてピッチの広い外部接続電極を裏面に備えた半導体
装置及びその製造方法を得ることを目的とするものであ
る。
Therefore, the present invention is intended to solve the above-mentioned problems, and does not require the side and back surfaces of the integrated circuit chip to be sealed with an insulating sealing material, and moreover, the flat surface of the integrated circuit chip. Slightly larger than the target size,
It is another object of the present invention to obtain a semiconductor device having external connection electrodes with a wide pitch on its back surface and a method for manufacturing the same.

【0011】[0011]

【課題を解決するための手段】それ故、本発明の半導体
装置は、複数の電極が形成されている集積回路チップ
と、その集積回路チップを搭載するフレキシブル配線基
板とからなり、前記集積回路チップの側面及び裏面を前
記フレキシブル配線基板で覆い、前記裏面側に外部接続
電極を具備せしめて構成されている。
Therefore, a semiconductor device according to the present invention comprises an integrated circuit chip having a plurality of electrodes formed thereon and a flexible wiring board on which the integrated circuit chip is mounted. The side surface and the back surface are covered with the flexible wiring board, and external connection electrodes are provided on the back surface side.

【0012】更に、具体的構造としては、本発明の半導
体装置は、複数の電極が形成されている集積回路チップ
と、フレキシブル絶縁板の中央部に形成された開口部に
突き出して前記フレキシブル絶縁板に形成されている複
数の電気的導通部が形成され、それら電気的導通部の突
き出し部を内部電極とし、それら複数の内部電極とは反
対側の電気的導通部を外部電極とし、前記複数の内部電
極と前記複数の外部電極との中間部の電気的導通部が絶
縁保護膜で被覆されて形成されているフレキシブル配線
基板とからなり、前記集積回路チップの前記複数の電極
と前記フレキシブル配線基板の前記複数の内方電極とが
それぞれ電気的に接続されて、前記絶縁保護膜で被覆さ
れている電気的導通部が前記集積回路チップの側面を覆
い、そして前記複数の外部電極が前記集積回路チップの
裏面に外部接続電極として形成されている。
Further, as a specific structure, the semiconductor device of the present invention has an integrated circuit chip on which a plurality of electrodes are formed, and the flexible insulating plate protruding from an opening formed in a central portion of the flexible insulating plate. A plurality of electrically conducting portions are formed, the protruding portions of the electrically conducting portions are internal electrodes, the electrically conducting portions on the opposite side of the plurality of internal electrodes are external electrodes, and A flexible wiring board formed by covering an electrically conductive portion in an intermediate portion between the internal electrode and the plurality of external electrodes with an insulating protective film, and the flexible wiring board and the plurality of electrodes of the integrated circuit chip. Of the plurality of inner electrodes are electrically connected to each other, the electrically conductive portion covered with the insulating protective film covers the side surface of the integrated circuit chip, and The external electrodes are formed as external connection electrodes on the back surface of the integrated circuit chip.

【0013】また、本発明の半導体装置の製造方法は、
フレキシブル絶縁板の中央部に形成された開口部に突き
出して前記絶縁板に形成されている複数の電気的導通部
を内部電極とし、それら複数の内部電極より外方の電気
的導通部を外部電極とし、前記複数の内部電極と前記複
数の外部電極とを接続する電気的導通部を絶縁膜で被覆
されて形成されているフレキシブル配線基板に、表面に
複数の電極が形成されている集積回路チップを搭載して
前記集積回路チップの裏面に外部接続電極を形成する半
導体装置の製造方法において、前記集積回路チップの表
面を前記フレキシブル配線基板の前記内部電極側に向け
て前記開口部に臨ませて位置決めする位置決め工程と、
その位置決めされた前記集積回路チップの前記複数の電
極を前記フレキシブル配線基板の前記内部電極にそれぞ
れ直接接続する電極接続工程と、前記複数の外部電極が
形成されている前記フレキシブル配線基板の外方部を前
記集積回路チップの裏面側に折り返して固定する折返し
工程とを備えていることを特徴とする。前記のフレキシ
ブル配線基板としては、前記内部電極及び前記外部電極
が形成されている面とは反対の面に接着層が形成されて
いることが望ましい。
A method of manufacturing a semiconductor device according to the present invention is
The plurality of electrically conducting portions formed in the insulating plate and protruding from the opening formed in the central portion of the flexible insulating plate are used as internal electrodes, and the electrically conducting portions outside the plurality of internal electrodes are external electrodes. An integrated circuit chip in which a plurality of electrodes are formed on the surface of a flexible wiring substrate formed by covering an electrically conductive portion connecting the plurality of internal electrodes and the plurality of external electrodes with an insulating film. In the method of manufacturing a semiconductor device, in which an external connection electrode is formed on the back surface of the integrated circuit chip by mounting the integrated circuit chip, the surface of the integrated circuit chip is faced to the internal electrode side of the flexible wiring board and is exposed to the opening. A positioning step for positioning,
An electrode connecting step of directly connecting the positioned plurality of electrodes of the integrated circuit chip to the inner electrodes of the flexible wiring board, and an outer portion of the flexible wiring board on which the plurality of outer electrodes are formed. And a folding-back step of folding and fixing the same on the back surface side of the integrated circuit chip. In the flexible wiring board, it is desirable that an adhesive layer is formed on the surface opposite to the surface on which the internal electrodes and the external electrodes are formed.

【0014】従って、本発明の半導体装置では、集積回
路チップの平面的寸法よりも僅かに大きい面積で形成で
き、そして集積回路チップの側面及び裏面は絶縁保護膜
及びフレキシブル絶縁板で覆われて保護されているた
め、集積回路チップの表面のみを封止材で封止するだけ
でよい。また、複数の外部接続電極を広いピッチで形成
することができる。
Therefore, in the semiconductor device of the present invention, it can be formed in an area slightly larger than the planar size of the integrated circuit chip, and the side surface and the back surface of the integrated circuit chip are covered with the insulating protective film and the flexible insulating plate to protect them. Therefore, only the surface of the integrated circuit chip needs to be sealed with the sealing material. Moreover, a plurality of external connection electrodes can be formed at a wide pitch.

【0015】そして、本発明の半導体装置の製造方法で
は、集積回路チップのフレキシブル配線基板における位
置決めがし易く、また、フレキシブル配線基板の内部電
極に集積回路チップの電極を直接接続することから半導
体装置全体の厚みを薄くでき、更に、半導体装置の平面
的寸法を集積回路チップの平面的寸法より、それ程広く
ない面積の構造で形成でき、更にまた、外部電極をフレ
キシブル配線基板の外方に格子配列などの任意の配列で
形成しておくことにより、それら外部電極を集積回路チ
ップの裏面に折り返すだけで外部接続電極として形成で
き、そしてそれら外部接続電極のピッチを広く設計でき
る任意の配列で形成でき、しかもフレキシブル配線基板
の外方部を集積回路チップの裏面に折り返すことによ
り、その側面及び裏面をフレキシブル配線基板の絶縁材
で覆う構造の半導体装置を形成することができる。ま
た、フレキシブル配線基板の裏面に設けた接着層の存在
により、集積回路チップの裏面に折り曲げたフレキシブ
ル配線基板の外方部を、その側面及び裏面に接着、固定
することができる。
In the method of manufacturing a semiconductor device according to the present invention, the integrated circuit chip is easily positioned on the flexible wiring board, and the electrodes of the integrated circuit chip are directly connected to the internal electrodes of the flexible wiring board. The overall thickness can be reduced, and the planar dimensions of the semiconductor device can be formed in a structure that is not so large as the planar dimensions of the integrated circuit chip. Furthermore, the external electrodes can be arranged in a grid outside the flexible wiring board. The external electrodes can be formed as an external connection electrode simply by folding them back on the back surface of the integrated circuit chip by forming them in an arbitrary array such as, and can be formed in an arbitrary array in which the pitch of the external connection electrodes can be widely designed. In addition, by folding the outer part of the flexible wiring board to the back surface of the integrated circuit chip, It is possible to form a semiconductor device having a structure covered with the insulating material of the flexible wiring board. Further, the presence of the adhesive layer provided on the back surface of the flexible wiring board enables the outer portion of the flexible wiring board bent to the back surface of the integrated circuit chip to be bonded and fixed to the side surface and the back surface thereof.

【0016】[0016]

【発明の実施の形態】以下、図1乃至図5を用いて、本
発明の一実施形態の半導体装置及びその製造方法を説明
する。
DETAILED DESCRIPTION OF THE INVENTION A semiconductor device and a method of manufacturing the same according to an embodiment of the present invention will be described below with reference to FIGS.

【0017】図1は本発明の実施形態の半導体装置を示
していて、同図Aはその断面図、同図Bは同図Aの半導
体装置の裏面図、図2は本発明の半導体装置に用いて好
適な一実施形態の1単位のフレキシブル配線基板を示し
ていて、同図Aはその表面側から見た平面図、同図Bは
同図AのB−B線上における断面図、図3は図1に示し
た本発明の半導体装置を製造するための第1の製造方法
を示す工程図、図4は図1に示した本発明の半導体装置
を製造するための第2の製造方法を示す工程図、図5は
絶縁封止材で集積回路チップの表面を封止するために用
いられる封止装置の断面図、そして図6は他の2種類の
実施形態のフレキシブル配線基板を用いて集積回路チッ
プを本発明の封止方法で封止した場合の2種類の半導体
装置の裏面図である。
FIG. 1 shows a semiconductor device according to an embodiment of the present invention. FIG. 1A is a sectional view thereof, FIG. 1B is a rear view of the semiconductor device of FIG. 1A, and FIG. 2 shows a semiconductor device of the present invention. 1 shows a flexible wiring board of one unit suitable for use in the present invention, FIG. A is a plan view seen from the front side, FIG. B is a sectional view taken along line BB in FIG. FIG. 4 is a process chart showing a first manufacturing method for manufacturing the semiconductor device of the present invention shown in FIG. 1, and FIG. 4 shows a second manufacturing method for manufacturing the semiconductor device of the present invention shown in FIG. 5 is a sectional view of a sealing device used to seal the surface of the integrated circuit chip with an insulating sealing material, and FIG. 6 shows the flexible wiring board according to the other two embodiments. FIG. 6 is a back view of two types of semiconductor devices when an integrated circuit chip is sealed by the sealing method of the present invention. .

【0018】図1において、符号50Aは本発明の一実
施形態の半導体装置を指す。この半導体装置50は、集
積回路チップSとフレキシブル配線基板30Aとから構
成されている。
In FIG. 1, reference numeral 50A indicates a semiconductor device according to an embodiment of the present invention. The semiconductor device 50 includes an integrated circuit chip S and a flexible wiring board 30A.

【0019】集積回路チップSは表面に複数の電極上に
金、半田などのバンプ1が形成されており、それらのバ
ンプ(電極)1がその表面の4辺に沿って四辺形状に配
列されている構造(クワッドインライン配列)のもので
あってもよく、相対向する2辺に沿って所定の間隔で一
直線状に配列されている構造(デュアルインライン配
列)のもの、その表面の4辺に沿って四辺形状に配列さ
れている構造(クワッドランギュラ配列)のものでも、
集積回路チップSの表面全面に格子状に配列されてい
る、所謂、エリアアレイ配列の構造のものであってもよ
い。図示の集積回路チップSは複数の電極(バンプ)1
がクワッドインライン配列で形成されているものとす
る。
On the surface of the integrated circuit chip S, bumps 1 such as gold and solder are formed on a plurality of electrodes, and the bumps (electrodes) 1 are arranged in a quadrilateral shape along the four sides of the surface. Structure (quad in-line arrangement), which is arranged in a straight line at a predetermined interval along two opposite sides (dual in-line arrangement), along the four sides of the surface Even if it has a quadrangular structure (quadrangular arrangement),
The integrated circuit chip S may have a so-called area array arrangement structure, which is arranged in a grid pattern on the entire surface. The illustrated integrated circuit chip S has a plurality of electrodes (bumps) 1
Are formed in a quad in-line arrangement.

【0020】フレキシブル配線基板30Aは、図2に示
したように、例えば、ポリイミドなどの絶縁材で形成さ
れたフレキシブル絶縁板31(図2B)の表面に、内部
電極321と外部電極322とを繋ぐ複数の配線32が
形成されており、中央部に開口部33が形成されてい
る。複数の配線32の内部電極321は開口部33の中
央の方に突き出して形成されており、外部電極322は
フレキシブル絶縁板31の外方部311、312、31
3、314に隣接する外部電極322のピッチを広げて
配設されている。これらピッチの寸法は外方部311、
312、313、314の面積、形状に応じて広げるこ
とができる。内部電極321と外部電極322とを除く
配線32部分などは絶縁保護膜34で被覆されている
(図2B)。開口部33の各コーナには一辺の長さがL
cの正方形の小孔35が形成されている。この小孔35
の代わりに開口部33に一辺に沿う切り込み線であって
もよい。そして一辺の長さLcは集積回路チップSの厚
みに相当する寸法とする。
As shown in FIG. 2, the flexible wiring board 30A connects an internal electrode 321 and an external electrode 322 to the surface of a flexible insulating plate 31 (FIG. 2B) formed of an insulating material such as polyimide. A plurality of wirings 32 are formed, and an opening 33 is formed at the center. The inner electrodes 321 of the plurality of wirings 32 are formed so as to project toward the center of the opening 33, and the outer electrodes 322 are formed on the outer portions 311, 312, 31 of the flexible insulating plate 31.
The external electrodes 322 adjacent to the electrodes 3 and 314 are arranged with a wider pitch. The dimensions of these pitches are the outer portion 311,
It can be expanded according to the area and shape of 312, 313, and 314. The wiring 32 and the like except the internal electrode 321 and the external electrode 322 are covered with an insulating protective film 34 (FIG. 2B). The length of one side is L at each corner of the opening 33.
A square small hole 35 of c is formed. This small hole 35
Alternatively, a cut line may be formed along the side of the opening 33. The length Lc of one side has a dimension corresponding to the thickness of the integrated circuit chip S.

【0021】なお、フレキシブル配線基板30Aは図を
簡略化して描いた。そのため、複数の内部電極321と
外部電極322も、代表的なもののみを示し、他のもの
は省略されている。
The flexible wiring board 30A is drawn by simplifying the drawing. Therefore, the plurality of internal electrodes 321 and the external electrodes 322 are also representative ones, and the other ones are omitted.

【0022】半導体装置50は、このような構造のフレ
キシブル配線基板30Aに集積回路チップSが搭載され
て構成されたものであって、集積回路チップSの各電極
(バンプ)1は各内部電極321に直接接続されてお
り、集積回路チップSの側面及び裏面がフレキシブル配
線基板30A、即ち、フレキシブル絶縁板31と絶縁保
護膜34で覆われ、そして、図1Bに示したように、集
積回路チップSの裏面に複数の外部電極322が外部接
続電極として形成され、そしてその表面のみが封止樹脂
Inで封止された構造のものである。
The semiconductor device 50 is constructed by mounting the integrated circuit chip S on the flexible wiring substrate 30A having such a structure, and each electrode (bump) 1 of the integrated circuit chip S has each internal electrode 321. 1C, the side surface and the back surface of the integrated circuit chip S are covered with the flexible wiring board 30A, that is, the flexible insulating plate 31 and the insulating protective film 34, and as shown in FIG. A plurality of external electrodes 322 are formed as external connection electrodes on the back surface of, and only the front surface is sealed with the sealing resin In.

【0023】このような構造を採ることによって、半導
体装置50の側面は、電気的導体である配線32が露出
せず、それらの側面を格別の絶縁保護材で保護する必要
が無くなる。従って、集積回路チップSの表面のみを絶
縁封止材で保護するだけでよい。
By adopting such a structure, the wiring 32, which is an electric conductor, is not exposed on the side surface of the semiconductor device 50, and it becomes unnecessary to protect those side surfaces with a special insulating protective material. Therefore, only the surface of the integrated circuit chip S need be protected by the insulating sealing material.

【0024】次に、図3を用いて、半導体装置50の第
1の製造方法を説明する。
Next, a first method of manufacturing the semiconductor device 50 will be described with reference to FIG.

【0025】先ず、図2に示したフレキシブル配線基板
30Aを載置台(不図示)に水平に載置し、その下方向
から集積回路チップSをフレキシブル配線基板30Aの
開口部33に挿入し、同図Bに示したように、集積回路
チップSの電極(バンプ)1と内部電極321とを接触
状態にする。そしてツールと呼ばれる細い棒(不図示)
を使用し、加熱しながら超音波で、直接、集積回路チッ
プSの電極1と内部電極321とを接続する。この場
合、少なくとも内部電極321に、予め、Au、Niな
どのメッキを施しておけば、集積回路チップSの電極1
との間に金属合金が形成され、容易に接続することがで
きる。そして、図示したように、フレキシブル配線基板
30Aの外周部を、図2Aに示した一点鎖線Laに沿っ
て所定の寸法、形状に切断する。
First, the flexible wiring board 30A shown in FIG. 2 is horizontally mounted on a mounting table (not shown), and the integrated circuit chip S is inserted into the opening 33 of the flexible wiring board 30A from the lower side thereof. As shown in FIG. B, the electrodes (bumps) 1 of the integrated circuit chip S and the internal electrodes 321 are brought into contact with each other. And a thin rod called a tool (not shown)
The electrode 1 of the integrated circuit chip S and the internal electrode 321 are directly connected to each other by ultrasonic waves while heating. In this case, if at least the internal electrode 321 is plated with Au, Ni or the like in advance, the electrode 1 of the integrated circuit chip S
A metal alloy is formed between them and they can be easily connected. Then, as illustrated, the outer peripheral portion of the flexible wiring board 30A is cut into a predetermined size and shape along the alternate long and short dash line La shown in FIG. 2A.

【0026】次に、図3Cに示したように、フレキシブ
ル配線基板30Aの外方部311、312、313、3
14を集積回路チップSの側面に沿うように下方に折り
曲げ、続いて点線Lbで集積回路チップSの裏面にも折
り曲げて、その裏面部分に接着剤などで固着する。この
ようにして半製品の半導体装置50が得られる。この半
製品の半導体装置50表面を、図5に示したように、別
の封止工程に投入し、エポキシ樹脂などの絶縁樹脂の封
止材Inで被覆し、加熱硬化させて封止すると、図1に
示した本発明の半導体装置50が得られる。
Next, as shown in FIG. 3C, the outer portions 311, 312, 313, 3 of the flexible wiring board 30A.
14 is bent downward along the side surface of the integrated circuit chip S, then also bent to the back surface of the integrated circuit chip S along the dotted line Lb, and fixed to the back surface portion with an adhesive or the like. In this way, the semi-finished semiconductor device 50 is obtained. As shown in FIG. 5, the surface of the semiconductor device 50 of this semi-finished product is put into another encapsulation step, covered with an encapsulant In of an insulating resin such as an epoxy resin, and heat-cured for encapsulation. The semiconductor device 50 of the present invention shown in FIG. 1 is obtained.

【0027】次に、本発明の半導体装置50を製造する
第2の製造方法を図4を用いて説明する。
Next, a second manufacturing method for manufacturing the semiconductor device 50 of the present invention will be described with reference to FIG.

【0028】この製造に用いるフレキシブル配線基板3
0Bの構造は、図4Aに示したように、実質的にフレキ
シブル配線基板30Aの構造と同一であって、その表面
には前記のように配線32が形成されているので、それ
らの説明は省略するが、異なる点は、そのフレキシブル
絶縁板31の裏面部分で、この裏面には接着剤層36と
その表面に剥離フィルム37とがラミネートされた構造
の基板である。この接着剤層Laは中央部の開口部33
を除くフレキシブル絶縁板31の裏面全面に、剥離フィ
ルム37は集積回路チップSの大きさより大きい開口部
を除く全面にラミネートされたものである。なお、フレ
キシブル絶縁板31も、例えば、ポリイミド樹脂製など
の絶縁材を用いて形成することができる。
Flexible wiring board 3 used in this manufacturing
The structure of 0B is substantially the same as the structure of the flexible wiring board 30A as shown in FIG. 4A, and the wiring 32 is formed on the surface thereof as described above, and therefore the description thereof is omitted. However, the different point is the back surface portion of the flexible insulating plate 31, which is a substrate having a structure in which an adhesive layer 36 is laminated on the back surface and a release film 37 is laminated on the surface thereof. The adhesive layer La has a central opening 33.
The peeling film 37 is laminated on the entire back surface of the flexible insulating plate 31 except for the area other than the opening larger than the size of the integrated circuit chip S. The flexible insulating plate 31 can also be formed by using an insulating material such as a polyimide resin.

【0029】本発明の第2の製造方法においては、この
ような構造のフレキシブル配線基板30Bを用いる。先
ず、図4Aに示したように、そのフレキシブル配線基板
30Bを載置台(不図示)に水平に載置し、その下方向
から集積回路チップSをフレキシブル配線基板30の開
口部33に挿入すると、同図Bに示した状態になる。そ
して、第1の製造方法の場合と同様に、ツールと呼ばれ
る細い棒(不図示)を使用し、加熱しながら超音波で、
直接、集積回路チップSの電極(バンプ)1と配線32
の内部電極321とを接続する。
In the second manufacturing method of the present invention, the flexible wiring board 30B having such a structure is used. First, as shown in FIG. 4A, when the flexible wiring board 30B is horizontally mounted on a mounting table (not shown) and the integrated circuit chip S is inserted into the opening 33 of the flexible wiring board 30 from below, The state shown in FIG. Then, as in the case of the first manufacturing method, a thin rod (not shown) called a tool is used, and ultrasonic waves are applied while heating.
The electrodes (bumps) 1 and the wiring 32 of the integrated circuit chip S are directly connected.
To the internal electrode 321 of.

【0030】次に、図3Bの工程でフレキシブル配線基
板30Aを切断した場合の要領で、図2Aに示した一点
鎖線Laに沿ってフレキシブル配線基板30Bの外周部
の切断を行う。そうすると、図4Bに示したような形状
の集積回路チップSが搭載されたフレキシブル配線基板
になる。
Next, as in the case of cutting the flexible wiring board 30A in the step of FIG. 3B, the outer peripheral portion of the flexible wiring board 30B is cut along the alternate long and short dash line La shown in FIG. 2A. Then, the flexible wiring board on which the integrated circuit chip S having the shape shown in FIG. 4B is mounted is obtained.

【0031】そして、フレキシブル配線基板30Bの裏
面の剥離フィルム37を剥がし、集積回路チップSの外
側に存在するフレキシブル配線基板30の外方部31
1、312を集積回路チップSの各側面から裏面側に折
り返す。そうすると、接着剤層36でフレキシブル絶縁
板31が集積回路チップSの側面及び裏面に自動的に接
着され、それら外方部311、312を集積回路チップ
Sの裏面に容易に固着させることができ、同図Cに示し
たように、外部電極322を外部接続電極として形成さ
れた構造の半製品の半導体装置が得られる。この半製品
の半導体装置の外形は図3Cに示したものと同一であ
る。
Then, the release film 37 on the back surface of the flexible wiring board 30B is peeled off, and the outer portion 31 of the flexible wiring board 30 existing outside the integrated circuit chip S is removed.
1 and 312 are folded back from each side surface of the integrated circuit chip S to the back surface side. Then, the flexible insulating plate 31 is automatically adhered to the side surface and the back surface of the integrated circuit chip S by the adhesive layer 36, and the outer portions 311 and 312 can be easily fixed to the back surface of the integrated circuit chip S, As shown in FIG. 6C, a semi-finished semiconductor device having a structure in which the external electrode 322 is formed as an external connection electrode is obtained. The outer shape of this semi-finished semiconductor device is the same as that shown in FIG. 3C.

【0032】次に、このようにして得られた半導体装置
を、図5に示した封止装置を備えた封止工程に移し、こ
の封止装置を用いて集積回路チップSの表面のみをエポ
キシ樹脂などの封止材Inで覆い、加熱硬化させること
で、図1に示したような半導体装置50が得られる。
Next, the semiconductor device thus obtained is transferred to a sealing step equipped with the sealing device shown in FIG. 5, and only the surface of the integrated circuit chip S is epoxy-treated by using this sealing device. The semiconductor device 50 as shown in FIG. 1 is obtained by covering with a sealing material In such as resin and heating and curing.

【0033】このような第2の製造方法を採ることによ
って、前記のように集積回路チップSの側面及び裏面を
フレキシブル配線基板30Bで被覆することができ、そ
の時接着剤層36の存在によって、そのフレキシブル絶
縁板31を集積回路チップSの側面及び裏面に自動的に
接着、固定することができる。半導体装置50の側面
は、電気的導体である配線32が露出しておらず、それ
らの側面を別工程の絶縁保護材で保護する必要がなく、
集積回路チップSの表面のみを封止材で封止するだけで
よい。
By adopting the second manufacturing method as described above, the side surface and the back surface of the integrated circuit chip S can be covered with the flexible wiring board 30B as described above. The flexible insulating plate 31 can be automatically adhered and fixed to the side surface and the back surface of the integrated circuit chip S. The wiring 32, which is an electric conductor, is not exposed on the side surface of the semiconductor device 50, and there is no need to protect those side surfaces with an insulating protective material in a separate process.
Only the surface of the integrated circuit chip S needs to be sealed with the sealing material.

【0034】前記の実施形態では、集積回路チップSの
複数の電極がクワッドランギュラ配列で形成されている
ものを採り上げて説明し、その集積回路チップSの裏面
に折り返すフレキシブル配線基板30A、30Bの外方
部311、312、313、314を同一形状の三角形
としたが、本発明はこれらの構造、形状に限定されるも
のではなく、集積回路チップSの裏面に折り曲げた外方
部311、312、313、314の外部接続電極部分
の形状を、図6Aに示したように、相対向する2辺が台
形と扁平三角形の切片でそれぞれ構成されるようなフレ
キシブル配線基板を用いてもよく、また、集積回路チッ
プSの複数の電極がデュアルインライン配列の場合に
は、集積回路チップSの裏面に折り曲げる外方部図を、
6Bに示したように、2枚の長方形の切片で構成できる
ような形状のフレキシブル配線基板を用いてもよいこと
を付言しておく。
In the above-described embodiment, the case where the plurality of electrodes of the integrated circuit chip S are formed in the quadrangular arrangement will be described, and the flexible wiring boards 30A and 30B that are folded back to the back surface of the integrated circuit chip S will be described. Although the outer portions 311, 312, 313, 314 have the same triangular shape, the present invention is not limited to these structures and shapes, and the outer portions 311 and 312 bent to the back surface of the integrated circuit chip S are not limited thereto. As for the shape of the external connection electrode portions of 313, 314, as shown in FIG. 6A, a flexible wiring board may be used in which two opposing sides are respectively trapezoidal and flat triangular sections. When the plurality of electrodes of the integrated circuit chip S are in a dual in-line arrangement, an outer view of bending the back surface of the integrated circuit chip S to
Note that a flexible wiring board having a shape that can be configured by two rectangular pieces as shown in FIG. 6B may be used.

【0035】[0035]

【発明の効果】以上説明したように、本発明の半導体装
置によれば、集積回路チップの平面的寸法よりも僅かに
大きいだけの、そしてピッチの広い外部接続電極を裏面
に備えた半導体装置を得ることができ、また、集積回路
チップの側面及び裏面は絶縁保護膜及びフレキシブル絶
縁板で覆われて保護されているため、改めて集積回路チ
ップの側面及び裏面を絶縁、保護する必要がない。
As described above, according to the semiconductor device of the present invention, there is provided a semiconductor device having external connection electrodes on the back surface which are slightly larger than the planar size of the integrated circuit chip and have a wide pitch. Further, since the side surface and the back surface of the integrated circuit chip are covered and protected by the insulating protective film and the flexible insulating plate, it is not necessary to insulate and protect the side surface and the back surface of the integrated circuit chip again.

【0036】また、裏面に予め接着剤層が形成されてい
るフレキシブル配線基板を用いることにより集積回路チ
ップの側面及び裏面にフレキシブル絶縁板を自動的に固
着でき、作業効率が向上する。
Further, by using the flexible wiring board having the adhesive layer formed on the back surface in advance, the flexible insulating plate can be automatically fixed to the side surface and the back surface of the integrated circuit chip, and the working efficiency is improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の一実施形態の半導体装置の断面図で
ある。
FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

【図2】 本発明の半導体装置に用いて好適な一実施形
態のフレキシブル配線基板であって、同図Aはその1単
位の平面図、同図Bは同図AのB−B線上における断面
図、同図Cは本フレキシブル絶縁板を集積回路チップの
裏面に折り曲げた状態の裏面平面図である。
FIG. 2 is a flexible wiring board according to an embodiment suitable for use in the semiconductor device of the present invention, in which FIG. 2A is a plan view of one unit thereof, and FIG. 2B is a cross section taken along line BB of FIG. FIGS. 11C and 11C are plan views of the back surface of the flexible insulating plate when it is bent on the back surface of the integrated circuit chip.

【図3】 図1に示した本発明の半導体装置を製造する
ための第1の製造方法を示す工程図である。
FIG. 3 is a process drawing showing a first manufacturing method for manufacturing the semiconductor device of the present invention shown in FIG.

【図4】 図1に示した本発明の半導体装置を製造する
ための第2の製造方法を示す工程図である。
FIG. 4 is a process drawing showing a second manufacturing method for manufacturing the semiconductor device of the present invention shown in FIG.

【図5】 他の2種類の実施形態のフレキシブル配線基
板を用いて集積回路チップを本発明の封止方法で封止し
た場合の2種類の半導体装置の裏面図である。
FIG. 5 is a back view of two types of semiconductor devices when an integrated circuit chip is sealed by the sealing method of the present invention using the flexible wiring boards of the other two types of embodiments.

【図6】 他の2種類の実施形態のフレキシブル配線基
板を用いて集積回路チップを本発明の封止方法で封止し
た場合の2種類の半導体装置の裏面図である。
FIG. 6 is a back view of two types of semiconductor devices when an integrated circuit chip is sealed by the sealing method of the present invention using the flexible wiring boards of the other two types of embodiments.

【図7】 従来技術の裏面に外部接続電極が形成されて
いる半導体装置を示す半断面図である。
FIG. 7 is a half sectional view showing a semiconductor device in which an external connection electrode is formed on the back surface of a conventional technique.

【図8】 裏面に外部接続電極が形成されている他の半
導体装置を示す半断面図である。
FIG. 8 is a half cross-sectional view showing another semiconductor device having an external connection electrode formed on the back surface.

【図9】 図8に示した半導体装置を複数個積み重ねた
積層半導体装置の断面図である。
9 is a cross-sectional view of a stacked semiconductor device in which a plurality of semiconductor devices shown in FIG. 8 are stacked.

【符号の説明】[Explanation of symbols]

1…集積回路チップSのバンプ(電極)、30C,30
D…フレキシブル配線基板、31…フレキシブル絶縁
板、311,312…フレキシブル絶縁板31の外方
部、32…配線、321…内部電極、322…外部電極
(外部接続電極)、33…開口部、34…絶縁保護膜、
35…切り込み、36…接着剤層、37…剥離フィル
ム、50A…本発明の一実施形態の半導体装置、S…集
積回路チップ、In…絶縁材、W…金属ワイヤ、Lb…
折線
1 ... Bump (electrode) of integrated circuit chip S, 30C, 30
D ... Flexible wiring board, 31 ... Flexible insulating plate, 311, 312 ... Outer portion of flexible insulating plate 31, 32 ... Wiring, 321 ... Internal electrode, 322 ... External electrode (external connection electrode), 33 ... Opening portion, 34 … Insulating film,
35 ... Notch, 36 ... Adhesive layer, 37 ... Release film, 50A ... Semiconductor device of one embodiment of the present invention, S ... Integrated circuit chip, In ... Insulating material, W ... Metal wire, Lb ...
Broken line

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 複数の電極が形成されている集積回路チ
ップと、該集積回路チップを搭載するフレキシブル配線
基板とからなり、前記集積回路チップの側面及び裏面を
前記フレキシブル配線基板で覆い、前記裏面側に外部接
続電極を備えていることをことを特徴とする半導体装
置。
1. An integrated circuit chip having a plurality of electrodes formed thereon, and a flexible wiring board on which the integrated circuit chip is mounted, wherein a side surface and a back surface of the integrated circuit chip are covered with the flexible wiring board, and the back surface is formed. A semiconductor device having an external connection electrode on its side.
【請求項2】 複数の電極が形成されている集積回路チ
ップと、フレキシブル絶縁板の中央部に形成された開口
部に突き出して前記フレキシブル絶縁板に形成されてい
る複数の電気的導通部が形成され、該電気的導通部の突
き出し部を内部電極とし、該複数の内部電極とは反対側
の電気的導通部を外部電極とし、前記複数の内部電極と
前記複数の外部電極との中間部の電気的導通部が絶縁保
護膜で被覆されて形成されているフレキシブル配線基板
とからなり、前記集積回路チップの前記複数の電極と前
記フレキシブル配線基板の前記複数の内方電極とがそれ
ぞれ電気的に接続されて、前記絶縁保護膜で被覆されて
いる電気的導通部が前記集積回路チップの側面を覆い、
そして前記複数の外部電極が前記集積回路チップの裏面
に外部接続電極として形成されていることを特徴とする
半導体装置。
2. An integrated circuit chip having a plurality of electrodes formed therein, and a plurality of electrically conducting portions formed in the flexible insulating plate protruding into an opening formed in a central portion of the flexible insulating plate. The protruding portion of the electrically conducting portion is an internal electrode, the electrically conducting portion on the opposite side of the plurality of inner electrodes is an outer electrode, and the intermediate portion between the plurality of inner electrodes and the plurality of outer electrodes is A flexible wiring board in which an electrically conductive portion is covered with an insulating protective film, and the plurality of electrodes of the integrated circuit chip and the plurality of inner electrodes of the flexible wiring board are electrically connected to each other. An electrically conductive portion that is connected and is covered with the insulating protective film covers a side surface of the integrated circuit chip,
The semiconductor device is characterized in that the plurality of external electrodes are formed as external connection electrodes on the back surface of the integrated circuit chip.
【請求項3】 フレキシブル絶縁板の中央部に形成され
た開口部に突き出して前記絶縁板に形成されている複数
の電気的導通部を内部電極とし、該複数の内部電極より
外方の電気的導通部を外部電極とし、前記複数の内部電
極と前記複数の外部電極とを接続する電気的導通部を絶
縁膜で被覆されて形成されているフレキシブル配線基板
に、表面に複数の電極が形成されている集積回路チップ
を搭載して前記集積回路チップの裏面に外部接続電極を
形成する半導体装置の製造方法において、 前記集積回路チップの表面を前記フレキシブル配線基板
の前記内部電極側に向けて前記開口部に臨ませて位置決
めする位置決め工程と、 該位置決めされた前記集積回路チップの前記複数の電極
を前記フレキシブル配線基板の前記内部電極にそれぞれ
直接接続する電極接続工程と、 前記複数の外部電極が形成されている前記フレキシブル
配線基板の外方部を前記集積回路チップの裏面側に折り
返して固定する折返し工程とを備えていることを特徴と
する半導体装置の製造方法。
3. A plurality of electrically conductive portions formed in the insulating plate and projecting into an opening formed in a central portion of the flexible insulating plate are used as internal electrodes, and electrical parts outside the plurality of internal electrodes are electrically connected. A plurality of electrodes are formed on the surface of a flexible wiring board which is formed by covering the electrically conductive portion connecting the plurality of internal electrodes and the plurality of external electrodes with an insulating film, and the conductive portion as an external electrode. A method of manufacturing a semiconductor device, comprising: mounting an integrated circuit chip, wherein an external connection electrode is formed on a back surface of the integrated circuit chip, wherein the front surface of the integrated circuit chip faces the internal electrode side of the flexible wiring board and the opening is formed. A positioning step of positioning the integrated circuit chip so as to face it, and the plurality of electrodes of the positioned integrated circuit chip are directly contacted with the internal electrodes of the flexible wiring board, respectively. And a folding step of folding and fixing the outer portion of the flexible wiring board on which the plurality of external electrodes are formed to the back surface side of the integrated circuit chip. Device manufacturing method.
【請求項4】 前記フレキシブル配線基板の前記内部電
極及び前記外部電極が形成されている面とは反対の面に
接着層が形成されていることを特徴とする請求項2に記
載の半導体装置の製造方法。
4. The semiconductor device according to claim 2, wherein an adhesive layer is formed on a surface of the flexible wiring board opposite to a surface on which the internal electrodes and the external electrodes are formed. Production method.
JP2001195087A 2001-06-27 2001-06-27 Semiconductor device and manufacturing method thereof Pending JP2003007899A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001195087A JP2003007899A (en) 2001-06-27 2001-06-27 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001195087A JP2003007899A (en) 2001-06-27 2001-06-27 Semiconductor device and manufacturing method thereof

Publications (1)

Publication Number Publication Date
JP2003007899A true JP2003007899A (en) 2003-01-10

Family

ID=19033122

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001195087A Pending JP2003007899A (en) 2001-06-27 2001-06-27 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP2003007899A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004055891A1 (en) * 2002-12-17 2004-07-01 Fujitsu Limited Semiconductor device and stacked semiconductor device
KR100595889B1 (en) 2004-01-27 2006-06-30 가시오게산키 가부시키가이샤 Semiconductor device having conduction part of upper and lower conductive layer and manufacturing method thereof
JP2016167540A (en) * 2015-03-10 2016-09-15 シチズンホールディングス株式会社 Light emitting module

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004055891A1 (en) * 2002-12-17 2004-07-01 Fujitsu Limited Semiconductor device and stacked semiconductor device
US7196418B2 (en) 2002-12-17 2007-03-27 Fujitsu Limited Semiconductor device and stacked semiconductor device that can increase flexibility in designing a stacked semiconductor device
KR100595889B1 (en) 2004-01-27 2006-06-30 가시오게산키 가부시키가이샤 Semiconductor device having conduction part of upper and lower conductive layer and manufacturing method thereof
JP2016167540A (en) * 2015-03-10 2016-09-15 シチズンホールディングス株式会社 Light emitting module

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