JPH0683408B2 - Television receiver - Google Patents

Description

Description: TECHNICAL FIELD The present invention is a television receiver capable of simultaneously displaying images of a plurality of channels on one screen and displaying images of arbitrary channels among them as still images. It is about machines.

<Prior Art> Currently, in the state of television broadcasting in Japan, the number of broadcasting stations that can be received in one region is at most 9 channels, so if an image of about 9 channels can be simultaneously displayed on one screen, the viewer will be This is convenient because you can check the broadcast contents of all broadcast channels in the area at a glance, and you do not need to perform channel switching operations many times to select the broadcast channel you want to watch.

On the other hand, conventionally, the main screen and the secondary screen are displayed on one screen of the CRT.
A television receiver capable of displaying channel images at the same time has already been proposed (for example, Japanese Patent Application Laid-Open No. 49-2419) and has been partially put into practical use.

However, the television receiver as described above can display images of only two channels on one screen, and if more images are to be displayed, tuners must be added by the number of the images. However, it is practically impossible to simultaneously display images of all broadcasting channels in one area on one screen by the conventional method.

<Objects of the Invention> The present invention has been made in view of the above problems, and a plurality of images can be simultaneously displayed on one screen by using a single tuner, and a receiver is provided. It makes it easy to check the contents of all broadcast channels in one region without complicating or increasing the size of the configuration, eliminating the hassle of channel selection, and displaying the desired 1-channel image on the screen as necessary. It is an object of the present invention to display a still image and also to display a small image with a slight time delay in a part of the still image so as to facilitate confirmation of a changing image.

<Structure of the Invention> In order to achieve the above object, the present invention is directed to a channel selection unit that switches the reception channels of a single tuner, and a buffer memory that stores one image portion of a video signal of one of the selected channels. And a display memory for storing a plurality of images of each selected video signal of one or a plurality of channels,
A buffer memory control unit that controls writing to the buffer memory based on a synchronization signal in a received radio wave, and generates a television synchronization signal based on a clock pulse from a reference oscillation circuit and synchronizes with the television synchronization signal. A display memory control unit for controlling writing / reading to / from the display memory; and a video signal switching unit for switching the input to both the video output unit and the deflection output unit to the CRT to the display memory side, respectively. Sync signal switching unit, central control unit for controlling each unit, CRT
And an operation unit that is operated to select a display mode, the central control unit, when displaying images of a plurality of channels in one screen, displays one image portion during the display scanning period of the synchronization signal of the channels. After storing the video signal in the buffer memory, the contents of the buffer memory are transferred to the display memory during the vertical blanking period of the television sync signal, and this stored content can be read during the display scan period of the television sync signal.
When sending to a CRT to display images of a plurality of channels on one screen and updating each image of a plurality of channels displayed, and when displaying a still image of any one channel on a screen, During the display scanning period of the synchronization signal of the channel, one image portion of the synchronization signal is directly stored in the display memory based on the synchronization signal of the received radio wave,
After the video signal for one image is temporarily stored in the buffer memory during the display scanning period of the synchronizing signal of the channel after a predetermined time, the contents of the buffer memory are changed to the contents of the buffer memory during the vertical blanking period of the television synchronizing signal. And stores it in a part of the display memory, reads the stored contents during the display scanning period of the television synchronizing signal and sends out to the CRT, and displays the still image of the 1-channel in the center of the screen. A plurality of still images are displayed at the corners of the screen with a time lag from the still images.

<Examples> Hereinafter, the present invention will be described in detail based on Examples shown in the drawings.

FIG. 1 is a block diagram of the entire television receiver of the present invention, which comprises a main body circuit portion A and an image processing circuit portion B.

The main circuit portion A includes an antenna 1 and a single tuner 2
A video amplification section 3, a video signal processing section 4, a synchronization signal processing section 5, a video output section 8, a deflection output section 9, and a CRT 10.
And a deflection coil 10a, and the video signal switching unit 6 is provided between the video signal processing unit 4 and the video output unit 8.
However, the synchronization signal switching unit 7 is interposed between the synchronization signal processing unit 5 and the deflection output unit 9.

The image processing circuit portion B also selects a channel selection section 11 for switching the receiving channel of the tuner 2, a multiplexer 12 for introducing the video signal from the video signal processing section 4, and an analog signal from the multiplexer 12 for converting it into a digital signal.
An A / D converter 13, a buffer memory 15 that temporarily stores one field of a video signal, a buffer memory control unit 14 that controls writing to the buffer memory 15 based on a synchronization signal of a received radio wave, and a clock pulse. A reference oscillation circuit 16 to be generated and a display memory 18 for storing one field of each video signal of each of a plurality of channels (9 channels in this embodiment) to be displayed on the CRT 10 or one frame of the video signal of one channel. A display memory control unit 17 for controlling writing and reading to and from the display memory 18 by generating a television synchronization signal from the clock pulse and the television synchronization signal, and a digital video signal read from the display memory 18. A D / A converter 19 for converting into an analog amount, the buffer memory control unit 14 and the display memory control unit 17 A central control unit (CPU) 20 for controlling the video signal switching unit 6, the synchronizing signal switching unit 7, etc., a program ROM 21 for storing the program of the central control unit 20, a work RAM 22, and a display mode of the CRT 10 for selecting. Operation unit 23 operated by and central control unit
A control signal output unit 24 for operating the channel selection unit 11, the video signal switching unit 6, and the synchronization signal switching unit 7 based on the signal from 20 is provided.

In the above configuration, by operating the operation unit 23 to select a display mode, a desired 1-channel image is displayed on the CRT10 screen like a normal television receiver, and the CRT10 screen is also displayed. Images of multiple channels (images of 9 channels in this embodiment) are displayed at the same time, or images of 1 channel are displayed as still images on the CRT 10 screen. The operation in each mode will be described while describing the more detailed configuration of the memory control unit 17.

(B) Normal display mode The television radio wave of the channel received by the antenna 1 and tuned by the tuner 2 is amplified by the video amplification section 3,
It is input to the video signal processing unit 4 and the synchronization signal processing unit 5. In the video signal processing unit 4, the video signal is separated into a luminance signal (Y signal) and two color difference signals (RY signal and BY signal). On the other hand, the sync signal processing unit 5 separates the received signal into a horizontal sync signal and a vertical sync signal and outputs them. At this time, in the video signal switching unit 6, the switching piece 6c is connected to the contact 6a, and the output of the video signal processing unit 4 is input to the video output unit 8. In the other synchronizing signal switching unit 7, the switching piece 7c is connected to the contact 7a, and the output of the synchronizing signal processing unit 5 is input to the deflection output unit 9. CRT1 like this
Since a video signal is input to the main body and a synchronizing signal is input to the deflection coil 10a, a desired 1-channel image is displayed on the screen of the CRT 10.

(B) Multi-channel image display (multi-mode) When the multi-mode is set in the operation unit 23, the CPU 20 operates to control each unit so as to display a plurality of images on the CRT10 screen. A signal from the CPU 20 instructs the control signal output section 24 to the channel selection section 11 to select any one of a plurality of channels, for example, the A channel, whereby the tuner 2 selects the A channel. . The video signal of channel A is input to the multiplexer 12 via the video amplifier 3 and the video signal processor 4. The multiplexer 12 sequentially extracts the Y signal, the RY signal, and the BY signal from the video signals.
It is sent to the A / D converter 13. The A / D converter 13 converts an analog signal into a digital signal. The video signal converted into a digital amount in this way is stored in the buffer memory control unit.
It is stored in the buffer memory 15 through the buffer memory 14 at the timing of the buffer memory controller 14.

FIG. 2 is a block diagram showing the internal structure of the buffer memory control unit 14, and FIG. 3 is a time chart of the buffer memory control unit 14 in the multimode. The operation when controlling writing to the memory will be described. Command signal S from the CPU 20
b is input to the writing period detection unit 26. The writing period detector 26 introduces a synchronizing signal of the received radio wave, and in response to the command signal Sb, generates a writing pulse of the display scanning period length of the one field from the synchronizing signal of the receiving radio wave.
To be precise, the write pulse has a length from the falling edge of the vertical synchronizing signal of the received radio wave to the rising edge of the next vertical synchronizing signal, as shown in FIG. While the write pulse is rising, the write row counter 27 and the write column counter 28 count the clock pulse from the reference oscillation circuit 16 and output the row-direction and column-direction address signals, respectively. At this time, in the changeover switches 30 and 31 respectively connected to the write row counter 27 and the write column counter 28, the changeover pieces 30c and 31c are connected to the contacts 30a and 31a, so that the write row counter 27 and the write Each output of the column counter 28 is supplied to the buffer memory 15, and the storage address of the buffer memory 15 is designated. On the other hand, the video signal stored in the buffer memory 15 includes the multiplexer 12, the A / D converter 13, and the changeover switch 29.
Supplied through. In the multiplexer 12, the three contacts 12a, 12b, 12c are sequentially closed in synchronization with the horizontal synchronizing signal of the received radio wave, so that the Y signal, the RY signal and the BY signal are sequentially A / A for each horizontal synchronizing. It is sent to the D converter 13, A / D converted, and stored in the buffer memory 15.

Thus, when one field of the video signal of the required channel (A channel) is stored in the buffer memory 15,
The operations of the write row counter 27 and the write column counter 28 are stopped, and the changeover switches 30 and 31 have the changeover pieces 30a and 3a.
1a switches to the other contacts 30b and 31b, and the buffer memory 1
The address signal line of 5 is connected to the address bus of the CPU 20, and the switching piece 29c of the changeover switch 29 is switched to the contact 29b, so that the data signal line of the buffer memory 15 is connected to the CPU 20.
Connect to the data bus. This state is the buffer memory
When the display memory 18 can transfer the stored contents of 15 to the display memory 18, and the display memory 18 is ready to accept the transfer, the transfer is started. In FIG. 2, reference numeral 25 is a still image control unit and 32 is a ternary counter.

On the other hand, the display memory 18 is set with the same number of storage areas corresponding to the images of a plurality of channels (9 channels) to be displayed on the CRT 10, and the video signals stored in these storage areas are changed from clock pulses. It is accessed by the generated address signal and is displayed on the CRT 10 by the television synchronizing signal which is also generated from the clock pulse.

The operation in this case will be described based on the block diagram of the display memory control unit 17 in FIG. A control signal is sent from the control signal output unit 24 to the video signal switching unit 6 and the synchronization signal switching unit 7 in response to a command from the CPU 20, and the switching pieces 6c of both switching units 6 and 7,
7c is switched to the contacts 6b and 7b, respectively, and as a result, the input terminals of the video output section 8 and the deflection output section 9 are respectively in the display memory.
Switch to 18 side. In the display memory control unit 17, the horizontal synchronizing signal generation counter 33 counts clock pulses to generate a television horizontal synchronizing signal and also generates a column direction address signal for the display memory 18 synchronized with the television horizontal synchronizing signal. To do. The vertical sync signal generation counter 34 generates a television vertical sync signal based on the television horizontal sync signal from the horizontal sync signal generation counter 35, and at the same time, generates a row direction address signal for the display memory 18. The display control circuit 35 controls the changeover switches 36, 37, 38 in response to the television horizontal synchronizing signal and the television vertical synchronizing signal. Changeover switch 36,3
In FIG. 7, the switching pieces 36b and 37b are connected to the contacts 36a and 37a, respectively, so that the address signals generated by the both synchronizing signal generation counters 33 and 34 are supplied to the display memory 18, respectively, and the display signals are generated by the address signals. 18 is accessed and the stored contents of the display memory 18 are read. At this time,
Since the contact 38a of the changeover switch 38 is closed,
The video signal read from the display memory 18 is sent to the D / A converter 19, converted into an analog signal, and input to the video output unit 8 through the video signal switching unit 6. Further, the television horizontal synchronization signal generated by the horizontal synchronization signal generation counter 33 and the television vertical synchronization signal generated by the vertical synchronization signal generation counter 34 (hereinafter collectively referred to as television synchronization signal) are synchronized signal switching. Input to the deflection output unit 9 through the unit 7. Then, during the display scanning period of these television synchronizing signals, the video signals of a plurality of channels stored in the display memory 18 are displayed on the CRT 10, and the image of a predetermined channel among the images of a plurality of channels in one screen is updated and displayed. It

During the vertical retrace line of the television synchronizing signal, the changeover pieces 36b, 3 of the changeover switches 36, 37 are controlled by the control signal of the display control circuit 35.
7b switches to contacts 36c and 37c respectively, and display memory 1
The address signal line 8 is connected to the address bus of the CPU 20, and the contact 38c of the changeover switch 38 is closed so that the data signal line of the display memory 18 is connected to the data bus of the CPU 20. This state is a state in which data transfer from the buffer memory 15 can be received. At this time, on the buffer memory 15 side, the CPU address bus is connected to the address signal line of the buffer memory 15, and the CPU 20 data bus is connected to the buffer memory 1
If it is connected to the data signal of 5, the display memory 18 and the buffer memory 15 are connected via the address bus and the data bus of the CPU 20. When connected in this way, the CPU 20 reads the stored contents from the buffer memory 15 and transfers this to the corresponding storage area of the display memory 18. This transfer is repeated for each vertical blanking period of the television sync signal, and the required video signal for one field of one channel (A channel) is transferred. When this is displayed on the CRT 10, the next channel (B in this example) is displayed. The next cycle of storing and displaying one field of the video signal of the (channel) is started, and the same operation as the above-described operation of storing and displaying the video signal of the A channel is repeated. B to I are selected in this manner
One field of the video signal of the channel is temporarily stored in the buffer memory 15, then transferred to the display memory 18, read from the display memory 18, and displayed at a predetermined position on the CRT 10 screen. An image as shown in the block diagram of FIG. 5 is formed.

(C) Still image display (still mode) When the still mode is selected by the operation unit 23, the channel selection in the tuner 2 is fixed to any one channel (D channel in this example) by a command from the CPU 20. . Also CP
A command signal Sa is output from U20 and enters the still image control unit 25 of the buffer memory control unit 14, and this still image control unit 25 outputs a signal corresponding to the command signal Sa to the writing period detection unit 26. In response to this, the writing period detecting unit 26 generates a writing pulse having a length of two display scanning periods of the reception radio wave of the predetermined channel (D channel) as shown in the time chart of FIG. This write pulse is exactly the length from the fall of the vertical sync signal of the received radio wave to the rise of the second vertical sync signal, and the write pulse enables writing of the video signal for one frame. . The write pulse is generated by the horizontal sync signal generation counter 33 and the vertical sync signal generation counter of the display memory control unit 17.
Sent to 34. The write pulse is also sent to the changeover switches 36, 37 of the display memory control unit 17, and in the changeover switches 36, 37, the changeover pieces 36b, 37b have contact points 36a,
Switch to 37a. Therefore, the address signal is supplied to the display memory 18 while the write pulse is rising, that is, during the two display scanning periods of the synchronizing signal of the received radio wave. On the other hand, on the buffer memory 15 side, the multiplexer 12 switches the contacts in a predetermined order as shown in FIG. That is, the contact 12a is closed during the first display scanning period of the received radio wave, and only the Y signal is introduced, and the two contacts 12b and 12c are alternately closed every horizontal synchronization period during the second display scanning period, and R-Y The signal and the BY signal are alternately introduced. These video signals are sent to the A / D converter 13
After being converted to a digital signal with, the selector switch 29
Is sent to the changeover switch 38 in the display memory control unit 17 via. At this time, the changeover switch 38 has a contact 38
Since b is closed, the video signal sent from the buffer memory control unit 14 side is input to the data signal of the display memory 18. An address signal synchronized with the display scanning period of the received radio wave is already stored in the display memory 18, so that one frame of a video signal of a predetermined channel is stored in a predetermined storage area by addressing the address signal. To be done.

The operation of reading the video signal for one frame stored in the display memory 18 and displaying it on the CRT 10 is the same as in the case of the (b) multimode, and the video signal switching unit 6 and the synchronization signal switching unit 7 are respectively Switching pieces 6c, 7c are contact points 6b, 7b
The input terminals of the video output unit 8 and the deflection output unit 9 are switched to the display memory 18 side. In the display memory control unit 17, the horizontal sync signal generation counter 33 generates a television horizontal sync signal and a column direction address signal for the display memory 18 synchronized with the television horizontal sync signal. Further, the vertical synchronizing signal generation counter 34 generates a television vertical synchronizing signal and a row direction address signal for the display memory 18. Under the control of the display control circuit 35, the changeover switches 36 and 37 have switching pieces 36b and 37b connected to the contacts 36a and 37a, respectively, and the television horizontal synchronizing signal and the television vertical synchronizing signal are respectively displayed in the display memory. The display memory 18 is supplied to the display memory 18, and the display memory 18 is accessed by the television synchronizing signal to read the stored contents of the display memory 18. Further, since the contact 38a of the changeover switch 38 is closed, the video signal read from the display memory 18 is sent to the D / A converter 19 and converted into an analog signal, and the video signal is output through the video signal switching unit 6. Enter in 8. Further, the television sync signal is input to the deflection output unit 9 through the sync signal switching unit 7. As a result, the predetermined 1-channel (D-channel) video signal stored in the display memory 18 is displayed on the CRT 10. After that, the stored contents of the display memory 18 are not updated and the same stored contents are continuously read and displayed. Therefore, the CRT 10 has a predetermined channel (D channel) as shown in the configuration diagram of FIG.
Image is displayed in a static state.

Then, in such a state, a predetermined time (for example, 0.1 seconds to 1
Second) has elapsed, the CPU 20 gives the command Sb to the writing period detection unit 26. As a result, the video signal for one frame is written in the buffer memory 15 by the same operation as described above at the timing shown in FIG. Then, in the subsequent vertical blanking period, changeover switches 29, 30, 31 and
36, 37, 38 are respectively connected to the address bus or the data bus of the CPU 20, and the image data in the buffer memory 15 is gradually transferred from the buffer memory 15 to a predetermined storage area of the display memory 18. Such a transfer operation is repeated during the vertical blanking period. When the transfer of the image data for one frame is completed, the command Sb is given from the CPU 20 to the writing period detection unit 26 again after a predetermined time elapses, and the same operation is performed to cause the buffer memory 15 to change to a different one
The video signals for the frames are once written, and then the image data in the buffer memory 15 are sequentially transferred to the display memory 18 during the vertical blanking period and stored in a storage area different from the case described above.

Thus, the same operation as described above is repeated several times,
As a result, the display memory 18 stores the image data for one frame of the predetermined channel immediately after the still mode is selected, and further the image data for several frames of the same channel for a predetermined time thereafter is equivalent to one frame. The data is intermittently stored in a predetermined storage area.

Then, the stored contents of the display memory 18 are sequentially read out by the same operation as the above-described read-out operation, converted into an analog signal by the D / A converter 19, and then the video switching unit 6 and the video output unit 8 As a result, the image of the predetermined channel (D channel) is displayed in the center part on the screen of the CRT10 as shown in FIG. 7, and the still image is displayed in the four corners of the screen. The four small images D ', D ", D, D'of the same channel, which are slightly shifted (delayed) in time, are displayed at the same time.

<Effects of the Invention> As described above, according to the present invention, by switching the operation unit to the mode for displaying images of a plurality of channels (multi mode), images of a plurality of channels are simultaneously displayed on one CRT screen. Therefore, the viewer can instantly check the broadcast contents of a plurality of channels when desired, does not need to perform troublesome channel operations, and can easily select a desired broadcast, which is convenient. Then, each image of multiple channels displayed on one screen is displayed as a still image, and these still images are sequentially updated, so it is only possible to grasp the current broadcast contents of each channel at a glance. In addition, there is an excellent effect that it is very easy to check how the broadcast content of each channel is changing.

Further, when the central control unit (CPU) is in a mode (multi mode) for displaying images of a plurality of channels on one screen, a video signal for one image is temporarily buffered during the display scanning period of the synchronization signal of the channels. After that, the contents of the buffer memory are sequentially transferred to the display memory during the vertical retrace line of the television sync signal, and the stored contents are read out and sent to the CRT during the display scan period of the television sync signal. , The image on the CRT screen is continuously updated, and a smooth image is obtained, and the visual effect is very natural.

In addition to the synchronization signal of the channel selected by the tuner, a television synchronization signal for displaying an image different from the television video signal being received based on the clock pulse from the reference oscillation circuit The video signal switching unit and the synchronization signal switching unit switch the inputs to the video output unit and the deflection output unit to the CRT respectively, so that when the synchronization signal included in the television broadcast signal is disturbed, It is possible to display a high-quality still image without causing a problem that the boundary line of each of the plurality of still images sways and is very conspicuous when the still image is displayed.

Further, in the present invention, a mode in which the central control unit displays an image of any one channel on one screen (still mode)
In this case, a desired one-channel still image is displayed in the center of the screen, and a plurality of still images slightly different in time from the still images are displayed in the corners of the screen. You can check the image carefully in the center of the screen, and a still image that is slightly different in time from this still image is displayed around the still image displayed in the center of the screen. It is easy to visually grasp the change with time.

Further, in the present invention, first, by switching the operation unit to a mode (multi mode) for displaying images of a plurality of channels, it is possible to simultaneously display the images of a plurality of channels on one CRT screen and to display a broadcast that may be of interest. A channel is selected, and then the operation unit is switched to a mode (still mode) in which a still image of one channel is displayed, the still image of the selected channel is displayed in the center of the screen, and the time is slightly delayed from the still image. Still images can be displayed in the corners of the screen, and you can better check the broadcast content even for the channels you have selected because you feel like you are interested, so you can steadily select the channel of the broadcast content you want to watch step by step. .

In addition, the present invention, as a memory for storing images, a buffer memory having a storage capacity for one selected image,
It has a simple configuration with one display memory for storing multiple images of each selected video signal of one or multiple channels, and the number of images to be displayed on one screen can be easily set. it can.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of a buffer memory control unit thereof, FIG. 3 is a time chart showing a storage operation in a multi mode, and FIG. 4 is a display memory control unit. Fig. 5 is a block diagram of the
CRT screen configuration diagram, FIG. 6 is a time chart showing the storage operation in still mode, and FIG. 7 is a CRT in still mode.
It is a block diagram of a screen. 2 ... tuner, 6 ... video signal switching unit, 7 ... synchronization signal switching unit, 10 ... CRT, 11 ... tuning unit, 14 ...
Buffer memory control unit, 15 ... Buffer memory, 17 ...
Display memory control unit, 18 ... Display memory, 20 ... Central control unit (CPU), 23 ... Operation unit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-49-46330 (JP, A) JP-A-49-129419 (JP, A) JP-A-56-132067 (JP, A)

Claims (1)

[Claims] 1. A single tuner switches channels at a constant cycle to store video signals of each channel, and the stored video signals are sequentially read to display images of a plurality of channels on one screen. A television receiver for displaying a still image of any one channel on a screen, which stores only one image portion of a video signal of one of the selected channel and a tuning unit for switching the receiving channel of the tuner. Buffer memory, a display memory that stores a plurality of images of each selected video signal of one or a plurality of channels, and a buffer memory that controls writing to the buffer memory based on a synchronization signal in a received radio wave. The control unit generates a television synchronizing signal based on the clock pulse from the reference oscillation circuit, and Writing to emissions synchronizing signal said display memory in synchronism with a display memory control unit that controls reading, in the previous stage of the image output unit and deflection output unit to CRT,
A video signal switching unit and a synchronization signal switching unit that switch the inputs to the respective units to the display memory side, a central control unit that controls the respective units, and an operation unit that is operated to select a CRT display mode. When displaying images of a plurality of channels in one screen, the central control unit stores a video signal for one image in a buffer memory during a display scan period of a synchronization signal of the channels, and then stores the reference signal. The contents of the buffer memory are transferred to the display memory during the vertical blanking period of the television synchronizing signal based on the clock pulse from the oscillator circuit, and the stored contents are read out during the display scanning period of the television synchronizing signal and sent to the CRT. To display the images of multiple channels on one screen and to update each image of the displayed multiple channels. When a still image of one channel is displayed, one image portion of the video signal is stored in the display memory based on the synchronization signal of the received radio wave during the display scanning period of the synchronization signal of the channel, and After the video signal for one image is temporarily stored in the buffer memory during the display scanning period of the synchronizing signal of the channel, the buffer memory is stored during the vertical retrace period of the television synchronizing signal based on the clock pulse from the reference oscillation circuit. The contents are transferred to the display memory and stored in a part of the display memory, the stored contents are read out during the display scanning period of the television synchronizing signal and sent to the CRT, and the 1-channel still image is displayed at the center of the screen. A television set characterized by displaying a plurality of still images at the corners of the screen with a slight time difference from the still images while displaying the images. Down receiver.