JPS6116683A - Television receiver - Google Patents

Abstract

PURPOSE:To easily confirm an image, and simplify the constitution and reduce its size by switching an operation part to a multimode and displaying images of plural channels simultaneously on a CRT screen, and switching the operation part to a still mode and displaying an image of one optional channel over the entire CRT screen as a still picture. CONSTITUTION:Display modes are selectedby operating the operation pat 23 to display an image of one desired channel on the screen of the CRT10 like a normal television receiver and also displays images of plural channels simultaneously while displaying the image of one channel as a still picture. For example, when the multimode is set by the operation part 23, a CPU20 operates to control respective parts so that plural images are displayed on the screen of the CRT10. Further, when the still mode is selected by the operation part 23, a tuner 2 is fixed to one channel under the command of the CPU20. Then, an image of a specific channel is displayed in a still state.

Description

[Detailed description of the invention] Technical fields> The present invention relates to a television receiver.

<Prior art> Currently, in the state of television broadcasting in Japan, there are at most 9 channels of broadcasting stations that can be received in a region. Therefore, if images from about 9 channels can be displayed simultaneously on one screen, the viewers can It is convenient because the broadcast content of all broadcast channels in the area can be checked at a glance, and there is no need to repeatedly switch channels to select the desired broadcast channel.

In response to this, television receivers have been proposed that display images of two channels, main and sub, simultaneously on one screen of a CRT (for example, in Japanese Patent Application Laid-Open No. 49-1999)
No. 419), some of which have been put into practical use.

However, the above television receiver can only display images from two channels on one screen, and if you want to display more images, you have to add a tuner for the number of images. However, it is practically impossible to simultaneously display images of all broadcast channels in one area on one screen using conventional methods.

<Object of the Invention> The present invention has been made in view of the above-mentioned problems, and it is possible to simultaneously display a plurality of images on one screen using a single tuner. Without complicating the configuration or increasing the size of the system, it is possible to easily check the contents of all broadcast channels in the area and eliminate the trouble of selecting channels.

It is an object of the present invention to facilitate confirmation of a changing image by displaying a desired channel image as a still image on a screen as needed.

<Structure of the Invention> In order to achieve the above object, the present invention includes a tuning section that switches the reception channel of a single tuner, and a buffer memory that stores one image of the video signal of any selected channel. a display memory that stores one image of each video signal of one or more selected channels; a buffer memory control unit that controls writing to the buffer memory based on a synchronization signal in received radio waves; and a clock pulse. a display memory control unit that generates a television synchronization signal based on the television synchronization signal and controls reading and writing to the display memory in synchronization with the television synchronization signal;
A video signal switching section and a synchronization signal switching section that are located before the video output section and the deflection output section to switch the inputs to the two sections to the display memory side, respectively, and a central control section that controls each of the sections. and an operation section operated to select a display mode of the CRT, and when displaying images of multiple channels on two screens, the central control section controls display scanning of synchronizing signals of the channels. During the period, the video signal for one image was stored in one buffer memory,
The contents of the buffer memory are transferred to the display memory during the vertical retrace period of the television synchronization signal, and the stored contents are read out and sent to the CRT during the display scanning period of the television synchronization signal, so that any part of the main screen can be displayed on the main screen. When displaying a still image of one channel, one image of the video signal is directly stored in the display memory based on the synchronization signal of the received radio wave during the display scanning period of the synchronization signal of the channel, and the stored contents are It is configured so that it is read out and sent to the CRT during the display scanning period of the television synchronization signal.

<Example> Hereinafter, the present invention will be described in detail based on an example that shows one aspect of the invention.

FIG. 1 is a block diagram of the entire television receiver of the present invention, which consists of a main circuit section A and an image processing circuit section B. As shown in FIG.

The main circuit section A includes an antenna 1, a single tuner 2, a video amplification section 3, a video signal processing section 4, a synchronization signal processing section 5, a video output section 8, a deflection output section 9, and a CRTIO.
and a deflection coil 10a, with a video signal switching section 6 between the video signal processing section 4 and the video output section 8, and a video signal switching section 6 between the synchronization signal processing section 5 and the deflection output section 9. A synchronizing signal switching section 7 is interposed in each case.

The image processing circuit section B also includes a tuning section 11 that switches the receiving channel of the tuner 2, a multiplexer 12 that introduces the video signal from the video signal processing section 4, and converts the analog signal from the multiplexer 12 into a digital signal. An A/D converter 13, a buffer memory 15 that temporarily stores one field of a video signal, a buffer memory control unit 14 that controls writing to the buffer memory 15 based on a synchronization signal of received radio waves, and a clock pulse. A reference oscillation circuit 16 to be generated, and a display memory 18 that stores one field of each video signal of a plurality of channels (nine channels in this embodiment) to be displayed on the CRTlo, or one frame of one channel of video signal. a display memory control section 17 that generates a television synchronization signal from the clock pulse and controls writing and reading of the display memory 18 using the television synchronization signal; Converting video signals to analog quantities D
/A funverter 19 and the buffer memory control section 14
A central control unit (C, PU) that controls the display memory control unit 17, video signal switching unit 6, synchronization signal switching unit 7, etc.
20, a program ROM 21 that stores programs for the central control unit 20, a work RAM 22, and a CR'TI
The operation section 23 is operated to select the display mode of O.
and the channel selection section 1 based on a signal from the central control section 20.
1, a video signal switching section 6, and a control signal output section 24 for operating the synchronization signal switching section 7.

In the above configuration, by operating the operation unit 23 and selecting the display mode, the desired one channel image is displayed on the CRTIO screen like a normal television receiver, and also on the CRT10 screen. Images of multiple channels (in this example, images of 9 channels) are displayed simultaneously (1), or images of one channel are displayed as a still image on the CRTIO screen. The operation in each mode will be explained while explaining the more detailed configuration of the display memory control section 17.

(b) Normal display mode.

The television radio waves of the channel received by the antenna 1 and selected by the tuner 2 are amplified by the video amplification section 3,
The signal is input to the video signal processing section 4 and the synchronization signal processing section 5. In the video signal processing section 4, the video signal is separated into a luminance signal (Y signal) and two color difference signals (RY signal, BY signal). On the other hand, the synchronization signal processing section 5 separates the received signal into a horizontal synchronization signal and a vertical synchronization signal and outputs the separated signals. At this time, in the video signal switching section 6, the switching piece 6c is connected to the contact 6.
a, and the output of the video signal processing section 4 is input to the video output section 8. In the other synchronizing signal switching section 7, the switching piece 7c is connected to the contact 7a, and the output of the synchronizing signal processing section 5 is input to the deflection output section 9. In this way, since the video signal is input to the CRTIO main body and the synchronization signal is input to the deflection coil 10a, a desired one-channel image is displayed on the CRTIO screen.

(b) Image display of multiple channels (multi-mode) When the multi-mode is set in the operation section 23, the CPU 2
0 operates to control each part to display multiple images on the CRTIO screen. First, the control signal output part 24 sends a signal from the CPtJ 20 to the channel selection part 11 to select which of the multiple channels to display. The tuner 2 instructs the tuner to select one channel, for example, the A channel, and thereby the tuner 2 selects the A channel. The video signal of the A channel is input to the multiplexer 12 via the video amplifying section 3 and the video signal processing section 4. The multiplexer 12 sequentially extracts the Y signal, the RY signal, and the BY signal from the video signal and sends them to the A/D converter 13. The A/D converter 13 converts analog signals into digital signals. The video signal thus converted into a digital quantity passes through the buffer memory controller 14 and is sent to the buffer memory 15 at the timing of the buffer memory controller 14.
is stored in

FIG. 2 is a block diagram showing the internal configuration of the buffer memory control section 14, and FIG. 3 is a time chart of the buffer memory control section 14 in multi mode. Based on both figures, the buffer memory control section 14 controls the buffer memory. The operation when controlling writing will be explained. The command signal sb from the CPU 20 is input to the write period detection section 26.

The write period detection section 26 receives a synchronization signal of the received radio wave, and generates a write pulse having a display scanning period length of one field from the synchronization signal of the received radio wave in response to the command signal sb. To be precise, the write pulse is the third
As shown in the figure, it is the length from the fall of the vertical synchronization signal of the received radio wave to the rise of the next vertical synchronization signal. While the write pulse is rising, the write row counter 27 and the write column counter 28 count the tarock pulses from the reference oscillation circuit 16 and output address signals in the row direction and column direction, respectively. At this time, the changeover switches 30 and 31 connected to each of the write row counter 27 and the write column counter 28,
The switching pieces 30c and 31c are connected to the contacts 30a and 31a, so that the outputs of the external write row counter 30 and the write column counter 31 are supplied to the buffer memory 15, and the storage address of the buffer 7 memory 15 is specified. be done. On the other hand, the video signal stored in the buffer 77 memory 15 is
It is supplied through multiplexer 12, A/D converter 13 and changeover switch 29. In the multiplexer 12, the three contacts 12a, 12b, and 12c are sequentially closed in synchronization with the horizontal synchronization signal of the received radio wave.
The Y signal, RY signal, and BW signal are sequentially sent to the A/D converter 13 for each horizontal opening period, A/D converted, and stored in the buffer memory 15.

When one field of the video signal of the desired channel (channel A) is stored in the buffer memory 15 in this way, the write row counter 27 and the write column counter 28
operation is stopped, the switching pieces 30a and 31a are switched to other contacts 30b and 31b in the changeover switches 30 and 31, and the address signal line of the buffer memory 15 is connected to the address bus of the CPt 120, and In the changeover switch 29, the changeover piece 29c is switched to the contact 29b, and the data signal line of the buffer memory 1''5 is connected to CPt.
120 data bus. This state is buffer 7
Memo 1) When the storage contents of 15 can be transferred to the display memory 18 and the display memory 18 side is ready to accept the transfer, the transfer is started. In FIG. 2, reference numeral 25 is a still image control section, and 26 is a ternary counter.

On the other hand, the same number of storage areas are set in the display memory 18 corresponding to the images of multiple channels (9 channels) to be displayed on the CRT10, and the video signals stored in these storage areas are The QCRT is accessed by an address signal generated from the QCRT and by a television synchronization signal also generated from the clock pulse.
Displayed on IO.

The operation in this case will be explained based on the block diagram of the display memory control section 17 shown in FIG. C, Ptl 20, a control signal is sent from the control signal output section 24 to the video signal switching section 6 and the synchronization signal switching section 7, and the switching pieces 6 et 7 c of both switching sections 6 and 7 are connected to the contact 6 b, respectively.
, 7b, and as a result, the input terminals of the video output section 8 and the deflection output section 9 are respectively switched to the display memory 18 side. In the display memory control unit 17, a horizontal synchronization signal generation counter 33 counts clock pulses to generate a television horizontal synchronization signal, and also generates a column direction address signal for the display memory 18 in synchronization with the television horizontal synchronization signal. do. The main vertical synchronization signal generation counter 34 generates a television vertical synchronization signal based on the television horizontal synchronization signal from the horizontal synchronization signal generation counter 33, and simultaneously generates a row direction address signal for the display memory 18. do. display.

The control circuit 35 has a changeover switch 36, corresponding to the television horizontal synchronization signal and the television vertical synchronization signal.
37 and 38 are controlled. In the changeover switches 36+37, the changeover pieces 36b and 37b are contacts 36a and 37a, respectively.
Therefore, the address signals generated by both the synchronization signal generation counters 33 and 34 are respectively supplied to the display memory 18, and the display memory 18 is accessed by this address signal, and the storage contents of the display memory 18 are is read out. At this time, the changeover switch 38 is at contact 3.
8a is closed, the video signal read from the display memory 18 is sent to the D/A converter 19, converted to an analog signal, and input to the video output section 8 via the video signal switching section 6. Furthermore, the television horizontal synchronization signal generated by the horizontal synchronization signal generation counter 33 and the television vertical synchronization signal generated by the vertical synchronization signal generation counter 34 (hereinafter collectively referred to as television synchronization signals) are synchronization signal switching. It is inputted to the deflection output section 9 through the section 7. During the display scanning period of these television synchronization signals, the video signals of multiple channels stored in the display memory 18 are displayed on the CRTIO, and the image of a predetermined channel among the images of multiple channels on one screen is updated and displayed. Ru.

Vertical retrace period 1 of television synchronization signal is display system @
The switching pieces 36b and 37b of the changeover switches 36 and 37 are switched to the contacts 36c and 37c, respectively, by the control signal of the circuit/circuit 35, and the address signal line of the display memory 18 is changed to CP.
U2. When the contact 38c of the changeover switch 38 is closed, the data signal line of the display memory 18 is connected to the data bus of the CPU 20.

This state is a state in which data transfer from the buffer memory 15 can be accepted. At this time, if the address bus of the CPU is connected to the address signal line of the buffer memory 15 on the buffer memory 15 side, and the data bus of cPu2o is connected to the data signal line of the buffer memory 15, then the display memory 18 and the buffer memory 15 are connected. is connected via the address bus and data bus of C and PU20. 4 above this! If continued, the CPU 20 reads the stored contents from the buffer memory 15 and transfers them to the corresponding storage area of the display memory 18. This transfer is repeated every vertical blanking period of the television synchronization signal, and the required one channel (
A channel) transfers one field worth of video signal,
When this is displayed on CRTl 0, the next cycle starts in which 1 file Y of the video signal of the next channel (D channel in this example) is stored and displayed (1), and the video signal of the above-mentioned A channel is displayed. Repeat the same operation as storing and displaying. In this way, one field of the video signals of channels B to ■, which are sequentially selected, is temporarily stored in the buffer memory 15, and then transferred to the display memory 18, read from the display memory 18, and displayed on the CRTIO screen. The image is displayed at a predetermined location, thereby forming an image on the CRT screen as shown in the block diagram of FIG.

(c) Displaying still images (still mode).

When the still mode is selected on the operation unit 23, CPt32
The six selected stations in tuner 2 are fixed to any one channel (channel D in this example) by the command from tuner 2. Further, a command signal Sa is output from the CPU 20 and input to the still image control section 25 of the buffer memory control section 14, and this still image control section 25 outputs a signal corresponding to the command signal Sa to the write period detection section 26. In response to this, the write period detecting section 26 generates a write pulse having a length of one display scanning period of the received radio wave of a predetermined channel (D channel) as shown in time chart F in FIG. This write pulse is exactly the length from the fall of the vertical synchronization signal of the received radio wave to the rise of the second vertical synchronization signal, and this write pulse is the length of the vertical synchronization signal of the received radio wave.
Video signals for frames can be written. The write pulse is sent to the horizontal synchronizing signal generation counter 33 and vertical synchronizing signal generation counter 34 of the display memory control section 17.

The writing pulse is also sent to the changeover switch 36.37 of the display memory control section 17, and in the changeover switch 36.37, the changeover pieces 36b, 37b are switched to the contacts 36a, 37a. Therefore, the address signal is supplied to the display memory 18 while the write pulse is rising, that is, during the two display scanning periods of the synchronization signal of the received radio wave. On the other hand, on the buffer memory 15 side, multiplexer 1
2 switches the contacts in a predetermined order as shown in FIG. Immediately, during the first display scanning period of the received radio wave, the contact 12a is closed and only the Y signal is introduced, and during the second display scanning period, the two contacts 12b and 12c are alternately closed every horizontal opening period.
The RY signal and the BY signal are introduced alternately. These video signals are converted into digital signals by the A'/D converter 13, and then sent to the changeover switch 38 in the display memory control section 17 via the changeover switch 29. At this time, the contact 38b of the changeover switch 38 is closed, so the video signal sent from the buffer memory control section 14 is input to the data signal line of the display memory 18. Since this display memory 18 has already entered an address signal synchronized with the display scanning period of the received radio wave, one frame of the video signal of a predetermined channel is stored in a predetermined storage area by addressing the address signal. be done.

The operation of reading one frame worth of video signal stored in the display memory 18 and displaying it on the CRT10 is the same as in the case of (b) multi mode, and the video signal switching section 6 and synchronization signal switching section 7 Each switching piece 6c,
7c is switched to contact 6b+7b, thereby switching each input terminal of the video output section 8 and the deflection output section 9 to the display memory 18 side. Display memory control unit 1'7.
, the horizontal synchronization signal generation counter 33 generates a television horizontal synchronization signal and a column direction address signal for the display memory 18 synchronized with the television horizontal synchronization signal. Further, a vertical synchronization signal generation counter 34 generates a television vertical synchronization signal and a row direction address signal for the display memory 18. At this time, the changeover switches 36 and 37 are turned off under the control of the display control circuit 35.

Switching pieces 36b and 37b are connected to contacts 36a+37b, the television horizontal synchronization signal and the television vertical synchronization signal are respectively supplied to the display memory 18, and the display memory 18 is accessed by the television synchronization signal, The contents of display memory 18 are read out. Further, the contact 38a of the changeover switch 38 is closed, so the video signal read out from the display memory 18 is sent to the D/A converter 19, converted into an analog signal, and passed through the video signal switching unit 6 to the video output unit. Enter 8. Further, the television synchronization signal is inputted to the deflection output section 9 through the synchronization signal switching section 7.

As a result, the video signal of one predetermined channel (D channel) stored in the display memory 18 is displayed on the CRTIO. After this, the storage contents of the display memory 18 are not updated and the same storage contents are read out and displayed continuously, so C
An image of a predetermined channel (D channel) as shown in the block diagram of FIG. 7 is displayed on the RTIO in a static state.

<Effects of the Invention> As described above, according to the present invention, images of multiple channels are displayed simultaneously on the CR1 screen by switching the operation unit to multi-mode (multiple image display).
It is convenient for viewers to instantly check the broadcast content of multiple channels when desired, and to easily select the broadcast they want to watch, without having to make troublesome channel changes. In addition, once the video signal is stored in the buffer memory, the stored contents are sequentially transferred to the display memory by the CPU and displayed on the CRT, so the image on the CR1 screen is continuously updated and a smooth image is obtained, making it visually appealing. Excellent effectiveness.

Further, by operating the operating section, the image of any one channel can be displayed as a still image on the entire CRT screen, so that changing images can be stopped and checked accurately and easily.

In addition, since a single tuner for normal reception is used as is, the same number of channels as for normal reception can be received and displayed simultaneously without the need to set new reception channels for multi-mode. can,
Easy to use with no need to repeat sets, and easy to configure.
It can be implemented in existing television receivers.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a block diagram of its buffer memory control section, Fig. 3 is a time chart F showing storage operation in multi mode, and Fig. 4 is a display memory control section. 5 is a block diagram of the CRT screen in multi mode, FIG. 6 is a time chart showing memory operation in still mode, and FIG. 7 is a block diagram of CRT screen in still mode.
It is a block diagram of an RT screen.

Claims (4)

[Claims] (1) A single tuner switches channels at regular intervals and stores the video signals of each channel, and sequentially reads out the stored video signals to display images of multiple channels on one screen, or to display images of multiple channels on one screen. A television receiver that displays a still image of any one channel, comprising: a channel selection unit that switches the receiving channel of the tuner; and a buffer memory that stores one image of the video signal of the selected channel. a display memory that stores one image of each video signal of one or more selected channels; a buffer memory control unit that controls writing to the buffer memory based on a synchronization signal in received radio waves; and a clock. A display memory control unit that generates a television synchronization signal based on pulses and controls reading and writing to the display memory in synchronization with the television synchronization signal, and a display memory control unit that is provided at a stage before a video output unit and a deflection output unit to the CRT. a video signal switching section and a synchronizing signal switching section that switch the inputs to the two sections to the display memory side respectively; a central control section that controls each section; and an operation section that is operated to select the display mode of the CRT. When displaying images of multiple channels on one screen, the central control unit stores the video signal for one image in the buffer memory during the display scanning period of the synchronization signal of the channel, and then displays the video signal of the television. The contents of the buffer memory are transferred to the display memory during the vertical retrace period of the television synchronization signal.L The stored contents are read out during the display scanning period of the television synchronization signal.
RT, and when displaying a still image of any one channel on one screen, one image of the video signal is sent to the synchronizing signal of the received radio wave during the display scanning period of the synchronizing signal of that channel. A television receiver characterized in that the stored contents are directly stored in a display memory, and the stored contents are read out and sent to a CRT during a display scanning period of a television synchronization signal. (2) The television receiver according to claim 1, wherein when displaying a plurality of channels on one screen, the amount of video signals stored in the buffer memory is for one field. (3) The television receiver according to claim 1, wherein when displaying one channel of still images on one screen, the amount of video signals stored in the display memory is one frame. (4) The television receiver according to claim 1, wherein the number of images of different channels displayed on one screen is nine.