JPH0680485B2 - Operation control system for voltage fluctuation countermeasure equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention is used in a substation or the like for the purpose of suppressing system voltage fluctuations, and a shunt reactor facility (hereinafter abbreviated as ShR) and a phase advance capacitor facility (hereinafter SC). Abbreviated) and a reactive power compensator (hereinafter abbreviated as SVC) in which a thyristor and a reactor are connected (hereinafter abbreviated as SVC).

[Prior Art] In substations, etc., measures are taken to suppress system voltage fluctuations by combining ShR, SC, and SVC.

The system voltage can be lowered by inputting ShR to the system, and the system voltage can be increased by inputting SC.
By the operation of, the fluctuation of the system voltage can be suppressed within a predetermined voltage fluctuation range.

The following methods have been used for the operation of the above-mentioned equipment.

(1) The time sequence circuit individually opens and closes ShR and SC based on the situation of the load fluctuation in the system in advance.

(2) When the SC detects the energizing current in the SVC and the maximum capacity of the SVC is 1.0 PU (par unit), for example,
If 0.1PU (10%) or 0.9PU (90%) continues for a certain period of time, the method of sequentially opening and closing the SC will be adopted.

(3) ShR compares the reference value of the grid voltage, below a certain value,
Or open and close when above.

[Problems to be Solved] (1) The time sequence method cannot cope with a sudden change in system conditions. (It is not possible to control with high accuracy even in a fixed condition.) (2) When the switching of SVC is judged only by the SVC current, the power receiving system voltage rises, and even if the maximum capacity of SVC is controlled, if the system voltage is above the set value, SC Will be turned on, and the voltage will rise.

(3) If only the system voltage is used to open and close ShR, under the control assumption of SVC where the power receiving system voltage slowly drops (the set voltage is set in the final control), ShR is turned on unless proper timing is adjusted, and hunting is performed. Cause

[Configuration of the Invention] The present invention has been made for the purpose of solving the above-mentioned problems, and in order to prevent erroneous control in conventional ShR and SC switching, ShR and SC switching is performed under conditions of system bus voltage and SVC current. Thus, the opening / closing control of each is performed to smoothly control the operation of the equipment.

The present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. It is assumed that the power source 1 is connected through the impedance 2 and the bus 3 has the load 4.

ShR equipment 20, SC equipment 3 against voltage fluctuations caused by this load 4
0 and SVC main circuit 10 are installed side by side.

The ShR facility 20 is equipped with a plurality of switches 21 and a plurality of diversion reactors 22. The SC equipment 30 is provided with a plurality of switches 31 and SC32. The SVC main circuit 10 is composed of a high impedance transformer 11 and an antiparallel connection thyristor 12 in series.

For these ShR equipment 20, SC equipment 30 and SVC main circuit 10,
By ShR opening / closing control circuit a, SC opening / closing control circuit b, and voltage adjustment control (hereinafter referred to as AVR) circuit 7, which are surrounded by chain lines,
A control signal is formed.

First, the AVR circuit 7 will be described. A voltage detector 71 is connected to the secondary side of PT5 connected to the system bus 3. The system bus voltage signal is subtracted by a bus reference voltage signal 72 and an adder 73, integrated by a controller 74, and a function circuit 75
Is input to the pulse generation circuit 8 with blockson. In addition, the power supply synchronization detection circuit 6 is the pulse generation circuit 8
The output from the pulse generating circuit 8 is input to the gates G ₁ and G ₂ of the thyristor 12.

The ShR switching circuit a will be described with reference to FIG. 2 showing in detail.

With the voltage signal obtained by subtracting the bus reference voltage signal 72 as the input,
Input to the upper / lower limit detector 24 via the coefficient unit 23. In this detector 24, plus. When the voltage signal from the coefficient unit 23 reaches the level of the upper limit 5% or the lower limit 5%, the signal Vu or V _L is output and the AND circuit (the (See FIG. 3) At the same time as outputting to 352 and 351, the upper and lower limit output sides from the detector 24 are connected to AND circuits 251 and 252, respectively. There is an output signal iu or i _L from the lower limit detection circuit 34, and Vu or V _L from the detector 24 described above.
Is output, the AND circuit 251 or 252 is turned on.

AND circuit 251 on the upper limit side, AND circuit 252 on the lower limit side
The output side of each sh
It is connected to the R drive circuit 27, and when there is a signal on the upper limit side, it issues a signal to input ShR and closes the switch 21, and when there is a signal on the lower limit side, it issues a signal to open ShR and opens the switch 21. open.

The SC opening / closing control circuit b will be described in detail with reference to FIG.

The SVC current detection circuit 33 is connected to form a conduction current signal for the SVC by inputting the current from the CT that detects the conduction current of the SVC main circuit 10, and this current detection circuit 33 is the above. It is connected to the lower limit detector 34. The detector 34 has an upper limit of 0.9 and a lower limit of 0.1 when the maximum current carrying capacity of the SVC is 1.0. When the energizing current signal reaches the upper limit, the signal iu is emitted, and when the lower limit is reached, the signal i _L is emitted.
Up. The upper limit and lower limit of the lower limit detector 34 are AND circuits 35
1 and 352 connected to the AND circuits 351 and 352, respectively, on the ShR switching control circuit a in FIG. When the lower limit output V _L and the upper limit output V _U of the lower limit detector 24 are input and i _U and V _L are present at the same time, the upper limit AND circuit 351 is turned on, and
_The lower limit side AND circuit 352 is turned on when _L and V _U are present at the same time.

The output sides of the AND circuits 351 and 352 are respectively connected to the SC drive circuit 37 via the timer 36, and when there is a signal on the upper limit side, after a certain period of time a signal for SC input is issued to close the switch 31 and to the lower limit side. When there is a signal, an SC open signal is issued to open the switch 30.

In FIG. 1, the signal converted into the thyristor firing control angle by the function circuit 75 of the AVR circuit 7 is input to the block zone pulse generating circuit 8 and is output with the firing phase control angle being limited. Figure 4 shows the block zone and the range in which gate pulses can be generated.

At the time of load, when controlling the fluctuation of system voltage Ve by SVC, energization control for high impedance transformer 11 or reactor is performed as is well known, and SVC energizing current is increased for increase in system bus voltage Ve, The voltage drop is dealt with by reducing the current flow. In this case, the controllable range is between the phase a = 90 °, which is the maximum peak value of the system bus voltage, and 180 °. The maximum current flow is at 90 ° and it is zero at 180 °. In the present invention, the energization control can be performed at the phase position while the maximum value of the energization current is, for example, 90% to 10%.
If the pulse phase position corresponding to the above current flows,
When the pulse phase position corresponds to a current of 0% and a current of 10% or less, no current is applied to the SVC.

[Operation] In the device of the present invention, basically, the opening / closing of the SC is controlled by detecting the presence (for example, 90% or more) and the absence (for example, 10% or less) of the SVC current and controlling the opening and closing.

Normally, when the SVC current flows, the system bus voltage Ve drops, but when the sending power receiving voltage is higher than the set value, the SC is not turned on and the AND condition is set.

Further, the switching of ShR is detected and controlled if the system bus voltage Ve is equal to or higher than or equal to a set value.

If the system voltage Ve drops slowly, the SVC also responds slowly, so if ShR is turned on while the SV is performing cutoff control, hunting will occur at this time, so the SVC current will be detected. , If more than 90% flow, ShR
In addition, the condition that can be input is that under 10%, ShR is opened and each condition is set as AND condition.

Here, the opening and closing conditions of the SC are summarized as follows.

(Main) SVC current 90% or more + (Slave) System voltage setting or less → Input (Main) SVC current 10% or less + (Slave) System voltage setting or more → Open In addition, ShR switching and conditions are summarized as follows.

(Main) System voltage setting or more + (Slave) SVC current 90% or more → input (Main) System voltage setting or less + (Slave) SVC current 10% or less → Open In the above examples, SVC current is 90% or more , Or 10% or less, the SVC phase control angle β is proportional to the SVC current in the sawtooth wave control signal shown in FIG.
It is also possible to detect the SVC phase control angle β that controls the generation of the C current from the function circuit 75, detect that this is in the upper limit or the upper limit block zone, and set it as the AND condition.

The thyristor gate pulses G ₁ and G ₂ are compared with the upper and lower limits of the block zone, and they become the same, and when clinging (U _L ) signal or lower limit (L _L ) signal is output.

[Effects of the Invention] Since the present invention opens and closes SC and ShR by setting the grid voltage, SVC current, or phase control angle as the AND condition, not only the proper grid voltage stabilization is achieved, but also unnecessary switch operation. The reliability of the device can be increased.

[Brief description of drawings]

FIG. 1 shows a block diagram of an embodiment of the present invention. FIG. 2 is a block diagram showing the ShR switching control circuit of FIG. FIG. 3 is a block diagram showing the SC switching control circuit of FIG. FIG. 4 is a time chart of the pulse generating circuit with block zone shown in FIG. 6 ... Power supply synchronization detection circuit, 7 ... AVR control circuit, 8 ...
Pulse generator with block zone, 10 …… SVC main circuit, 2
0 …… ShR equipment, 23 …… Coefficient unit, 24 …… Up. Lower limit detector,
25,251,252 …… And circuit, 26,36 …… Timer, 27,37
…… Switch drive circuit, 30 …… SC equipment, 33 …… SVC current detection circuit, 34 …… Top. Lower limit detector.

Claims (1)

[Claims] 1. A voltage fluctuation countermeasure facility comprising a shunt reactor facility, a phase-advancing capacitor facility, and a reactive power compensator in which a reactor is connected in series with an antiparallel connection thyristor, wherein a system voltage and a current of the reactive power compensator or The phase control angle for controlling the generation of the current is detected, and the system voltage is the upper limit or the lower limit of the set value of the set system voltage, and the current of the reactive power compensator is set in the compensator. Operation of voltage fluctuation countermeasure equipment characterized by turning on and off the shunt reactor equipment and phase-advancing capacitor equipment under the following AND conditions, provided that the applied current value is 90% or more or 10% or less. control method. a: Reactive power compensator current 90% or more (+) system voltage set value or less → Advancing phase condenser equipment b: Reactive power compensator current 10% or less (+) system voltage setting value or more → Phase advancing capacitor equipment release c: System voltage Equipment set value or more (+) Reactive power compensator current
90% or more → Shunt reactor equipment input d: System voltage set value or less (+) Reactive power compensator current 10%
Below → Open shunt reactor equipment