JPH0637259A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] [Object] It is an object of the present invention to provide a technique for reducing a chip layout area of a semiconductor integrated circuit and reducing noise caused by an operation of a data output circuit. [Structure] The power supply wiring dedicated to the signal output system and the power supply wiring dedicated to the internal circuit, which have the same polarity,
By connecting to the common external terminals 31 and 32 and short-circuiting power supply wirings having the same polarity, the electrostatic breakdown voltage is improved and the number of electrostatic protection circuits is reduced. Even when the power supply wires having the same polarity are short-circuited in this way, the data output circuit and the internal circuit can be supplied with power through the dedicated external terminals for power supply, respectively. , 7B, 8A, 8B to reduce the noise caused by the operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a technique for improving a power supply system in the semiconductor integrated circuit.
The present invention relates to a technique effectively applied to AM (Video Random Access Memory).

[0002]

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit having multiple power supply terminals, a power supply terminal or a power supply main line may be separated for each purpose of use of the power supply.

For example, in a semiconductor integrated circuit which inputs and outputs multi-bit data at the same time, the switching noise of the data output circuit does not affect the operation of other internal circuits due to the switching noise of the data output circuit, and the operation of other internal circuits is not affected. The power supply system is separated from the internal circuits other than the output circuit. When the power supply system is separated in this way, the input level Vih / Vil (high level input potential / low level input potential) is completely separated from the power supply wiring for the data output circuit, which has a relatively large amount of noise. Therefore, at least there is no inconvenience regarding power supply noise, but if the power supply wiring is separated in this way, the load of the power supply for the data output circuit becomes relatively light, and the electrostatic breakdown withstand voltage of the data output circuit becomes Will fall. As a countermeasure,
Conventionally, an electrostatic protection circuit is provided between power supply lines to prevent element destruction by allowing a surge current to escape. A bidirectional surge absorption circuit called lateral bipolar or the like is applied to this electrostatic protection circuit. In this surge absorbing circuit, for example, the power source is the high-potential-side power source Vdd1,
Considering the case where there are two systems, such as the low-potential-side power supply Vss1, the high-potential-side power supply Vdd2, and the low-potential-side power supply Vss2, between Vdd1-Vss1 and Vdd2-Vss2.
, Vdd1 to Vss2, and Vdd2 to Vss1. Therefore, at least four are required.

An example of a document describing electrostatic breakdown of a semiconductor integrated circuit is "LSI Handbook (page 679)" issued by Ohmsha Co., Ltd. on November 30, 1984.

[0005]

However, in the conventional method in which a large number of surge absorbing circuits are provided as described above, the reduction of the chip layout area (chip size) of the semiconductor integrated circuit is hindered accordingly. On the other hand, if the power supply system is not separated, the number of surge absorbing circuits may be small, but the power supply noise of the data output system will hinder stable operation of the input first stage circuit.

An object of the present invention is to provide a technique for reducing the chip layout area of a semiconductor integrated circuit and reducing the noise caused by the operation of the data output circuit.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, the power supply wiring dedicated to the signal output system,
This is to short-circuit power supply wires having the same polarity as the power supply wires dedicated to the internal circuit. At this time, the power supply wirings having the same polarity and the common terminal can be coupled by a bonding wire.

[0010]

According to the above-mentioned means, it is seen from the external terminal for power supply that the power supply wiring dedicated to the signal output system and the power supply wiring dedicated to the internal circuit are short-circuited with each other. In addition, this is equivalent to the case where the internal power supply wiring is one system, which achieves a reduction in the number of surge absorption circuits. Further, as described above, even if the power supply wiring dedicated to the signal output system and the power supply wiring having the same polarity in the power supply wiring dedicated to the internal circuit are coupled to the common terminal, the data output circuit and the internal circuit, Power can be supplied through the dedicated power supply terminals, respectively, which achieves reduction of noise caused by the operation of the data output circuit.

[0011]

FIG. 1 shows a VRAM which is an embodiment of the present invention.

Although not particularly limited, the VRAM shown in FIG. 1 is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

In FIG. 1, 7A and 7B are first data output circuits, and 8A and 8B are second data output circuits. This data output circuit is not particularly limited, but may be an n-channel type MOS transistor and a p-channel type MOS transistor.
Including an inverter formed by connecting a transistor in series,
The logical output of this inverter can be externally output through an external terminal (not shown) for data output. VRAM
Is a random accessible RA, as will be described in detail later.
An M unit and a serially accessible SAM unit are included. In that case, the first data output circuits 7A and 7B are provided.
Is a parallel data output system of the RAM section, and the second data output systems 8A and 8B are serial data output systems of the SAM section.

The low-potential-side power supply terminals of the first data output circuits 7A and 7B are coupled to the power-supply wiring 3, and the low-potential-side power supply terminals of the second data output circuits 8A and 8B are connected to the power-supply wiring 4. Be combined. The power supply wiring 3 and the power supply wiring 4 are V
In the inside of the RAM, in order to reduce the fluctuation of the low-potential-side power supply Vss, separate wiring is used. The ends of the power supply wiring 3 and the power supply wiring 4 are bonded to the bonding pads 16 and 1, respectively.
7, 18 and 19, and this pad is bonded to the external terminals 30 and 33 for supplying power. As a result, the power supply wiring 3 and the power supply wiring 4 are short-circuited in a direct current manner at the external terminals 30 and 33. The power wiring is not particularly limited, but is aluminum wiring.

Further, the first data output circuits 7A, 7
The high potential side power supply terminal of B is coupled to the power supply wiring 2, and the high potential side power supply terminals of the second data output circuits 8A and 8B are coupled to the power supply wiring 1. Power wiring 1 and power wiring 2
In the inside of the VRAM, the wirings are separated from each other in order to reduce the fluctuation of the low potential side power supply Vdd. The ends of the power supply wiring 1 and the power supply wiring 2 have bonding pads 15, 1
4 and this pad is connected to the external terminal 32 for power supply.
Is bonded to. As a result, the power supply wiring 1 and the power supply wiring 2 are short-circuited in a direct current manner at the external terminal 32.

Here, the external terminal 30 is a low potential side power source Vss1 terminal, and the external terminal 32 is a high potential side power source Vd.
d2 terminal, and the external terminal 33 is the low-potential-side power supply Vss3
It is used as a terminal.

In the data output circuits 7A, 7B, 8A, 8B, a relatively large switching current flows, and the switching current causes a Vi of the input system of the internal circuits 9A, 9B.
Power supply wirings 5 and 6 different from the power supply wirings of the data output circuits 7A, 7B, 8A and 8B are provided only for internal circuits so that h / Vil is not affected. Internal circuit 9
The high-potential-side power supply terminals A and 9B are coupled to the power supply wiring 5. This power supply wiring 5 is connected to a bonding pad 21, and this pad is connected to an external terminal 34 for supplying power by a bonding wire BW. The external terminal 34 serves as a high-potential-side power supply Vdd1 terminal. Similarly, the power supply wiring 6 is coupled to the bonding pad 20, and this pad is coupled to the external terminal 35 for power supply. The external terminal 35 serves as a low-potential-side power supply Vss2 terminal.

Here, according to the prior art, if the power supply wiring is separated according to the purpose of use, the load of the power supply for the data output circuit will be lightened as a result, and the electrostatic breakdown voltage of the data output circuit will tend to decrease. In order to prevent this, a large number of surge absorbing circuits were required to prevent element destruction by allowing surge current to escape. If the power supply wiring is not separated for the data output circuit and the internal circuit, that is, if power is supplied to both the data output circuit and the internal circuit by one system of power supply wiring, Since the total area of the diffusion layer of the MOS transistor as viewed from the external terminal becomes large, the electrostatic breakdown voltage becomes higher than that in the case where the power supply wiring is separated as described above. However, in that case, since power is supplied to both the data output circuit and the internal circuit by the power supply wiring of one system, a relatively large switching current in the data output circuit causes the input system of the internal circuit to operate. Vih / Vil may be affected.

Therefore, in this embodiment, by connecting the power supply wirings dedicated to the signal output system and the power supply wirings dedicated to the internal circuit, which have the same polarity, to the common external terminals 31 and 32, that is, , These external terminals 31, 32
By short-circuiting the power supply wirings having the same polarity by utilizing the above, the electrostatic breakdown withstand voltage is improved while maintaining the noise resistance of the internal circuits 9A and 9B. That is, the power supply wirings 1, 2 and 5 are connected to the bonding pads 15 and 1, respectively.
4, 13 and the bonding pads 15, 1
External terminals 3 and 4 are formed by bonding wires BW.
2, the power supply wirings 3, 4, 6 are respectively coupled to the bonding pads 12, 10, 11 and the bonding pads 12, 10, 11 are coupled to the external terminals 31 by the bonding wires BW. Since the power supply wiring dedicated to the signal output circuit and the power supply wiring dedicated to the internal circuit are short-circuited with each other, the total area of the diffusion layer of the MOS transistor viewed from the external power supply terminal side is increased, and By adding the bonding wire WB and the inductance component and capacitance component of the power supply wiring thereto, the load of the power supply is increased, and as a result, the electrostatic breakdown voltage is improved. If the electrostatic breakdown withstand voltage is improved in this way, the number of surge absorption circuits to prevent element destruction by allowing surge current to escape is
The number can be reduced as compared with the conventional circuit in which the power supply wiring is simply separated. In other words, in the case of the conventional circuit in which the power supply wiring is simply separated, since the power supply load on the data output system side is light, it is necessary to arrange a large number of surge absorption circuits to improve the electrostatic breakdown voltage. In the present embodiment, as described above, by connecting the power supply wirings having the same polarity to the common external terminals 31 and 32, the external power supply terminals are equivalent to the case of one system of power supply wirings. Therefore, it is possible to reduce the number of surge absorbing circuits, and thereby reduce the chip layout area.

FIG. 2 shows a detailed configuration example of the internal circuits 9A and 9B.

As shown in FIG. 2, internal circuits 9A and 9B are provided.
In the block corresponding to, the RAM section 110 that enables random access and the S section that enables serial access.
It includes an AM unit 120 and a control unit 130 that controls the operation of the entire VRAM.

The RAM section 110 includes, but is not limited to, a memory cell array 111 in which a plurality of dynamic memory cells are arranged in a matrix. The addressing of the memory cells includes the operation of driving a predetermined one word line to a selection level based on the output of the X (row) address decoder 113 and the pair of complementary data based on the output of the Y (column) address decoder 112. The operation is performed based on the operation of the switch circuit that selectively connects the lines to the complementary common data line.

The SAM unit 120 is not particularly limited, but two systems of data registers (DR0, DR1) 121, 1 coupled to the data input / output system of the RAM unit 110.
22, a selector 125 arranged on the serial output side thereof, a shift register 123 for performing address control of the data registers 121 and 122, and a serial clock SC input from the outside to the shift register 123. And a clock buffer 124 for.

Each time a serial clock is input, the pointer pointed to by shift register 123 is shifted, thereby enabling addressing of data registers 121, 122. The data read by this addressing can be selectively output to the outside by the selector 125. Specifically, when the output of one data register 121 is selected, the output of the other data register is selected by the selector 125 after all the data held in that register is read as serial data, and this time. The data held in the register 122 is read out as serial data, and the output of the data register 121 is selected again by the selector 125 after all the held data in the register 122 are read out.
Serial data is alternately read from 1,122 in word units. Such switching control of the selector 125 is
This is enabled by the output of the comparison circuit 139. Further, the shift register 123 has a preset function, and the initial address of the data register 121 or 122 can be set. The RAM 111 and the data register 12
A gate circuit 126 whose operation is controlled by the control unit 130 is arranged between the gate circuit 1 and the circuit 122.
26 from the RAM 111 to the data register 121,
It is possible to selectively transfer data to the 122 in word units.

According to the above embodiment, the following operational effects can be obtained.

(1) By connecting the power supply wiring dedicated to the signal output system and the power supply wiring dedicated to the internal circuit, which have the same polarity, to the common external terminals 31 and 32, that is, the power supply wiring 1 , 2, 5 are coupled to the bonding pads 15, 14, 13 respectively, the bonding pads 15, 14, 13 are coupled to the external terminal 32, and the power supply wirings 3, 4, 6 are bonded to the bonding pads 12, 10, respectively. 11 and the bonding pads 12, 10 and 11 are coupled to the external terminal 31, so that the power supply wiring dedicated to the signal output system and the power supply wiring dedicated to the internal circuit have the same polarity.
Since the power supply wirings having the same polarity are short-circuited by being coupled to a common external terminal, the total area of the diffusion layer of the MOS transistor viewed from the external power supply terminal side is increased, resulting in electrostatic breakdown voltage Is improved. By improving the electrostatic breakdown voltage as described above, the number of surge absorbing circuits can be reduced as compared with the case of the conventional circuit in which the power supply wiring is simply separated. For example, as described above, in the prior art, when the power source has two systems, four surge absorbing circuits are required, whereas according to the present embodiment, one surge system is seen from the external terminal for power supply. Since it is equivalent to the power supply wiring, it is sufficient to provide one surge absorbing circuit between the high potential side power source and the low potential side power source. By reducing the number of surge absorbing circuits in this way, the chip layout area can be reduced.

(2) Further, even when the power supply wiring dedicated to the signal output system and the power supply wiring dedicated to the internal circuit are short-circuited with each other as described above, the data output circuit and the internal circuit are connected to each other. Since the power can be supplied through the dedicated external terminals for power supply, the data output circuit 7
Noise caused by the operations of A, 7B, 8A, and 8B can be reduced.

(3) Power wiring dedicated to the signal output system,
The power supply wirings having the same polarity as the power supply wiring dedicated to the internal circuit are coupled to a common terminal by a bonding wire, and the inductance component and the capacitance component of the bonding wire WB are added to increase the load of the power supply. And (1) and (2) above
The effect of is remarkable.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, in the above embodiment, the bonding pad 10, 11, 12 is connected to the power supply external terminal 31, and the bonding pad 13, 14, 15 is connected to the power supply external terminal 32. , It is not always necessary to use the external terminal for power supply. For example, instead of this external terminal for power supply, a non-connection terminal (non-connection pin) or the like can be used. Besides the bonding wire, an appropriate conductive member having an appropriate inductance, capacitance, and resistance can be used. You may make it short-circuit between power supply wirings via such a conductive member.

In the above description, the invention made by the present inventor is the field of application which is the background of the invention.
Although the case of application to the M has been described, the present invention is not limited to this, and can be widely applied to various semiconductor integrated circuits such as a multi-port RAM, a single-port semiconductor memory device, or a data processing device.

The present invention can be applied on condition that at least a plurality of systems of power supply wirings are provided.

[0033]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the power supply wiring dedicated to the signal output system,
By short-circuiting the power supply wirings of the same polarity with the power supply wiring dedicated to the internal circuit, it becomes equivalent to the internal power supply wiring being one system when viewed from the external terminal for power supply,
As a result, the number of surge absorbing circuits can be reduced and the chip layout area can be reduced. Even if the power supply wiring dedicated to the signal output system and the power supply wiring dedicated to the internal circuit are short-circuited with each other as described above, the data output circuit and the internal circuit are each supplied with a dedicated power source. Since power can be supplied via the external terminal, noise due to the operation of the data output circuit can be reduced.

[Brief description of drawings]

FIG. 1 is an overall configuration block diagram of a VRAM according to an embodiment of the present invention.

FIG. 2 is a detailed configuration block diagram of a main part of the VRAM.

[Explanation of symbols]

 1 Power Supply Wiring 2 Power Supply Wiring 3 Power Supply Wiring 4 Power Supply Wiring 5 Power Supply Wiring 6 Power Supply Wiring 7A Data Output Circuit 7B Data Output Circuit 8A Data Output Circuit 8B Data Output Circuit 10 Bonding Pad 11 Bonding Pad 12 Bonding Pad 13 Bonding Pad 14 Bonding Pad 15 Bonding pad 16 Bonding pad 17 Bonding pad 18 Bonding pad 19 Bonding pad 20 Bonding pad 21 Bonding pad 30 External terminal 31 External terminal 32 External terminal 33 External terminal 34 External terminal 35 External terminal 110 RAM section 111 RAM 112 Y address decoder 113 X address Decoder 120 SAM unit 121 Data register DR0 122 Data register DR1 123 Shift Register 124 clock buffer 125 selector 130 control unit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masahiro Ogata 5-20-1 Kamimizumotocho, Kodaira-shi, Tokyo Hitate Cho El SII Engineering Co., Ltd.

Claims (4)

[Claims] 1. A semiconductor integrated circuit in which a data output circuit and an internal circuit other than the data output circuit are formed on one semiconductor substrate, and dedicated power supply wirings are formed for the signal output circuit and the internal circuit, respectively. In the semiconductor integrated circuit, the power supply wiring dedicated to the signal output system and the power supply wiring dedicated to the internal circuit are short-circuited with each other. 2. The semiconductor integrated circuit according to claim 1, wherein the power supply wiring dedicated to the signal output system and the power supply wiring dedicated to the internal circuit have the same polarity and are coupled to a common terminal by a bonding wire. circuit. 3. A dedicated external terminal for supplying power to the data output circuit from the outside, and a dedicated external terminal for supplying power to the internal circuit from the outside. Semiconductor integrated circuit. 4. The internal circuit includes a random access RAM unit and a serial access SAM unit, and the output circuit includes an output buffer that enables external output of parallel data, and a serial data output unit. 4. The semiconductor integrated circuit according to claim 1, further comprising an output buffer that enables external output.