JPH06311022A - Semiconductor logic circuit device - Google Patents

Abstract

PURPOSE:To quicken the delay time of the circuit, to reduce the occupied area due to decrease in number of elements and to relieve the load when viewing from a pre-stage circuit by providing at least one MOS transistor(TR) whose source connects to a 1st input signal terminal and whose gate connects to a 2nd input signal terminal in a 2-input semiconductor logic circuit. CONSTITUTION:TRs P11, N12 are turned on and a TR N11 is turned off when a 1st input signal terminal A is at an H level and a 2nd input signal terminal B is at an L level, and when a size of a TR N12 is sufficiently smaller than a size of the TR P11, an output signal terminal OUT provides an H level output. In this case, an H level is outputted in the selection state of A=H, B=L with respect to four combinations of the 2 input signals A, B and an L level is outputted in other cases. That is, the logic operation equal to that of a conventional NOR circuit is realized with a fewer element number.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor logic circuit device, and more particularly to a semiconductor logic circuit device using BiCMOS or CMOS technology.

[0002]

2. Description of the Related Art Conventional semiconductor logic circuit devices have, for example, circuit configurations as shown in FIGS.

FIG. 6 shows a CMOS structure, and FIG. 7 shows a BiCMO.
This is an example of a NOR circuit having an S configuration, and outputs high (hereinafter, H) level only when both of the two input signal terminals A and B are at low (hereinafter, L) level, and otherwise outputs L level. Output.

FIG. 8 shows a CMOS structure, and FIG. 9 shows a BiCMO.
This is an example of an S-configured NAND circuit, and outputs L level only when both of the two input signal terminals A and B are H level, and outputs H level otherwise.

As the latest prior art for the purpose of reducing the area, there is a semiconductor logic circuit device as shown in FIGS. 10 to 13 shown in Japanese Patent Laid-Open No. 2-27714.

FIG. 10 shows an XOR circuit, which outputs H level when the logical values of the two input signal terminals A and B are different from each other.
When they match, L level is output.

FIG. 11 shows an XNOR circuit, which outputs an L level when the logical values of the two input signal terminals A and B are different from each other, and outputs an H level when they match.

FIG. 12 shows an OR circuit which outputs the L level only when both of the two input signal terminals A and B are at the L level, and outputs the H level at other times.

FIG. 13 shows an AND circuit which outputs the H level only when both of the two input signal terminals A and B are at the H level, and outputs the L level at other times.

[0010]

According to the conventional technique as described above, the MOS transistor is used for the logical operation.
The input signals are both connected to the gate, and the P-type MOS transistor is shown in FIGS. 6 and 7, and the N-type MOS transistor is shown in FIGS.
Since each two transistors are connected in series, the delay time (t _PD ) of the logic circuit increases and the area also increases. Further, since the gate capacitance is large, there is a problem that the load of the circuit at the previous stage becomes large.

Further, among the above-mentioned problems, NOR and NAND circuits cannot be constructed with the latest prior art circuit configuration shown in "Japanese Patent Laid-Open No. 2-2771414" for the purpose of reducing the area. A structure in which an inverter circuit is connected before or after must be taken, and the effect of area reduction cannot be obtained. Moreover, as a fundamental problem, when B = L in FIGS. 10 and 12 and B = H in FIGS. 11 and 13, the output is not actually fixed in the floating state. There was a problem that the expected logical operation could not be performed.

[0012]

In a semiconductor logic circuit for generating a logic output signal from two input signals, a MOS having a source connected to a first input signal terminal and a gate connected to a second input signal terminal. Have at least one type transistor. Further, in the above means, the source portion of the MOS transistor connected to the first input signal terminal is commonly used as a mask pattern with the source portion of another MOS transistor to which the same signal is input.

[0013]

Embodiment 1 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In this embodiment, the source part is connected to the first signal input terminal A and the gate part is connected to the second signal input terminal B.
The drain portion is connected to the output signal terminal OUT, the P-type first MOS transistor P ₁₁ , the source portion is connected to the low-potential-side power supply terminal GND, and the gate portion is connected to the second signal input terminal B. And the drain is the output signal terminal OU
N-type second MOS transistor N connected to T
₁₁ , the source part is connected to the power supply terminal on the low potential side,
The gate is connected to the power supply terminal VCC on the high potential side,
The drain portion has an N-type third MOS transistor N ₁₂ connected to the output signal terminal OUT.

Next, the operation of this embodiment will be described.

When the first input signal terminal A is at L level, that is, on the low potential side, the transistor P ₁₁ is always off.
In this state, when the second input signal terminal B is at the H level, that is, on the high potential side, the transistor N ₁₁ is in the ON state,
The output signal terminal OUT becomes L level. Further, when the second input signal terminal B is at L level, both P ₁₁ and N ₁₁ are in the OFF state, but since the gate portion is at the high potential power supply terminal, the transistor N ₁₂ which is always in the ON state causes the output signal terminal OUT does not enter a floating state and outputs L level.

Next, when the first input signal terminal A is at the H level, when the second input signal terminal B is at the H level, the transistor P ₁₁ is OFF and N ₁₁ and N ₁₂ are ON, so that the output signal is output. The terminal OUT becomes L level. Second input signal terminal B
Is at L level, the transistors P ₁₁ and N ₁₂ are ON and N ₁₁
Is OFF, and at this time, if the size of the transistor N ₁₂ is sufficiently smaller than the size of the transistor P ₁₁ , that is, the resistance component in the ON state is sufficiently large, the output signal terminal OUT outputs the H level.

Therefore, in this embodiment, for four combinations of two input signals A and B, the H level is output only when A = H and B = L are selected, and otherwise the L level is output. The same logical operation as the NOR circuit shown in FIGS. 6 and 7 of outputting is performed.

At this time, as is clear from comparison between FIG. 1 and FIG. 6, the number of elements is smaller in this embodiment and the effect of area reduction can be obtained. Further, in this embodiment, the transistor P of FIG.
Since there is no series connection like ₆₁ and P ₆₂ , t _PD can be speeded up.

In fact, the transistors P ₆₁ , P of the circuit of FIG.
The size of ₆₂ is 30 μm, and the size of N ₆₁ and N ₆₂ is 15 μm
1 and the load capacitance is 0.1 pF, the circuit of FIG. 1 has a transistor P ₁₁ size of 20 μm, N ₁₁ size of 10 μm, N ₁₂ size of 2 μm and t _PD of 0.25.
20% improvement from ns to 0.2 ns. Further, as can be seen from this numerical example, not only the number of elements is small in order to obtain the performance higher than that of the conventional circuit, but also the element size itself is small, and the effect of further area reduction can be obtained.

Further, although the diffusion capacitance is larger in the gate capacitance and the diffusion capacitance of the source / drain portion of the conventional MOS transistor, the gate capacitance is increased and the diffusion layer is increased by thinning the gate oxide film by the recent miniaturization technique. The gate capacitance and the diffusion capacitance are becoming almost equal due to the reduction of the bottom and side capacitances due to the reduction of the area and thinning in the depth direction. Therefore, there is no problem in using the circuit of the present embodiment in place of the conventional example, and the circuit of the present embodiment has the input signal terminal A commonly connected to a plurality of circuits as shown in FIG. In this case, by making the source part common to the mask data as shown in FIG. 3, it is possible to reduce the load seen from the circuit in the previous stage (the circuit which generates the input signal A) by half.

FIG. 4 shows the NAND circuit (BiCM) of this embodiment.
This is an example of the OS configuration). In this case, the output signal terminal OUT is at the L level only when the input signal terminal A is at the H level and the input signal terminal B is at the L level, and the H level is output otherwise, the NAND circuit shown in FIGS. Performs circuit operation equivalent to.

[0023]

Second Embodiment FIG. 5 is a circuit diagram showing a second embodiment of the present invention.

In the first embodiment shown in FIG. 1, the input signal terminal A is
Is H level and B is L level, transistors P ₁₁ and N ₁₂
Are both turned on, a current flows from the input signal terminal A to the low-potential-side power supply terminal, which may lead to an increase in power if the number of circuits is large. Further, the H level of the output signal terminal OUT drops to some extent due to the current, the wiring resistance of the input signal A itself, and the resistance component of the transistor P _{11 in} the ON state.

The second embodiment was invented to solve such a problem. In FIG. 1, the gate portion of the transistor N ₁₂ connected to the power supply terminal on the high potential side is supplied to the CMOS inverter of the input signal A. The circuit is connected to the signal inverted by the circuit INV1.

As a result, the transistor N ₁₂ is turned on only when the input signal A is at L level, and the current becomes zero. Actually, the area is increased by INV1 as compared with the first embodiment, but this inverter may have a small size, and also when the input signal A is commonly connected to a plurality of circuits as shown in FIG. Since only one inverter is required, this increase in area is not a problem.

[0027]

As described above, according to the present invention, in a 2-input semiconductor logic circuit device, one of the input signals is MOS.
By connecting to the source portion of the transistor, it is possible to obtain the effect of shortening the delay time of the logic circuit and reducing the occupied area by reducing the number of elements. Further, by devising the mask data, it is possible to obtain the effect of reducing the load seen from the circuit in the previous stage to half that of the conventional one.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention,

FIG. 2 is a circuit diagram showing a usage example of the first embodiment of the present invention,

3 is a diagram showing a mask pattern of the circuit diagram of FIG. 2;

FIG. 4 is a circuit diagram showing an application example of the first embodiment of the present invention,

FIG. 5 is a circuit diagram showing a second embodiment of the present invention,

FIG. 6 is a circuit diagram showing a conventional example,

FIG. 7 is a circuit diagram showing a conventional example,

FIG. 8 is a circuit diagram showing a conventional example,

FIG. 9 is a circuit diagram showing a conventional example,

FIG. 10 is a circuit diagram showing a conventional example,

FIG. 11 is a circuit diagram showing a conventional example,

FIG. 12 is a circuit diagram showing a conventional example,

FIG. 13 is a circuit diagram showing a conventional example.

[Description of reference signs] A, B, B1, B2 input signal terminals OUT, OUT1, OUT2 output signal terminals P ₁₁ , P ₆₁ , P ₆₂ P-type MOS transistors N ₁₁ , N ₁₂ , N ₆₁ , N ₆₂ N-type MOS transistors INV1 inverter circuit

Claims (4)

[Claims] 1. A semiconductor logic circuit for generating a logic output signal from two input signals, comprising at least a MOS type transistor having a source connected to a first input signal terminal and a gate connected to a second input signal terminal. A semiconductor logic circuit device having one. 2. The semiconductor logic circuit device according to claim 1, wherein the source portion of the MOS transistor to which the first input signal terminal is connected is connected to another MO to which the same signal is input.
A semiconductor logic circuit device characterized in that the source portion of an S-type transistor and a mask pattern are commonly used. 3. The semiconductor logic circuit device according to claim 1, wherein when the MOS transistor is turned off by the combination of the logics of the first input signal and the second input signal, the output signal is determined. , A semiconductor logic circuit device having a normally-on second MOS transistor between the output terminal and the power supply. 4. A semiconductor logic circuit device, wherein a reverse phase signal of the first input signal is input to the gate portion of the second MOS transistor described in claim 3.