JPH06302828A - Nonvolatile semiconductor memory device - Google Patents

Abstract

(57) [Summary] [Purpose] Perform high-speed erase operation at low voltage in flash EEPROM. A semiconductor substrate 1 of the first conductivity type, a floating gate electrode 4 with a gate insulating film 3 interposed on a channel region on the surface of the semiconductor substrate 1, and an interelectrode insulating film 5 on the floating gate electrode 4. The floating gate electrode 4 is provided with a control gate electrode 6 interposed therebetween, and the floating gate electrode 4 is provided with a structure using a semiconductor material having a band gap larger than that of the semiconductor forming the substrate. With the above-described structure, the floating gate electrode 4 is made of a material having a bandgap larger than that of silicon, so that an FN tunnel current can be easily generated at a low voltage during erasing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor nonvolatile memory device.

[0002]

2. Description of the Related Art Conventionally, EP has been used as a semiconductor nonvolatile memory device.
ROM and EEPROM are widely known. Among them, in recent years,
A flash type EEPROM, which can electrically erase stored information in a batch or block unit of all memory cells, is attracting attention because it is advantageous for miniaturization and high integration of memory cells. An example of the conventional flash EEPROM described above will be described below with reference to the drawings.

FIG. 3 is a structural sectional view of a conventional flash type EEPROM. In FIG. 3, 1 is a p-type silicon substrate, 2 is an element isolation region, 3 is a channel region, 4 is a gate insulating film, 5 is a floating gate electrode, 6 is an interelectrode insulating film, and 7 is a control gate electrode (word line). , 8 is an n + source diffusion layer, 9 is an n + drain diffusion layer, 10 is an interlayer insulating film,
Reference numeral 11 is a bit line.

Flash type EEPR configured as described above
The operation of the OM will be described below. When the word line 7 and the bit line 11 are set to a high potential to operate the memory cell, a large amount of hot electrons are generated in the vicinity of the junction between the n + type drain diffusion layer 9 and the channel region 3 of the memory transistor. It is injected into the floating gate electrode 5 formed of silicon. At this time, the floating gate electrode 5
As shown in the energy band diagram of FIG. 4, the electrons accumulated in the cell have higher energy levels than those of the control gate 7, the n + source diffusion layer 8 and the n + drain diffusion layer 9, but the surrounding area is perfect. Since it is surrounded by an insulator, it does not escape even when the power is turned off. Since the threshold voltage of the memory transistor rises when electrons are accumulated in the floating gate electrode 5, even if the word line 7 is set to a specific potential and the same bias is applied to the memory transistor, Depending on the presence or absence of the accumulated charge of the memory transistor, a large difference occurs in the operating current value flowing between the source and drain of the memory transistor. In this way, the stored information can be written by injecting the charges into the floating gate electrode 5, and the stored information can be read out by the difference in the operating current value of the memory transistor. To erase the stored information, a positive bias is applied to the n + type source diffusion layer 8 or the p type semiconductor substrate 1, or a negative bias is applied to the floating gate electrode 5 due to the coupling capacitance with the control gate electrode 7. Done. FIG. 2B shows an energy band diagram during erasing. Here, a potential difference of ΔVb is generated between the floating gate electrode 5 and the n + type source diffusion layer 8, so that the electrons accumulated by the FN tunnel current are extracted to the n + type source diffusion layer 8 and erased. .

[0005]

However, in the above structure, the floating gate electrode 5 is formed of polysilicon, and the electrons accumulated by the FN tunnel current are extracted in erasing the stored information. 5 requires a high electric field between the n + type source diffusion layer 8 or the p-type semiconductor substrate 1 and a high positive bias is applied to the n + type source diffusion layer 8 or the p-type semiconductor substrate 1, or a control gate It is necessary to apply a high negative bias to the electrode 7. Therefore, another high voltage power source or a high voltage generating circuit is required, and there is a problem that the reliability of the gate insulating film 4 is deteriorated. There is also a problem that it takes time to extract the electrons.

Therefore, in view of the above problems, the present invention provides a semiconductor nonvolatile memory device which erases stored information at a high speed with a low voltage.

[0007]

In order to solve the above problems, a semiconductor nonvolatile memory device according to the present invention comprises a semiconductor substrate of a first conductivity type and a first insulating layer on a channel region on the surface of the semiconductor substrate. A floating gate electrode having a film interposed therebetween, and a control gate electrode having a second insulating film interposed between the floating gate electrode and the floating gate electrode, and the floating gate electrode is made of a semiconductor material having a band gap larger than that of a semiconductor forming the substrate. It has the configuration used. In addition, the floating gate electrode,
A conductor having a work function smaller than that of the semiconductor forming the substrate may be used.

[0008]

According to the present invention, since the floating gate electrode is made of a semiconductor material having a bandgap larger than that of the semiconductor forming the substrate, the electric charge in the floating gate written is different from that of the conventional example. It exists at a higher energy level. Therefore, the potential barrier between the gate insulating film and the floating gate electrode is reduced, and when the floating gate has a high potential with respect to the substrate or the source diffusion layer during erase, the accumulated charge in the floating gate is almost equal to the above. As the potential barrier between the gate insulating film and the floating gate becomes small, the FN tunnel current is generated by tunneling from the conduction band of the floating gate electrode to the conduction band of the gate insulating film at a low voltage.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Semiconductor non-volatile memory devices according to embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor nonvolatile memory device according to an embodiment of the present invention. In FIG. 1, 1 is a p-type silicon substrate, 2 is an element isolation region, 3 is a channel region, 4 is a gate insulating film, 5 is a floating gate electrode, 6 is an interelectrode insulating film, and 7 is a control gate electrode (word line). , 8 is n +
A source diffusion layer, 9 is an n + drain diffusion layer, 10 is an interlayer insulating film, and 11 is a bit line. Floating gate electrode 5
Is formed of a semiconductor material, such as gallium phosphide (Eg = 2.24eV), whose bandgap Eg is larger than that of silicon (Eg = 1.12eV) which is the substrate material. The gate insulating film 4 is formed of a silicon oxide film and has a thickness of 10 nm.

The operation of the semiconductor nonvolatile memory device configured as described above is performed by using hot electrons for writing the stored information and by using the FN tunnel current for erasing, as in the conventional example.

A detailed description will be given with reference to FIG. Figure 2 (a)
2B and 2B show energy bands at the time of erasing in the memory cell having the configuration shown in this embodiment and the configuration shown in the conventional example, respectively. In FIG. 2A, it is assumed that the charge is extracted to the n + source diffusion layer 8 in this embodiment. 3 is a channel region, 4 is a gate insulating film, 5 is a floating gate electrode (gallium phosphide), 6 is an interelectrode insulating film,
Reference numeral 7 indicates a control gate electrode. As shown in FIG. 2A, in this embodiment, since the bandgap Eg of the floating gate 5 is large, the accumulated electrons are higher by 0.2 to 0.5 V than when the conventional floating gate is made of polysilicon. It is in the energy level. Therefore, with respect to the electrons accumulated in the floating gate electrode 5, the barrier of the gate insulating film 4 becomes smaller, and the floating gate electrode 5 and the n + source diffusion layer 8 necessary for tunneling to the conduction band of the gate insulating film 4 are formed. The potential difference ΔV of ΔVb is required to be ΔVb in the conventional example, but can be reduced to ΔVa in the present embodiment. Therefore, in the erase operation, the potential difference between the n + source diffusion layer 8 and the control gate 7 required a high voltage of Vb in the configuration of the conventional example, but in the present embodiment, it was as low as Va and 0.2 to 0.5 V. It can be converted to voltage.

As described above, according to the present embodiment, by forming the floating gate electrode 5 of gallium phosphide having a bandgap larger than that of silicon, it is possible to perform an erasing operation at a low voltage and at a high speed, and thus to erase information. Rewriting can be performed at high speed and low voltage.

In the embodiment, the floating gate electrode 5
Is gallium phosphide, but a semiconductor material having a bandgap larger than that of silicon which is a substrate material (for example, gallium arsenide, silicon carbide, etc.) or a conductor having a work function smaller than that of silicon may be used. Although the stored information is erased by extracting the electric charge from the floating gate to the source region, the electric charge may be extracted from the floating gate to the channel region region. Although hot electrons are used for writing the stored information, FN tunnel current may be used. Although the memory transistor is of the n-channel type, it may of course be of the p-channel type.

[0015]

As described above, in the semiconductor nonvolatile memory device of the present invention, the floating gate electrode is formed of a semiconductor material having a band gap larger than that of the semiconductor forming the substrate or a conductor having a small work function. Therefore, the erase operation of the stored information can be performed at a high speed with a low voltage. Therefore, information can be rewritten at high speed and at low voltage, and a highly reliable semiconductor nonvolatile memory device can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional structural view of a semiconductor nonvolatile memory device according to an embodiment of the present invention.

FIG. 2A is an energy band diagram when erasing stored information in a semiconductor nonvolatile memory device according to an embodiment of the present invention. FIG. 2B is an energy band diagram when erasing stored information in a semiconductor nonvolatile memory device according to a conventional example. Figure

FIG. 3 is a cross-sectional structure diagram of a conventional semiconductor nonvolatile memory device.

FIG. 4 is an energy band diagram when storing information in a conventional semiconductor nonvolatile memory device.

[Explanation of symbols]

 1 p-type silicon substrate 2 element isolation region 3 channel region 4 gate insulating film 5 floating gate electrode 6 interelectrode insulating film 7 control gate electrode (word line) 8 n + source diffusion layer 9 n + drain diffusion layer 10 interlayer insulating film 11 Bit line

Claims (2)

[Claims] 1. A semiconductor substrate of a first conductivity type, a floating gate electrode with a first insulating film interposed on a channel region on the surface of the semiconductor substrate, and a second insulating film interposed on the floating gate. A semiconductor nonvolatile memory device comprising a control gate electrode, wherein the floating gate electrode uses a semiconductor material having a bandgap larger than that of a semiconductor forming the substrate. 2. A semiconductor substrate of a first conductivity type, a floating gate electrode having a first insulating film on a channel region on the surface of the semiconductor substrate, and a second insulating film on the floating gate. A semiconductor nonvolatile memory device comprising a control gate electrode, wherein the floating gate electrode uses a conductor having a work function smaller than that of a semiconductor forming the substrate.