JPH11238814A - Semiconductor memory device and control method thereof - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To enable low-voltage writing and downsizing of a cell size. SOLUTION: The semiconductor memory device of the present invention includes a memory cell transistor 2 and a selection transistor 3 formed adjacently on a semiconductor substrate.
Has a laminated film 7 composed of a silicon oxide film 4, a silicon nitride film 5, and a silicon oxide film 6, and a control gate 8 formed on the upper surface thereof. The selection transistor 3 has a selection gate 9. At the time of data writing, a voltage slightly higher than the source voltage is applied to the selection gate 9 and a voltage of about 5 V is applied to the control gate. As a result, the depletion layer spreads to the drain region side, and electrons are injected into the silicon nitride film 5 along the edge of the source side depletion layer. Therefore, the electron injection efficiency is improved, the cell size can be reduced because there is no floating gate, the control voltage at the time of data writing can be reduced to 10 V or less, and the element structure can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an electrically rewritable semiconductor memory device, for example, an element structure of an EEPROM, and a method of writing and reading data.

[0002]

2. Description of the Related Art Electrically rewritable memories are classified into NOR type and NAND type according to the arrangement of memory cells. The NOR type has high speed but high integration is difficult, and the NAND type has low speed but high integration is easy.

FIG. 8 is a view showing a sectional structure of a conventional NAND type EEPROM. As shown in FIG. 8, the conventional NAND type EEPROM has a structure in which a floating gate 53 is formed on a semiconductor substrate 51 via an insulating film 52, and a control gate 55 is formed on the upper surface thereof via an insulating film 54. ing.

The floating gate 53 is made of, for example, polysilicon, and the control gate 55 is made of, for example, tungsten silicide.

When writing data (electronics),
The source terminal 56 and the drain terminal 57 of FIG. 8 are grounded,
A high voltage of about 20 V is applied to the control gate 55. Thereby, electrons are injected from the substrate 51 into the floating gate 53 by the FN (Fowler-Nordheim) tunnel effect.

On the other hand, when erasing data (electrons), the control gate 55 is grounded, the source terminal 56 and the drain terminal 57 are opened, and a high voltage of about 20 V is applied to the substrate 51. As a result, electrons are extracted from the floating gate to the substrate 51 by the FN tunnel effect.

An EEPROM having a structure as shown in FIG. 8 requires a high voltage of about 20 V to inject / erase electrons into the floating gate 53, and the peripheral transistor must have a high breakdown voltage structure. The element structure becomes complicated,
This leads to a decrease in yield, which in turn leads to an increase in cost.

A so-called source side injection type EEPROM in which electrons are injected into the floating gate 53 from the source side has been proposed. Figure 9 shows this type of EEPR
FIG. 3 is a cross-sectional view illustrating a basic structure of the OM.

The EEPROM shown in FIG. 9 has a structure in which a memory transistor 63 and a select transistor 64 are formed adjacently between a source region 61 and a drain region 62.
The memory cell transistor 63 has a control gate 65 and a floating gate 66, and the selection transistor 64 has a selection gate 6
Seven. The floating gate 66 is generally formed of polysilicon.

To write data (electrons), a high voltage is applied to the control gate 65 and a predetermined voltage is applied between the drain and the source to apply a voltage slightly higher than the threshold voltage of the selection transistor 64. Apply to select gate 67.
As a result, electrons are injected from the source side of the floating gate 66.

The principle of operation is as follows. In the write bias state, the floating gate 66 has an intermediate potential due to coupling with the control gate 65. Floating gate 6
The channel below 6 needs negative charges corresponding to the potential of the floating gate 66, but since the channel current is kept low by the selection transistor 64, the amount of negative charges due to channel electrons is insufficient. To compensate for this shortage, a deep depletion layer S is formed below the floating gate 66 so that the donor of the substrate impurity is ionized.

That is, the energy level on the surface of the Si substrate is greatly reduced. Then, the Si under the floating gate 66
The energy level of the oxide film on the substrate also drops deeply. Thereby, the energy barrier of the Si-oxide film is maintained.

In this state, electrons that have entered from the source region 61 through the channel of the select transistor 67 to the channel region below the floating gate 66 without losing energy are lower than the energy level of the conduction band of the oxide film on the upper surface thereof. Enter with a high energy level. Then, the electrons are injected into the floating gate 66 along the electric field between the floating gate 66 and the substrate, across the energy barrier of the oxide film. On the other hand, the erasure of data (electrons) is controlled by the control gate 65.
And the select gate 64 is grounded, a voltage of about 12 V is applied to the drain 62, and the floating gate 66
It is performed by extracting electrons by FN tunnel effect.

As described above, in the EEPROM of FIG. 9, since the select transistor 64 keeps the program current low and injects electrons from the source side of the floating gate 66 along the traveling direction of the electrons, electrons are injected from the drain side. It is characterized in that the electron injection efficiency is higher than that of normal hot electron injection.

[0015]

However, FIG.
In each of the EEPROMs 9, the floating gate is formed of a conductive material such as polysilicon. When the floating gate is formed of a conductive material, the floating gate causes capacitive coupling with the control gate,
Even if a voltage is not directly applied to the floating gate, the voltage of the floating gate is an intermediate voltage between the voltage applied to the control gate and the ground voltage.

However, if the capacitive coupling between the floating gate and the control gate is weak, the voltage of the floating gate is reduced and the efficiency of electron injection is reduced. Therefore, as shown in FIG. Therefore, it is necessary to increase the coupling ratio between the floating gate and the control gate. Therefore, it was difficult to reduce the cell size, which hindered high integration.

The present invention has been made in view of such a point, and an object of the present invention is to enable electrons to be injected into a charge storage layer at a low voltage, to have a high electron injection efficiency, and to reduce a cell size. An object of the present invention is to provide a semiconductor memory device that can be miniaturized and a control method thereof.

[0018]

According to a first aspect of the present invention, a control gate and a selection gate formed adjacently on a semiconductor substrate are provided. A charge storage layer formed between
A source region and a drain region formed in the semiconductor substrate on both sides of the control gate and the select gate, and when writing data, applying a voltage slightly higher than a threshold voltage to the select gate. A semiconductor memory device for injecting electrons into the charge storage layer from a side closer to the source region, wherein an insulating film formed on an upper surface of the semiconductor substrate is provided between the semiconductor substrate and the control gate; And a silicon nitride film formed on the upper surface of the silicon nitride film, the silicon nitride film in the multilayer film,
At least one of the insulating film and the vicinity of the interface of the silicon nitride film is used as the charge storage layer.

According to a second aspect of the present invention, there is provided a memory cell transistor formed on a semiconductor substrate and having a charge storage layer capable of injecting electrons from the semiconductor substrate, and a select gate formed adjacent to the memory cell transistor and having a select gate. And a source region and a drain region formed in the semiconductor substrate on both sides of the memory cell transistor and the select transistor. When writing data, the select gate has a threshold for the select transistor. A semiconductor memory device in which a voltage slightly higher than a value voltage is applied to inject electrons into the charge storage layer from a side closer to the source region, wherein the memory cell transistor includes an insulating layer formed on an upper surface of a semiconductor substrate. A laminated film including a film and a silicon nitride film formed on an upper surface of the insulating film; A control gate formed on a surface thereof, wherein at least one of the silicon nitride film in the stacked film and the vicinity of an interface between the insulating film and the silicon nitride film is used as the charge storage layer, and the select transistor Is an enhancement type, and the memory cell transistor is a depletion type in a state where electrons are not injected into the charge storage layer.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor memory device to which the present invention is applied and a control method thereof will be specifically described with reference to the drawings. Hereinafter, a NAND type EEPROM will be described as an example.

FIG. 1 is a diagram showing a sectional structure of an embodiment of a semiconductor memory device according to the present invention, and shows a structure of one memory cell of an EEPROM. The EEPROM in Fig. 1
It performs side injection, and Fig. 1
FIG. 1A is a diagram illustrating a basic structure, and FIG. 1B is a diagram illustrating a data writing principle.

The EEPROM of FIG. 1 includes a memory transistor 2 and a select transistor 3 formed adjacently on a semiconductor substrate 1. The memory cell transistor 2 includes a silicon oxide film 4, a silicon nitride film 5, and a silicon oxide film. 6 and a control gate 8 formed on the upper surface thereof. The selection transistor 3 has a selection gate 9.

The EEPROM of FIG. 1 has a silicon nitride film 5 in a laminated film 7 instead of a floating gate made of polysilicon or the like.
Is used as a charge storage layer. To be more precise, the silicon nitride film 5 itself and the vicinity of the interface between the silicon nitride film 5 and the silicon oxide film 4 thereunder are used as a charge storage layer.

Conventionally, since electrons are injected into the floating gate, it is necessary to increase the voltage of the floating gate. For example, the surface area of the floating gate is increased to increase the coupling with the control gate 8. On the other hand, since the laminated film 7 of FIG. 1 is formed of an insulating material, it can be thinned, and the lowermost film 4 of the laminated film 7 can be formed with a low control gate voltage.
Can supply a sufficient electric field. For this reason, the surface area of the stacked film 7 can be reduced and the cell size can be reduced as compared with the conventional floating gate type.

Further, the electrons captured in the silicon nitride film 5 move less in the film than in the case where the electrons are captured in a floating gate formed of polysilicon or the like.
At this time, due to the injected electrons, the voltage of the stacked film 7 gradually decreases from the source side, and the extension of the depletion layer gradually moves to the drain side, so that the source side injection can be performed more efficiently. .

FIG. 2 is a layout diagram of the EEPROM of FIG. 1, and FIGS. 3 and 4 are diagrams showing the manufacturing process of the EEPROM of FIG. 3 and 4 are sectional views taken along the line AA 'of FIG. Less than,
The manufacturing process of the EEPROM shown in FIG. 1 will be briefly described based on these drawings. First, as shown in FIG. 3A, phosphorus ions are implanted into a cell formation region on a P-type silicon substrate 1 to depletion (dotted line portions in the drawing), and then a silicon oxide film 4 is formed on the substrate surface. . Next, as shown in FIG. 3B, a silicon nitride film 5 and a silicon oxide film 6 are sequentially formed on the upper surface of the silicon oxide film 4. That is,
Silicon oxide film 4 / silicon nitride film / silicon oxide film 4
Is formed.

Next, as shown in FIG. 3C, a polysilicon layer 8 which is a wiring material for the control gate 8 is formed on the upper surface of the silicon oxide film 6. Next, as shown in FIG. 4A, a photoresist film 10 is formed on the upper surface of the polysilicon layer 8.
Is formed, the polysilicon layer 8, the silicon oxide film 6, and the silicon nitride film 5 in the location where the select transistor 3 is formed are removed by RIE. Next, boron ions are implanted from above the exposed silicon oxide film 4 to enhance the vicinity of the substrate surface in the location where the select transistor 3 is formed, and then the silicon oxide film 4 and the photoresist film 10 are removed.

Next, a silicon oxide film 4 is formed on the upper surface of the substrate. Next, as shown in FIG. 4B, a polysilicon layer 13 serving as an electrode material of the selection gate 9 is formed on the upper surface of the silicon oxide film 4, and then, as shown in FIG. The polysilicon layer 13 is removed to form the select gate electrode 9. As a result, the selection transistor 3 is formed adjacent to the memory cell transistor 2. Further, a source region 11 and a drain region 12 are formed by implanting impurity ions such as phosphorus. Thereafter, a bit line and a word line (not shown) are formed, and each memory cell transistor 2 is NAND-connected.

FIG. 5 is a diagram showing a voltage applied to each electrode of the EEPROM of the NAND configuration shown in FIG. 1, FIG. 6 is a schematic layout diagram of the EEPROM of FIG. 1, and FIG. 7 is a sectional view of the EEPROM of FIG. The operation of the EEPROM of FIG. 1 will be described below with reference to FIGS.

The EEPROM of FIG. 1 discriminates between "0" and "1" of data depending on whether electrons are injected into the silicon nitride film 5 or near the interface between the silicon nitride film 5 and the silicon oxide film 4. . When electrons are injected into the silicon nitride film 5, the drain electrode D of the selected memory cell (hereinafter, referred to as a selected cell) is set to 5V, and the source electrode S is set to 0V.
In addition, the control gate (CG) 8 is set to 3 V, and the selection gate (S
G) Set 9 to 1.5V.

As shown in FIG. 6, an unselected cell having a drain electrode D and a source electrode S common to a selected cell (hereinafter, referred to as one unselected cell) and a control gate (CG) in a NAND-structured EEPROM. ) 8 and a non-selected cell in which the selection gate (SG) 9 is common to the selected cell (hereinafter, referred to as two non-selected cells). The unselected cell 1 is formed between the drain electrode D and the source electrode S, as shown in FIG.

When writing data to the selected cell, the drain electrode D of one unselected cell is set to 5 V and the selection gate (S
G) 9 and control gate (CG) 8 to 3V, source electrode S
Is set to 0 V, the drain electrode D and the source electrode S of the two unselected cells are set to 0 V, the selection gate SG is set to 1.5 V, and the control gate CG is set to 3 V.

As a result, in the selected cell, the depletion layer S extends from the drain region 12 to the source region 11 as shown in FIG. Here, when the select gate 9 is set to a voltage slightly higher than the threshold voltage, for example, 1.5 V, the electrons flowing from the select gate 9 to the control gate 8 side are, as shown in FIG. Is injected into the left end of the silicon nitride film 5 along the edge of the depletion layer S. When electrons are injected into the silicon nitride film 5, the depletion layer S
The next injected electron is injected slightly to the right (drain side) of the previous injection position, whereby the depletion layer S further shrinks.

Thereafter, similarly, electrons are always injected into the silicon nitride film 5 along the edge of the depletion layer S, so that the electrons can be injected over the entire surface of the silicon nitride film 5.

On the other hand, when data is read, the drain electrode D is set to 1.5 V, the source electrode S and the control gate 8 are set to 0 V, and the selection gate 9 is set to 3 V for the selected cell. Also, the drain electrode D of one unselected cell is set to 1.5
V, the source electrode S is set to 0V, and the selection gate SG and the control gate CG are set to 3V. Further, the drain electrode D and the source electrode S of the two unselected cells are set to 0 V, the selection gate 9 is set to 3 V, and the control gate is set to 0 V.

Thus, for the selected cell, data "0" or "1" can be determined depending on whether a current flows between the drain and the source. More specifically, if electrons are injected into the silicon nitride film 5, the threshold value increases, so that no current flows between the drain and the source.
If electrons have not been injected into the silicon nitride film 5, a current flows between the drain and the source.

As described above, the EEPROM of this embodiment is provided with the laminated film 7 composed of the silicon oxide layer 4, the silicon nitride layer 5, and the silicon oxide film 6 instead of the floating gate. Since the vicinity of the interface between the layer 5 and the silicon oxide film 4 is used as a charge storage layer and electrons are injected into the charge storage layer from the source side, the efficiency of electron injection can be increased. In order to perform source side injection, the voltage applied to the control gate 8 and the like is 10 V
The peripheral transistor does not need to have a high breakdown voltage structure. Therefore, the structure of the EEPROM can be simplified, and the cost can be reduced. Further, the same voltage is applied to the charge storage layer as the control gate 8 irrespective of its size. Therefore, the size of the charge storage layer can be smaller than that of the conventional floating gate, and the cell size can be reduced. Can be increased in capacity.

In the above-described embodiment, an example in which a NAND type structure is used has been described. However, the present invention can be applied to a memory having a configuration other than the NAND type.

That is, when the cell is not the NAND type, there is no unselected one cell in FIG. 6 and a structure in which a plurality of cells are connected to the same control gate (CG) 8 or select gate (SG) 9 is obtained.
The sectional view is as shown in FIG. In this case, FIG.
When writing or reading data to or from the selected cell indicated by the dotted line, the same voltage as in FIG. 5 may be applied to each of the gates 8 and 9, the drain electrode D, and the source electrode S.

[0040]

As described above in detail, according to the present invention, a laminated film is provided instead of providing a floating gate, and a silicon nitride film in the laminated film and an insulating film and a silicon nitride film in the laminated film are formed. By utilizing at least one of the vicinity of the interface as a charge storage layer and forming a control gate and a select gate adjacent to each other to inject electrons into the charge storage layer from the source side, while increasing the electron injection efficiency, The cell size can be reduced. Further, since electrons are injected into the charge storage layer from the source side, the voltage applied to the control gate or the like at the time of data writing can be reduced, and the need for a high breakdown voltage structure is eliminated. Therefore, the structure of the element can be simplified, and the yield can be improved and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a cross-sectional structure of an embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a layout diagram of the EEPROM of FIG. 1;

FIG. 3 is a view showing a manufacturing process of the EEPROM of FIG. 1;

FIG. 4 is a view showing a manufacturing process following FIG. 3;

FIG. 5 is a diagram showing voltages applied to each electrode of the EEPROM of FIG. 1;

FIG. 6 is a schematic layout diagram of the EEPROM of FIG. 1;

FIG. 7 is a sectional view of the EEPROM of FIG. 1;

FIG. 8 is a diagram showing a cross-sectional structure of a conventional NAND type EEPROM.

[Fig. 9] Source side injection type EEPROM
Sectional drawing which shows the basic structure of FIG.

FIG. 10 is a cross-sectional view of an EEPROM devised to increase a coupling ratio between a floating gate and a control gate.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 p-type silicon substrate 2 memory cell transistor 3 select transistor 4 silicon oxide film 5 silicon nitride film 6 silicon oxide film 7 laminated film 8 polysilicon layer 10 photoresist film 11 source region 12 drain region 13 polysilicon layer

Claims (5)

[Claims] A control gate and a select gate formed adjacently on a semiconductor substrate; a charge storage layer formed between the control gate and a surface of the semiconductor substrate; and a charge storage layer formed on both sides of the control gate and the select gate. A source region and a drain region formed in a semiconductor substrate, and when writing data, a voltage slightly higher than a threshold voltage is applied to the select gate, and the data is written from a side close to the source region. A semiconductor memory device for injecting electrons into a charge storage layer, comprising: an insulating film formed on an upper surface of a semiconductor substrate between a semiconductor substrate and the control gate; and a silicon nitride film formed on an upper surface of the insulating film. Is formed, and at least one of the silicon nitride film in the stacked film and the vicinity of the interface between the insulating film and the silicon nitride film is formed as the charge storage layer. A semiconductor storage device characterized by being used as a storage device. 2. A memory cell transistor formed on a semiconductor substrate and having a charge storage layer capable of injecting electrons from the semiconductor substrate; a select transistor formed adjacent to the memory cell transistor and having a select gate; A source region and a drain region formed in a semiconductor substrate on both sides of the memory cell transistor and the select transistor, wherein when writing data, the select gate has a voltage lower than a threshold voltage of the select transistor. A semiconductor memory device in which a high voltage is applied to inject electrons into the charge storage layer from a side closer to the source region, wherein the memory cell transistor comprises: an insulating film formed on an upper surface of a semiconductor substrate; A stacked film including a silicon nitride film formed on the upper surface of the film; and a stacked film formed on the upper surface of the stacked film. A control gate, wherein at least one of the silicon nitride film in the stacked film and the vicinity of the interface between the insulating film and the silicon nitride film is used as the charge storage layer, and the selection transistor is an enhancement type. Wherein the memory cell transistor is of a depletion type in a state where electrons are not injected into the charge storage layer. 3. The method according to claim 1, wherein the memory cell transistor and the selection transistor are paired, and the transistors of each pair are set to NA.
3. The semiconductor memory device according to claim 2, wherein said semiconductor memory device is ND-connected. 4. When writing data, a voltage higher than the source region is applied to the drain region, and a voltage slightly higher than a threshold voltage of the selection transistor is applied to the selection gate. 4. The method according to claim 2, wherein a voltage higher than that of the select gate is applied to the control gate. 5. When data is read, a higher voltage is applied to the drain region than the source region, a higher voltage is applied to the select gate than during data write, and the control gate is turned on. 4. The method according to claim 2, wherein the voltage is set to a ground voltage.