JPH06300814A - Integrated circuit and its testing method - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to an integrated circuit and a method for testing the same, and an integrated circuit including a DC test support circuit having an extremely simple and uniform structure and a simple DC test for such an integrated circuit. The purpose is to provide a test method that can be performed at high speed by a program. In an integrated circuit having a DC test function for an output circuit, an input terminal 2 to which a test signal and a test group selection signal are input, and a group to be a DC test target are selectively selected based on the test group selection signal. A switch for switching the input of the selection energizing circuit 3 for energizing and the input of each output circuit 1 energized by the output of the selection energizing circuit 3 into groups of N or less, from the original signal to the test signal. And a circuit 4. Preferably, N is the maximum number that allows a plurality of output circuits 1 to be switched simultaneously. In addition, in the above integrated circuit test method, (a) 1
(B) input a test signal and inspect each output signal of the above-mentioned 1 test group,
(C) The above steps (a) and (b) are sequentially executed for a plurality of test groups.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit and a test method thereof, and more particularly to an integrated circuit having a DC test function of an output circuit and a test method thereof. HIGH / LO of each output (buffer) circuit when manufacturing integrated circuits
A so-called DC test for confirming the operation at the W level is performed.
In recent years, integrated circuits tend to be complicated and highly integrated, and it is not possible to perform a DC test on all output circuits simply by combining existing input signals that are accessible from the outside. Therefore, there is provided an integrated circuit in which a support circuit for the DC test (DC test function) is incorporated in the integrated circuit, and a DC test can be performed using the circuit, and a test method therefor.

[0002]

2. Description of the Related Art FIG. 5 is a diagram for explaining a conventional integrated circuit and its testing method, in which 30 is a conventional integrated circuit,
1 is an output buffer circuit (B), 31 is a logical operation circuit such as a CPU, FF is a flip-flop forming a register,
B ₃ is a tri-state buffer circuit, 32 is an AND gate circuit (A), 33 is a data bus, 34 is an external access circuit, 35 is a gate logic circuit, O is an OR gate circuit,
36 is a buffer circuit (B).

Data signals D _{0 to} D _n on the data bus 33.
Are led to the respective output terminals via the corresponding output buffer circuits 1. D of each such output buffer circuit 1
Perform C test. By the way, such a data bus 33
Various logic circuits for driving this are connected to, and one of them is a logical operation circuit 31 having a complicated structure such as a CPU. In the logical operation circuit 31, the data D _{0 to} D _n are input from the data bus 33, and the data ID _{0 to} ID _n as a result of the internal logical operation are temporarily stored in the register and are generated in accordance with a predetermined command word. The output on the data bus 33 is performed by the signal G. However, since it is difficult to cause the logical operation circuit 31 to perform the above operation at the DC test stage, it is necessary to devise to drive the output buffer circuit 1 to "1" or "0" by another method. Become.

Conventionally, an external terminal 37 is used for a DC test.
The output of the logical operation circuit 31 whose output is indefinite is first masked by providing a support circuit including the buffer circuit 36 and the mask signal MSK applied to the external terminal 37. In this state, if the external access circuit 34 shown in the figure originally exists, the data signals ED _{0 to} ED _n and the gate signal EG are externally input by using the respective input pins thereof. Data bus 33
Data signals D _{0 to} D _n of "1" and "0" are formed on the upper side, and the DC test of each output buffer circuit 1 is performed by this.

However, it is complicated to design such a unique support circuit for each integrated circuit and incorporate it.
Moreover, although it is preferable to have the external access circuit 34 as the original function of the integrated circuit 30 as in this example, in the case of an integrated circuit in which the external access circuit 34 does not exist,
It is necessary to newly provide the external access circuit 34 as a support circuit for the DC test, and therefore a large amount of circuit space and external terminals are occupied.

Further, the integrated circuit 30 of this example is relatively simple.
Gate logic circuit 3 consisting of a combination of pure gate circuits
5 is also included. Conventionally, such a gate logic circuit
Output of "1" and "0" to each output buffer circuit 1 of 35
An input signal I that causes ₁~ I_qCombination day
Data sequence by an external soft simulation method
Had formed. However, to create such a data series
Takes a lot of time and effort and is a combination of the obtained inputs
Enormous data series (DC test program)
Therefore, it takes a considerable amount of time even when actually performing the DC test.
I needed it. In addition, this kind of integrated circuit has restrictions such as power.
Therefore, it is possible to switch multiple output circuits simultaneously.
You must also consider the maximum number you will get.

[0007]

As described above, in the conventional integrated circuit, a special support circuit for DC test is designed for each integrated circuit and incorporated therein. Therefore, a great deal of labor is required for manufacturing the integrated circuit. Was taking time. In addition, a large amount of circuit space and external terminals may be occupied by the DC test support circuit.

Further, the conventional test method is a method of forming a predetermined output in each output buffer circuit by utilizing an individually designed and designed support circuit and an existing input signal. It took a considerable amount of time to create and execute a DC test by the program. Moreover, since such a DC test program varies for each integrated circuit, the management of the program is complicated.

An object of the present invention is to provide an integrated circuit including a DC test support circuit having an extremely simple and uniform structure and a test method capable of performing a DC test of such an integrated circuit at a high speed by a simple program. It is in.

[0010]

The above-mentioned problems can be solved by the structure shown in FIG. That is, the integrated circuit of the present invention is an integrated circuit having a DC test function of an output circuit, and an input terminal 2 for inputting a test signal and a test group selection signal, and a DC test target based on the test group selection signal. The input signals of the selection energizing circuit 3 for selectively energizing the groups and the outputs of the output circuits 1 energized by the output of the selection energizing circuit 3 and divided into groups of N or less, respectively. To a test signal.

According to the integrated circuit test method of the present invention, in the integrated circuit test method, (a) a test group is selected, (b) a test signal is input, and each output of the test group is output. The signal is inspected, and (c) the above steps (a) and (b) are sequentially executed for a plurality of test groups.

[0012]

In the integrated circuit 10 of the present invention, the selection energizing circuit 3 targets the DC test based on the test group selection signals (for example, the group selection signals S ₀ and S ₁ and the DC test energization signal E). Selectively activate the groups G _{1 to} G _k . The switching circuit 4 is the output SEL of the selection energizing circuit 3.
The input of each output circuit 1 which is energized by _{0 to} SEL _k and is divided into groups of N or less is switched from the original signal (original signal of the integrated circuit) to the test signal T. Then, in this state, the test signal T is, for example, "1", "0".
When changed to, all the output signals of the output circuits 1 of the corresponding group change to "1" and "0" all at once.

As described above, since the integrated circuit 10 of the present invention has a simple and uniform structure in which the switching circuit 4 is provided on the input side of the output circuit 1, it can be applied to any complicated integrated circuit. The insertion design of such a switching circuit 4 is easy,
Moreover, it is easy to mount on an integrated circuit. Further, if the selection energizing circuit 3 is, for example, a decoder, even a small number of selection signals can selectively energize a large number of groups subject to the DC test, so that the number of terminals for the selection signals can be reduced. Further, since one test signal can be distributed to all groups, there are few terminals and circuits added for DC test as a whole. Thus, by providing a very simple and uniform support circuit, a DC test can be easily and reliably performed on any complicated integrated circuit.

Preferably, N output circuits 1 are provided in the same number.
Sometimes it is the maximum number that can be switched. According to the invention
This is because the architecture of the supporting circuit is simple.
It is easy to design circuits that meet such requirements. The present invention
In the method of testing the integrated circuit of, for example, an external IC
The tester selects the test group for (a) input terminal 2.
Signal (eg group selection signal S ₀, S₁And DC
Strike test signal E) to select 1 test group
Select (b) and continue to input the test signal T to the input terminal 2.
Then, each output signal of the first test group is inspected.
Then, (c) the steps (a) and (b) are repeated by a plurality of tests.
Stogroup is executed sequentially.

As described above, according to the test method of the present invention, a DC test of a complicated integrated circuit is performed by simply repeating a simple and uniform test cycle such as test group selection, test signal input and output signal inspection. Will be completed promptly. Moreover, it is not necessary to individually form a combination of input signals to be applied to the integrated circuit by soft simulation or the like as in the conventional case, and the uniform DC as described above is used.
The test program enables easy and reliable DC test on any complicated integrated circuit.

[0016]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The same reference numerals denote the same or corresponding parts throughout the drawings. FIG. 2 is a block diagram of an integrated circuit of the embodiment. In the drawing, 10 is the integrated circuit of the embodiment, 1 is an output buffer circuit (B), 2 is an input terminal for DC test, and 3 is an example of a selection energizing circuit. 3-8 decoder (DEC), 4 ₁ to 4 ₃ are data selectors (SEL) which are switching circuits by way of example, 11 is a CPU including a complicated logical operation circuit, etc. Memory (MEM), 13 is an address bus, 14 is a data bus, 15 is a gate logic circuit, A is an AND gate circuit,
O is an OR gate circuit, and 16 is a buffer circuit (B).

A test group selection signal S is applied to the input terminal 2.
₀ to S ₂ and adding DC test mode signal DCTM If the decoder 3 biased in the test group selection signal SEL ₀ ~
Set any one of SEL ₇ to "1". On a side input of the data selector 4 ₁ has entered the address signal (original signal) A ₀ to A _m and outputting CPU11 is, the b-side input test signal DCTD is input. Then, the data selector 4 ₁ selectively outputs the a-side input when the selection energizing signal SEL ₀ of the decoder 3 is "0", and selectively outputs the b-side input when the selection energizing signal SEL ₀ is "1". Data selector 4 ₂ , 4
_The same applies to ₃ .

The number of the output buffer circuits 1 in each of the test groups G _{1 to} G ₃ is divided by a number equal to or less than the maximum number that can simultaneously switch the plurality of output circuits 1 of the integrated circuit 10. The operation of the DC test of the embodiment for such an integrated circuit 10 will be described below. FIG. 3 is a flowchart of the DC test of the embodiment, which is executed by, for example, an external (not shown) IC tester.

In step S1, a test group selection message is sent.
Issue S₀~ S₂= 0 and DC test mode signal DCTM =
Initialization such as 0 is performed. Accumulation in step S2
S on the input terminal 2 of the circuit 10₀~ S₂= 0 and DCTM =
Add 1 to test group G for address bus₁Choose
Choose. In the integrated circuit 10, the output SEL of the decoder 3 ₀
= 1 and thus the data selector 4₁Well then
Address signal A at₀~ A_mTest instead of selective output of
The signal DCTD is selectively output. Continue in step S3
Input terminal 2 of integrated circuit 10 is tested for "1", "0"
Input the signal DCTD. In the integrated circuit 10, the test group
Loop G₁Each output buffer circuit 1 in the test signal DC
According to "1" and "0" of TD, all at once "1" and "0"
Driven by this, signal A of each output terminal₀~ A_mIn
It changes to "1" and "0" respectively. In step S4
Read each level of "1" and "0" of the output signal from
With this, the function (performance) of each output buffer circuit 1 is detected.
Inspect. In step S5, DC tests for all groups are performed.
It is determined whether or not the strike has ended. If not finished
If so, S in step S6₀~ S₂Update to = 1 and step
Return to S2. This makes it possible to test the data bus
Group G₂DC test is performed. The D
When the C test is completed, the gate logic circuit is further processed in the same manner.
Test group G for 15₃DC test about
Done. DC test for all groups
Upon completion, the determination in step S5 is YES, and
End the reason.

As described above, the DC test program of this embodiment is simple and can be uniformly constructed. In other words, if information such as the number of groups of DC test and the number of output terminals for each group (that is, each pin number) is used as a parameter, the DC test can be performed quickly and surely on any complicated integrated circuit. In this case, it is not necessary to know about the existing input signals I _{1 to} I _q .

FIG. 4 is an operation timing chart of the DC test of the embodiment. Set the test mode signal DCTM to "1"
Then, while the test group selection signals S _{0 to} S ₂ are sequentially updated to 0, 1, and 2 while adding test data DCTD of “1” and “0” as shown in each test phase,
The first in the test phase the same as the input from the output terminals of the address signals A ₀ to A _m, respectively "1", the output signal of "0" is obtained, similarly to the data signal D ₀ in the next test phase ~D the same "1" and input respectively from the output terminals of _n, "0" output signal is obtained, and further from the output terminals of the output signal O ₁ ~ O _p gate logic circuit in the next test phase each in Output signals of "1" and "0" which are the same as those of the input are obtained. The test data D added to the input in this way
"1" and "0" of CTD are immediately output signals of "1",
Since it appears as "0", the time required for the DC test is greatly reduced.

Although the selection energizing circuit 3 is a decoder in the above embodiment, it is not limited to this. Any circuit may be used as long as it selectively activates the group to be the DC test target based on the test group selection signal. Further, although the switching circuit 4 is the data selector in the above embodiment, the present invention is not limited to this. Any circuit may be used as long as the input of the output circuit 1 is substantially switched from the original signal to the test signal.

Further, (b) the test signal of the present invention is input to inspect each output signal of the above-mentioned 1st test group, and each output signal is read and stored in "inspection" of
It also includes the case where they are collectively inspected later.

[0024]

As described above, since the integrated circuit of the present invention has the above-mentioned structure, an appropriate DC test function can be easily designed and mounted on any complicated integrated circuit. Further, since the integrated circuit test method of the present invention has the above-mentioned configuration, the program creation for the DC test is greatly simplified and simplified, and the execution time of the DC test is significantly shortened.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram of an integrated circuit according to an embodiment.

FIG. 3 is a flow chart of a DC test of the embodiment.

FIG. 4 is an operation timing chart of the DC test of the embodiment.

FIG. 5 is a diagram illustrating a conventional integrated circuit and a test method thereof.

[Explanation of symbols]

 10 integrated circuit 1 output circuit 2 input terminal 3 selection energizing circuit 4 switching circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location H01L 27/04 T 8427-4M

Claims (3)

[Claims] 1. In an integrated circuit having a DC test function of an output circuit, an input terminal (2) for inputting a test signal and a test group selection signal, and a group to be a DC test target based on the test group selection signal. Energizing circuit for selectively energizing (3)
And a switching circuit (4) for switching the input of each output circuit (1), which is energized by the output of the selective energizing circuit (3) and is grouped into groups of N or less, from the original signal to the test signal. An integrated circuit comprising: 2. Integrated circuit according to claim 1, characterized in that N is the maximum number by which a plurality of output circuits (1) can be switched simultaneously. 3. The integrated circuit test method according to claim 1, wherein (a) 1 test group is selected, (b) a test signal is input, and each output signal of the 1 test group is inspected. c) A method for testing an integrated circuit, wherein the steps (a) and (b) are sequentially performed for a plurality of test groups.