JPH0623921B2 - Counter device - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a multistage setting type counter device. More specifically, the present invention is a counter that counts the pulses output from, for example, a rotary encoder in accordance with the rotation angle of the shaft, the moving distance, etc., and outputs a control signal when a preset count value is reached. It relates to the device.

[Description of Prior Art]

Conventionally, this type of counter device has been constructed by using a cam switch, a limit switch or the like, so that the whole structure is complicated and large. Also,
There are various problems in that the speed is slow, there is a limit in accuracy, and when the process or the like is changed, the cam switch is replaced and the handling is complicated.

[Outline of Invention]

The present invention has been made in view of the above problems in the prior art, and by electrically setting and storing a set value, a large number of set points and output points can be obtained, and high speed and high accuracy are achieved. The present invention provides a counter device that enables downsizing of the device.

The counter device according to the present invention includes a storage device that stores a plurality of set values in a predetermined order, for example, in order of increasing or decreasing order. Then, from this storage device, two set values that are adjacent to each other and that sandwich the counter count value are called, and these two set values are always on standby. Then, the two set values and the counter count value are compared with each other, and if a coincidence signal is obtained, a signal to that effect is transmitted.

That is, the counter device according to the first aspect of the present invention includes a hard-structured counter that counts pulse signals generated along with linear movement; a set value storage in which a plurality of set values are arranged and stored in ascending or descending order. Means; a first set value,
Two adjacent set values, which are two set values consisting of a second set value set to an address larger than the first set value, and which sandwich the count value of the counter, A set value register which is read from the set value storage means and set; and when a count value of the counter and the first set value match, a control output signal corresponding to the set value is output and a first match signal is output. Outputting the first coincidence signal to be output, outputting a control output signal corresponding to the set value when the count value of the counter coincides with the second set value, and outputting a second coincidence signal Means; when the first match signal is input, the address signal of the set value to be read to the register is decremented by 1, and when the second match signal is input, the address signal of the set value to be read to the register is incremented by 1. , 2 the two address signals adjacent values is supplied to the setting value storing means corresponding to the address
And a set value read counter for setting one set value in the set value register, and the counter device according to the second invention is a hardware-structured counter that counts pulse signals generated with circular motion. A set value storage means in which a plurality of set values are continuously arranged and stored in a predetermined area from a minimum address value to a maximum address value in an ascending or descending order; a first setting value; The two setting values consisting of a second setting value set to an address larger than the setting value of 1 and two adjacent setting values that sandwich the count value of the counter are set as the setting values. A set value register which is read out from the value storage means and set; when a count value of the counter and the first set value match, a control output signal corresponding to the set value is output and a first match signal is output. Comparing means for outputting a control output signal corresponding to the set value and a second match signal when the count value of the counter and the second set value match; the first match signal; When the input signal is input, the address signal of the set value read out to the register is decremented by 1, the maximum address value is set when the address signal is smaller than the minimum address value, and when the second match signal is input, Increment the address signal of the set value read to the register by 1,
When the address signal becomes larger than the maximum address value, the minimum address value is set, and two address signals having adjacent values are supplied to the set value storage means to set the two set values corresponding to the address. And a set value read counter for setting the value register.

Example Next, the present invention will be described based on the example.

FIG. 1 is a block diagram showing the overall configuration of a counter device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing its hardware configuration.

In FIG. 1, (1) is a counter that is supplied with a pulse signal from an encoder (not shown) and counts the pulse signal, which has a hardware configuration (discrete configuration). (2) is an array set value storage means, in which all set values are rearranged and arranged and stored in ascending or descending order. (3) is a set value register, which is an array set value storage means (2)
From the two adjacent two set values, the two set values that sandwich the count value of the counter (1) are read and set.
(4) is a comparison means, which compares the output of the counter (1) with the set value of the set value register (3) and sends a signal according to the comparison result. (5) is a set value read counter, which stores the set value to be the next set value for comparison among the many set values in the array set value storage means (2) based on the signal from the comparison means (4). The specified address signal is sent out, and the set value is sent from the array set value storage means (2) to the set value register (3).

The above counter (1), array set value storage means (2), set value register (3), comparison means (4) and set value read counter (5)
Is the main part of the present invention, and the details thereof will be described later.

Further, in FIG. 1, (11) indicates each setting No. (control output φ1
A keyboard is used, for example, as a set value input means for inputting ~ φn and the set values corresponding thereto. (12) is a first mode selection means, which can select at least an operation mode and a setting mode, and sends a signal indicating each mode. (13) is a second mode selecting means, which can select one-axis operation and circumferential operation (periodic operation), and sends a signal indicating each mode.

(14) is a data transfer means, to which the set value from the set value input means (11) and the mode signal from the mode selection means (12) and (13) are supplied, and various data are supplied based on these input information. Transfer. A set value storage means (15) stores a large number of set values corresponding to each setting number via the data transfer means (14). This storage is performed when the mode selection means (12) is selected in the setting mode. Also, the set value storage means
The setting value randomly input in (15) is the data transfer means.
The values are sorted via the (14) in ascending or descending order and stored in the array set value storage means (2).

(16) is an output command means, the match signal from the comparison means (4) and the output command signal from the data transfer means (14) are supplied,
The control output (ON or OFF) signal of the corresponding output number is sent to the output circuit (17). (18) is a display drive means, which is supplied with the output (count value) of the counter (1), the set value from the data transfer means (14) and the state of each control output (on or off), and displays these values. It is displayed on the device (19) by a digital value or the like.

Next, the correspondence between FIG. 1 and FIG. 2 will be described.

In FIG. 2, the counter (1) is the counter (1) of FIG.
In addition to this, the comparison means (4) is incorporated. (31) is the counter (1)
The microprocessor connected to the CPU performs various arithmetic operations according to the program stored in the ROM (32). The microprocessor (31) and the ROM (32) include a set value register (3), a set value read counter (5), a data transfer means (14), an output command means (16) and a display drive means (shown in FIG. 1). It has the function as 18). (33) is RA
M, array setting value storage means (2) and setting value storage means
It has the function as (15). A keyboard (11) corresponding to the setting input means, a mode selection switch (12),
(13), display (19), ROM (32) and RAM (33) are coupled to the microprocessor (31) via a data bus.
Further, an output circuit (17) is coupled to the microprocessor (31) and sends a control output to the outside based on the comparison result of the comparison means in the counter (1). Although not shown in FIG. 1, even if a cassette interface (34) is provided to record a required program on a cassette tape (not shown) or write an automatic program from the tape, Good.

In the above embodiment, the comparison means (4) is incorporated in the counter (1), but the microprocessor (31) and the ROM (32) are included.
May be used, or a separate comparison calculator may be used. The set value read counter (5) may also have a separate hardware configuration (discrete configuration).

Next, the operation of the apparatus according to this embodiment will be described focusing on the main part of the present invention.

First, the mode selection means (12) is selected to the setting mode, the set value is input by the set value input means (11), and is stored in the set value storage means (15) via the data transfer means (14). Next, the set values are read by the data transfer means (14) in the ascending order, and are arranged and stored in the array set value storage means (2) in the ascending order. Since this method is well known, its explanation is omitted here.

Next, the case where the mode selection means (12) is in the operation mode and the mode selection means (13) is selected for the operation on one axis will be described.

Prior to the explanation, a block diagram showing the main part of the present invention in more detail among the block diagrams shown in FIG. 1 is shown in FIG. 3 and its outline will be described. In the figure,
The same reference numerals as those in FIG.
(3) consists of two set value registers (3A) and (3B),
The comparison means (4) is composed of two comparison circuit units (4A) and (4B), and the set value read counter (5) is also composed of two set value read counters (5A) and (5B). .

Next, the operation in the above case will be described based on the flow chart of FIG.

The values of the array set value storage means (2) equal to or lower than the maximum address n, Ni and Ni + 1, are set value read counters (5A) and (5), respectively.
Write to B). Then, the set value Ai of the array set value storage means (2) contained in the address indicated by Ni is set in the set value register.
Write in (3A) and set value Ai of the address indicated by Ni + 1
Write +1 to the set value register (3B).

Here, the values of Ai and Ai + 1 are set value registers (3
A value such that (A) value (Ai) <counter (1) value Nc (t)) <setting value register (3B) value (Ai + 1)
Is set by the above operation (step 1). This results in the state shown in FIG.

Next, the value of the counter (1) and the values of the set value registers (3A) and (3B) are compared (step 2). The value of the counter (1) changes every moment according to the counting input, and if it matches the value of either one of the set value registers (3A) and (3B), the comparison circuits (4A) and (4
B) sends a coincidence output (step 3). When the value (Ai) of the set value register (3A) and the value (Nc (t)) of the counter (1) match, the control output corresponding to the set value (Ai) outputs the output command means (16). It is sent to the output circuit (17) through the display drive means (18) and to the display device (19) through the display drive means (18) (step 4; see FIG. 1). Then, the coincidence signal A of the comparison circuit (4A) is supplied to the set value reading counters (5A) and (5B), and the value of each counter is decremented by "1" (step 5). On the other hand, the set value register (3B) value (Ai + 1) and the counter value ((Nc
(t)) match, the control output corresponding to the set value (Ai + 1) is output circuit (17) and display (19) as above.
(Step 6). Then, the coincidence signal B of the comparison circuit (4B) is supplied to the set value read counters (5A) and (5B) to increase the value of each counter by "1" (step 7).

Next, set values of the array storage means (2) corresponding to the address signals of the respective counters (5A) and (5B) are set value counters (3A) and (3B).
, And the process returns to step 2. Therefore, when the coincidence signal A is generated, the relationship between the value of the counter (1) and the set value counters (3A) and (3B) is as shown in FIG. 6A. As shown in FIG. 6B.

Next, if the selection mode is the circumferential operation (periodic operation),
Description will be made based on the flow chart shown in FIGS. In this case, it is assumed that the array set value storage means (2) stores set values from address 1 to address n.

Steps 1 to 7 (to) shown in FIG. 7A
Since the contents are the same as the steps shown in FIG. 4, the description thereof will be omitted.

In FIG. 7B, when the coincidence signal A is generated, a comparison is made as to whether or not the value of the set value read counter (5B) is smaller than "1" (step 8), and from "1". When the value is small, the maximum address is displayed in the set value read counter (5B).
That is, "n" is written. On the other hand, when the value of the set value read counter (5B) is "1" or more, a comparison is made as to whether the value of the set value read counter (5A) is smaller than "1" (step 10). ).

If it is smaller than "1", "n" is written in the set value reading counter (5A) (step 11).

If it is "1" or more, the values of the setting read counters (5A) and (5B) remain unchanged and are not changed.

When the coincidence signal B is generated, a comparison is made as to whether or not the value of the set value read counter (5A) is larger than "n" (step 12). "1" is written in the set value reading counter (5A) (step 13). On the other hand, when the value of the setting read counter (5A) is "n" or less, the set value read counter (5A)
A comparison is made as to whether the value of B) is greater than "n" (step 14). If greater than "n",
"1" is written in the set value read counter (5B) (step 15). If the value is "n" or less, the values of the set value read counters (5A) and (5B) remain unchanged and are not changed.

Then, the set values of the addresses indicated by the set value read counters (5A) and (5B) are written into the set value registers (3A) and (3B) (step 16), and the process returns to step 2.

Therefore, the counter (1) and set value read counter (5
The relationship between the values A) and (5B) will be described below with reference to the drawings.

(1) In the case of step 1-2-3-4-5-8-9-16;
Step 2 is in the state shown in FIG. 8-1 (a), and step 16 is in the state shown in FIG. 8-1 (b).

(2) Step 1-2-3-4-5-8-10-11-1
Case 6; Step 2 is in the state shown in FIG. 8-2 (a), and Step 16 is in the state shown in FIG. 8-2 (b).

(3) In the case of step 1-2-3-4-5-8-10-16; in the state shown in FIG. 8-3 (a) in step 2, and in the state shown in FIG. 8-3 (b) in step 16. It becomes the state shown.

(4) In the case of step 1-2-3-6-7-12-12-13-16; in the state shown in FIG. 8-4 (a) in step 2, and in the state shown in FIG. 8-4 (b) in step 16. It becomes the state shown.

(5) Step 1-2-3-6-7-12-12-14-15
In the case of 16, the state shown in FIG. 8-5 (a) is obtained in step 2, and the state shown in FIG. 8-5 (b) is obtained in step 16.

(6) In the case of Step 1-2-3-6-7-12-12-14-16; in the state shown in FIG. 8-6 (a) in Step 2, and in the state shown in FIG. 8-6 (b) in Step 16 It becomes the state shown.

Further, the above description has explained the operation in the state where the operation mode, which is the main operation of the microprocessor, is selected, but in addition to this mode, each mode such as stop, adjustment, setting, and cassette is provided. It is possible. here,
The stop mode is a mode for stopping the entire apparatus, the setting mode is a mode for storing the set value from the set value input means (11) in the setting storage means (15), and the adjustment mode is the RAM (33). This is a mode for changing each set value and the like stored in. This adjustment mode is used when the keyboard is
From (11), the changed data will be written in the RAM (33). In the cassette mode, the program is recorded on the cassette tape via the cassette interface (34) and the program and the like are written from the cassette tape to the RAM (33).

This cassette mode is effective when the same program is written in the RAM (33) of many devices.

By thus selecting the various modes by the mode selecting means (12) and (13), it is possible to perform various kinds of operations and enhance versatility.

〔The invention's effect〕

As described above, the counter device according to the present invention is not only small in size and simple in structure as compared with a device using a conventional cam switch or limit switch, but also can set a large number of set values according to each process. In addition, the detection position can be set, adjusted, and changed easily, and highly accurate position detection can be performed. In addition, since the counter has a hardware configuration, high-speed counting is possible. The combination of the set value read counter and the array set value storage means shortens the processing time required to replace the set value in the set value register, and enables high-speed counting and output processing.

That is, since the count value of the counter is constantly sandwiched between two adjacent set values, the time required for the comparison calculation is shortened.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a counter device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the hardware configuration thereof, and FIG. 3 is a block diagram showing details of main parts of the present invention. Four
The figure shows the flow chart in operating mode (uniaxial operation), No. 5
FIGS. 6A and 6B are explanatory views showing the relationship between the counter (1) and the set value read counter (set value counter), and FIGS. 7A and 7B show the operation mode (circumferential operation). Float chart, Fig.8-1 (a) (b) to Fig.8-6 (a)
(b) is an explanatory view showing the relationship between the counter (1) and the set value reading counter. (1) …… Counter, (2) …… Array set value storage function, (3) (3A, 3B) …… Set value register, (4) …… Comparison means,
(4A), (4B) …… Comparison circuit, (5) (5A, 5B) …… Set value read counter.

Claims (2)

[Claims] 1. A counter having a hardware configuration for counting pulse signals generated with linear motion, a set value storage means in which a plurality of set values are arranged and stored in an ascending or descending order, and a first setting. Value and a second set value that is set to an address having a value larger than the first set value, and two adjacent settings that sandwich the count value of the counter. A set value register that reads out a value from the set value storage means and sets the value, and outputs a control output signal corresponding to the set value when the count value of the counter and the first set value coincide with each other.
The first coincidence signal is output, and when the count value of the counter coincides with the second set value, the control output signal corresponding to the set value is output, and the second
Comparing means for outputting the coincidence signal, and when the first coincidence signal is input, the address signal of the set value read out to the register is decremented by 1, and when the second coincidence signal is inputted, the set value read out to the register. Of the set value read counter for incrementing the address signal of 1 and supplying two address signals of adjacent values to the set value storage means to set two set values corresponding to the address in the set value register. A counter device characterized by the above. 2. A hard-structured counter for counting pulse signals generated by circular motion, and a plurality of set values arranged in a predetermined area from a minimum address value to a maximum address value in ascending or descending order. Two set values including a set value storage means stored and stored, a first set value, and a second set value set to an address having a value larger than the first set value. And a set value register that reads and sets two adjacent set values that sandwich the counted value of the counter from the set value storage means, and the counted value of the counter and the first set value are the same. At this time, the control output signal corresponding to the set value is output, and at the same time, the first match signal is output, and when the count value of the counter and the second set value match, the control output signal corresponding to the set value is output. With the first When the first match signal is input, the address signal of the set value read out to the register is decreased by 1, and when the address signal becomes smaller than the minimum address value, the maximum address value And when the second match signal is input, the address signal of the set value read out to the register is incremented by 1,
When the address signal becomes larger than the maximum address value, the minimum address value is set, two address signals having adjacent values are supplied to the set value storage means, and the two set values corresponding to the address are set. And a set value read counter for setting the value register.