JPH0620195B2 - Speed conversion circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a speed conversion circuit used in a digital electronic circuit. In particular, it is suitable for use in a digital multiplexing system of digital communication equipment.

〔Overview〕

In the speed conversion circuit that temporarily holds the selected data of the low-speed data and the fed back high-speed data, shifts this data with the clock and outputs it, selects the low-speed data at the desired position of the time interval of the high-speed clock. This makes it possible to obtain output data with the bits of input data swapped.

[Conventional technology]

Conventional speed conversion circuits include a shift register circuit that switches clocks and a circuit that uses a RAM. The configuration of the shift register circuit by clock switching is shown in FIG. In this circuit, both signal input and clock input are switched at the time of input and output, and the data input operation and output operation of the shift register 1 are completely independent. Therefore, there are two types of clocks input to the speed conversion circuit, a low speed input clock and a high speed output clock.
The clock selector 3 is operated by using the same selection pulse as the control of the selector 2. In a circuit using a RAM, the RAM address and read / write control can be switched to a speed corresponding to a high-speed output clock.

[Problems to be solved by the invention]

First, since the shift register circuit by clock switching has the same input data speed, frequency, and clock when the input signal is loaded into the shift register, the data order in the shift register is the same order as the input data string, and the order in which it is output is the same. Is output. That is, it is impossible to exchange the bits of the input data on the time axis and output, and there is a drawback that another bit exchange circuit must be connected to the output of this circuit in order to exchange the bits. Generally, bit swapping requires a memory with a capacity equal to all the data, which results in a large increase in hardware.

Further, in a circuit using a RAM, it is necessary to independently control a plurality of addresses, read / write control, and a clock given to the RAM at the time of writing and at the time of reading, so that the control pulse generating circuit becomes complicated.

The present invention eliminates these drawbacks, and an object of the present invention is to provide a speed conversion circuit that does not require a complicated control pulse generation circuit and can output the data by changing the data order of input data.

[Means for solving problems]

The present invention feeds back input data having a transmission rate of M bits per second and output data having a transmission rate of N bits per second (N is a multiple of M), and this input data is input while the selection pulse is in one state. During the period of being selectively output and in the other state, the selector to which this output data is selectively output, and the output of this selector is input, the shift operation is performed by a predetermined clock, and the output is output to the above feedback input. In the speed conversion circuit including the shift register, one of the states of the selection pulse is assigned to a desired region of the time domain obtained by equally dividing each of the bits forming the input data into (N / M) pieces, The frequency of the predetermined clock is NHz.

[Operation] The input signal is selected and input to the shift register for 1 / N second which is the data output time of 1 bit out of 1 / M second which is the data input time of 1 bit, and the output signal is selected for the other time. Then, the selector is controlled by the selection pulse input which is re-input to the shift register, and the shift register operates with a high-speed output clock.

By controlling the pulse position of the selection pulse, the timing of writing in the shift register is adjusted, and high-speed data in which the bits of the input data have been exchanged are output.

〔Example〕

 A circuit according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the circuit according to the embodiment of the present invention. In this embodiment, each of the input signal and the output signal is 8-bit data.

The circuit of this embodiment has an 8-bit shift register 1 for storing an input signal, a selector 2 for selecting an input signal and an output signal, an input terminal 10 for data having a speed of 8 kbit / s,
Data output terminal 11 with speed of 32kbit / s, 1/8000
A selection pulse input terminal 12 to which a selection pulse for selecting an input signal is applied and a clock input terminal 13 to input a 32 kHz clock input to a shift register are provided only for a period of 1/32000 seconds of the second.

FIG. 2 shows the operation of this embodiment. 8kbit as shown
The / s input signal is written to the shift register 1 selected by the 32 kHz clock, and then sequentially output to the output terminal 11. Further, by controlling the position of the selection pulse, the timing of writing the data in the shift register 1 is adjusted, and as a result, the bits of the input signal can be exchanged.

〔The invention's effect〕

As described above, since the present invention can operate only with a high-speed output clock by providing a selectable pulse input whose timing can be controlled, a complicated control pulse generating circuit is not required and the bits of input data can be replaced. There is an effect that can be output.

[Brief description of drawings]

FIG. 1 is a circuit connection diagram showing a configuration of an embodiment circuit of the present invention. FIG. 2 is a timing chart showing the operation of the embodiment circuit of the present invention. FIG. 3 is a circuit connection diagram showing a configuration of a conventional circuit. 1 …… Shift register, 2 …… Selector, 3 …… Clock selector, 10 …… Input terminal, 11 …… Output terminal, 12 ……
Select pulse input terminal, 13 …… Clock input terminal, 14 ……
Output clock terminal.

Claims (1)

[Claims] 1. Input data having a transmission rate of M bits per second,
The output data having a transmission rate of N bits per second (N is a multiple of M) is fed back, and this input data is selectively output while the selection pulse is in one state and this output data is in the other state. In the speed conversion circuit having a selector for selectively outputting and a shift register for inputting the output of the selector and performing a shift operation by a predetermined clock, the output of which serves as the output data for feedback input One of the states is allocated to a desired region of the time domain obtained by equally dividing each of the bits constituting the input data into (N / M), and the frequency of the predetermined clock is NHz. Speed conversion circuit.