JPH061050A - Video interface inspection equipment - Google Patents

Abstract

(57) [Abstract] [Purpose] It is an object to provide an inspection device capable of efficiently inspecting a video interface. An inspection apparatus for inspecting a video interface provided between a controller board of a printer and an engine section, wherein video data sent from the controller board to the engine section via the video interface is sent at the time of sending the video data. The input data is input at the same timing as the sequence, and the input data is sent back to the controller board, so that the CPU on the controller board executes the compare check, and the video interface is inspected only by the compare check of the CPU. Made possible.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a video interface inspection apparatus.

[0002]

2. Description of the Related Art Since a video interface provided on a controller board in a printer outputs serial video data without a sync signal, the inspection method is to actually output an image on paper. , The top margin and the left margin were visually confirmed from the output state.

[0003]

However, in the above-described conventional example, particularly when the substrates are mass-produced, it is necessary to actually output an image for each substrate and see the result. There was a drawback that it took time and was inefficient.

It is an object of the present invention to provide an inspection device capable of efficiently inspecting a video interface.

[0005]

SUMMARY OF THE INVENTION The present invention is an inspection apparatus for inspecting a video interface provided between a controller board of a printer and an engine section, wherein the controller board is connected to the engine section via a video interface. The video data to be transmitted has an input means for inputting at the same timing as the sequence at the time of transmission,
By returning the data input to the input means to the controller board, the CPU on the controller board is returned.
It is characterized by executing a compare check in.

According to the present invention, the controller board is provided with means for inputting the video data output to the engine at the same timing as the sequence at the time of transmission.
The video interface can be inspected only by U compare check.

[0007]

1 is a block diagram showing an embodiment of the present invention.

The inspection apparatus 102 of this embodiment has a video interface 10 on a controller board 101 of the printer.
Connected via 6.

The controller board 101 has an RO in which video data for inspection, a program for inspection, etc. are written.
M103, the controller board 101, and the inspection apparatus 1
It has a CPU 104 that controls the entire system including 03 and performs a compare check of the video data.

On the other hand, the inspection device 102 has an SRAM 105 which expands serial video data sent from the controller board 101 into parallel data and stores the parallel data.

The video interface 106 sends video data to an engine section (not shown) according to a print sequence.

Further, the CPU 104 is the SRAM 10
5, the address bus 107 and the data bus 108
An operation such as data acquisition is performed via the.

Next, FIG. 2 is a flow chart for explaining the operation at the time of inspection by such an inspection device.

First, the CPU 104 sends the video data written in the ROM 103 on the controller board 101 to the inspection device 102 as serial data (S).
1).

In the inspection device 102, the serial video data is expanded at a predetermined timing to be converted into parallel data (S2), which is then SRAM 105.
The data is sequentially written and accumulated on the top (S3). This is the CPU
The process is repeated until 104 finishes sending the serial data (S4).

Next, the CPU 104 reads and writes the data stored in the SRAM 105 (S5 to S7), and compares the read data with the video data which is first read from the ROM 103 and output to the inspection device 102. Yes (S8).

If the two match, (S
9), the inspection result is OK (S10). On the contrary, if they do not match, the inspection result is OK (S11). In this way, the top margin and left margin, which were conventionally inspected by visually observing the actually output paper, are
This can be performed only by the 104 compare check.

Next, FIG. 3 is a circuit diagram showing the internal structure of the inspection apparatus 102.

The inspection device 102 includes the SRAM 105.
In addition, an oscillator 201 that oscillates at the same frequency as the original vibration on the substrate 101, binary counters 202 and 203 that divides the oscillation frequency of the oscillator 201 to generate a video clock and an address, and outputs from the substrate address and the binary counter. 204 for selecting an address to be stored
And a shift register 205 for converting video data serially sent from the board into parallel data,
Latch circuits 207 and 2 for determining the signal level
08 and 209, and a buffer circuit 21 for buffering the video data read from the SRAM 105.
Has 0 and.

Next, details of the operation of the inspection apparatus 102 described with reference to FIG. 1 will be supplemented with FIG.

First, in the inspection apparatus 102, a horizontal synchronizing signal having a certain pulse width is created, and is input to the substrate 101, at the same time, latched by the latch circuit 207 and input to the enable terminal T of the binary counter 202. The binary counter 202 can now be controlled according to the level of the horizontal synchronizing signal.

Next, the original oscillation output from the oscillator 201 is input to the clock terminal of the binary counter 202, and the binary counter 202 produces a video clock by dividing the original oscillation. Here, this video clock is the board 10
1 corresponds to the clock when sending video data. Then, if this video clock is input to the clock terminal of the shift register 205, the serial video signal output from the substrate can be input in parallel at 8 clocks.

The above video clock is also input to the clock terminal of the binary counter 203, and the binary counter 203 is configured to output a pulse to the clock terminal of the latch circuit 208 after 8 clocks. Then, the latch circuit 208 can latch just when 8-bit video data is input. The latched data is stored at the address created by the binary counter 203 on the SRAM 105,
The data is written at a timing that stabilizes the data. If such an operation is performed each time the horizontal synchronizing signal is input, data is written in the SRAM 105 one after another.

The above is the principle of converting the serial data in FIG. 1 into parallel data and storing the parallel data in the SRAM 105.

Next, the data in the SRAM 105 is transferred to the CPU 1
The principle of 04 leading will be described.

First, when the data stored in the SRAM 105 is read, the select signal in the selector 204 is switched, and the address directly input from the substrate 101 through the address path is selected.
The data corresponding to the address on M105 is read by the CPU 104 at the same timing as the switching of the select signal. Then, the data is transferred to the buffer circuit 21.
It is input to the substrate 102 through 0.

If the system is operated with the above-described structure, it is possible to confirm how many times the horizontal synchronizing signal is input for the first time only by looking at the data read by the CPU 104. It is possible to check the margin and also check the bit number of the data input after the horizontal sync signal is input, so that the left margin can be checked.

FIG. 4 is a circuit diagram showing a selection circuit portion of an oscillator according to the second embodiment of the present invention.

In the above embodiment, only one oscillator is provided and the operation is explained by using the single oscillation frequency as the original oscillation. However, in the second embodiment, the controller board of the printer having a plurality of switchable resolutions. In order to inspect 102, a plurality of oscillators are provided on the inspection device 101. The configuration other than the selection of the oscillator is the same as that of the above embodiment, and the description thereof is omitted.

In this way, the video data can be inspected for each resolution simply by switching the clock input of the latch circuit 7 of FIG.

That is, in FIG. 4, when the clock switching signal is input to the AND circuits 402 and 403 by "H", the input to the AND circuit 402 becomes "H" and the AND circuit is input to the clock input of the latch circuit 7. 402 and O
The oscillation frequency f of the oscillator 201A is transmitted via the R circuit 404.
_A pulse whose original vibration is _A is input. Therefore, the inspected video data will be of the resolution represented by f _A.

On the other hand, conversely, the clock switching signal is set to "L".
When the AND circuits 402 and 403 are input, the NOT circuit 405 changes the input to the AND circuit 403 to "H". Therefore, the inspected video data is transmitted to the oscillator 20.
The resolution is represented by the oscillation frequency f _B of 1B. Therefore, it is possible to recognize whether the video data of each resolution is normally transmitted and received by performing the inspection twice.

[0033]

As described above, according to the present invention,
Since the video interface can be inspected only by the CPU compare check, there is no need to actually output the image on paper and visually inspect it, and there is an effect that the efficiency of the inspection process in mass production can be improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart illustrating an operation at the time of inspection by the inspection device of the same embodiment.

FIG. 3 is a circuit diagram showing in detail the configuration of the inspection apparatus of the same embodiment.

FIG. 4 is a circuit diagram showing a selection circuit portion of an oscillator according to a second embodiment of the present invention.

[Explanation of symbols]

 101 ... Controller substrate, 102 ... Inspection device, 103 ... ROM, 104 ... CPU, 105 ... SRAM, 106 ... Video interface.

Claims (1)

[Claims] 1. An inspection device for inspecting a video interface provided between a controller board of a printer and an engine section, wherein the video data sent from the controller board to the engine section via the video interface is transmitted by the inspection apparatus. It has an input means for inputting at the same timing as the sequence at the time of sending, and by returning the data input to this input means to the controller board, the CPU on the controller board executes a compare check. Video interface inspection device.