JPH11120212A - Method and device for designing circuit and recording medium recorded with program therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the influence of a metastable from being propagated into an LSI by inputting an asynchronous signal to a 1st order cell, inputting a signal outputted from the 1st order cell based on the asynchronous signal to a 2nd order cell and inputting a signal outputted from the 2nd order cell to a circuit. SOLUTION: Order cells 1 and 2 are connected in series, a clock signal CLK is inputted to the respective order cells 1 and 2, and the respective order cells 1 and 2 are synchronously operated. Therefore, set-up at the order cells 1 and 2 is simultaneously performed. Based on an asynchronous signal IN1 inputted from an external input pin, a signal Q1 is outputted from the order cell 1. Based on the signal Q1, a signal Q2 is outputted from the order cell 2. Thus, the order cell is designed so as to input a signal, in which the metastable does not occur, to the LSI circuit even when the asynchronous signal IN1 having the possibility not to keep set-up is inputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit design method and apparatus for designing a circuit such as an LSI by using, for example, a hardware description language, and a recording medium on which the program is recorded.

[0002]

2. Description of the Related Art FIG. 12 is a flowchart when a conventional LSI design is performed. Generally, when designing an LSI, a hardware description language (hereinafter, HDL: Hardware Descripti
on La-nguage). What is HDL?
This is a language used when describing the function of the LSI to be designed. When the HDL is described as shown in FIG.
101), a function level operation check (hereinafter referred to as function verification) is performed (S102), and the function is checked (S102).
3) If an unintended operation is found, the HDL is corrected and the function verification is performed again. At this stage of function verification, verification of timing (delay, setup, and hold time) is not performed. Here, the setup time in the sequential cell is a time in which data (signal value) must be determined before a clock signal is input. If the data is not determined within the setup time (that is, if the signal value changes within the setup time), there is no compensation for determining the data.

FIG. 13 is a diagram showing an example of an HDL description and an example of an LSI circuit represented by the HDL. Function verified H
DL is HDL as shown in FIG. 13 by logic synthesis software or the like.
Is converted to LSI circuit diagram data that operates as described in (S104). The converted LSI circuit diagram data is checked for operation at the circuit diagram level (hereinafter referred to as circuit verification) by a circuit simulator or the like (S1).
05). The circuit verification differs from the function verification in that the verification including the timing of each element is performed. Further, in recent years, verification including wiring delay data after layout by a layout tool has been performed. If an unintended operation is found due to element or wiring delay in the confirmation by circuit verification (S106), conversion to an LSI circuit diagram is performed again and circuit verification is performed. In some cases, the correction may be made by returning to the stage of describing the HDL.

FIG. 14 is a diagram showing a setup time of a sequential cell in an LSI circuit. In the figure, the sequential circuits A and B are a set of sequential cells. The combinational circuit unit synchronizes the clock signal, and receives the signal value output from the sequential circuit A unit as an input and propagates a change in the signal value of the combinational circuit unit to the sequential circuit B unit.

Here, if the propagation delay between the input and output of the combinational circuit section is large and the setup time of the sequential circuit B section is not maintained, the data cannot be compensated at the time when the clock signal is inputted. , The circuit simulator outputs an indefinite value as the output of the sequential circuit B. An undefined value is a state in which HIGH or LOW cannot be determined as a signal value.

As described above, the timing of the setup time and the like is also verified inside the LSI circuit.
The operation verification equivalent to the actual hardware LSI can be performed by the SI circuit verification.

[0007]

However, in the timing verification performed at the time of circuit verification, attention must be paid to signals asynchronously input from outside the LSI. This is because there is no guarantee that the setup time is maintained in the sequential cell because the signal is input asynchronously.

FIG. 15 is a time chart of a sequential cell circuit which malfunctions due to the input of an asynchronous signal from the outside and its input / output signals. If an asynchronous signal is input from an external input pin, and if the setup time of the sequence cell is not maintained, a signal change called metastable as shown in the time chart of FIG. 15 occurs in the output Q from the sequence cell. , Which propagates inside the circuit,
The I circuit may malfunction.

Therefore, it has been desired to realize an LSI design method in which the influence of metastable does not propagate inside the LSI and to realize an apparatus which can surely perform the design.

[0010]

A circuit design method according to the present invention includes a step of designing an external asynchronous signal to be input to a first sequential cell, and a method of designing a first sequential cell based on the asynchronous signal.
Designing a signal output from the second order cell to be input to a second order cell operating in synchronization with the first order cell; and outputting a signal output from the second order cell to a circuit. And designing the data to be input internally. In the present invention, the first sequential cell is designed to receive an asynchronous signal from the outside. The signal output from the first order cell based on the asynchronous signal is designed to be input to a second order cell that operates in synchronization with the first order cell, and is generated in the first order cell. The metastable is input at a time other than the setup time of the second ordered cell. A signal without metastable output from the second sequential cell is designed to be input into the circuit, a malfunction of the circuit is prevented, and a highly accurate circuit is designed.

In the circuit designing apparatus according to the present invention, when a signal name of a clock signal is inputted in a stage of describing a function of a circuit to be designed and performing a function design in accordance with a predetermined rule, the signal Searching means for searching for a description of a sequence cell operating based on a clock signal of a name, and determining whether a signal name of a signal input asynchronously is described for the description of the sequence cell searched by the searching means If the signal name is described, it is determined whether or not the description of the sequential cell is described in the signal name so that the description is made up of two or more connections operating in synchronization with the clock signal. If it is determined that there is no description that is composed of two or more connections operating in synchronization with the clock signal, a warning signal is output from the determination means for outputting a warning signal, and a warning signal is transmitted from the determination means. And a warning output means for issuing a warning with. In the present invention, when a signal name of a clock signal is input, a search unit searches for a description of a sequential cell that operates based on the clock signal having the signal name. The determining means determines whether or not the signal name of the signal input asynchronously is described with respect to the description of the searched order cell,
If the signal name is described, the description of the sequence cell is described in the signal name so as to be composed of two or more stages of connections that operate in synchronization with a clock signal that can avoid metastable. If it is determined that there is no description that is composed of two or more connections operating in synchronization with the clock signal, a warning signal is output. The warning output means issues a warning when the warning signal is transmitted, so that measures against metastable are made conscious at the function description stage.

Further, the circuit design device according to the present invention is constituted by a two-stage connection which operates in synchronization with a clock signal when a warning signal is received from the judgment means instead of the warning output means. A description changing means for rewriting such a description and outputting the effect is provided. In the present invention, when the determining means determines that the description is not made up of two or more connections operating in synchronization with the clock signal, the description changing means replaces the warning output means with the description changing means. Based on the warning signal, the description is rewritten as a two-stage connection that operates in synchronization with the clock signal, and that effect is output, and a measure against metastable is automatically performed to avoid metastable.

Further, when the signal name of the clock signal is inputted to the recording medium according to the present invention, the description of the sequence cell operating based on the clock signal of the signal name is searched, and the searched sequence cell is searched for. In the description, it is determined whether or not the signal name of the signal input asynchronously is described. If the signal name is described, two or more stages that operate in synchronization with the clock signal in response to the signal name When it is determined whether or not the sequence cell is described so as to be configured by the connection of the above, and it is determined that the description is not configured so as to be configured by two or more connections operating in synchronization with the clock signal,
Record the program that causes the computer to output the alert. In the present invention, when a signal name of a clock signal is input, a description of a sequential cell operating based on the clock signal of the signal name is searched. In addition, it is determined whether or not the signal name of the signal input asynchronously is described in the description of the searched order cell. If the signal name is described, the signal name is synchronized with the clock signal. It is determined whether or not the sequence cell is described so as to be constituted by two or more stages of connections that operate in response to a clock signal. If it is determined that there is no meta-stable, a warning is output so that the user can be conscious of the meta-stable measures at the function description stage.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 is an HDL description example for realizing the circuit design method according to the first embodiment of the present invention, and the HDL description.
FIG. 3 is a circuit diagram generated by. In the figure, reference numerals 1 and 2 denote sequential cells constituted by sequential elements. Order cell 1
And 2 are connected in two stages, the clock signal CLK is input to each of the sequential cells, and each of the sequential cells operates in synchronization. Therefore, the setup time in the order cells 1 and 2 is performed at the same time. A signal Q1 is output from the order cell 1 based on the asynchronous signal IN1 input from the external input pin. Also, based on the signal Q1, the sequence cell 2 outputs a signal Q2. The present embodiment provides a method of designing a sequential cell in which a signal free from metastable is input to an LSI circuit even when an asynchronous signal that may not follow setup is input.

FIG. 2 is a diagram showing an example of a time chart of signals input to the circuit diagram of FIG. The signal flow when two or more sequential cells are connected will be described with reference to FIGS. When the asynchronous signal IN1 whose setup is not protected is input from the external input pin,
In the order cell 1, the asynchronous signal IN1 has an indefinite value, and a metastable appears in the signal Q1. The signal Q1 in which the metastable appears is input to the order cell 2 as it is.

However, at the time when the metastable is input to the order cell 2, since the set-up time has expired in the order cell 2, the signal value of the signal Q1 input to the order cell 2 has been determined. Therefore, the signal Q2 output from the order cell 2 is a signal in which metastable is not generated, and this signal is input into the LSI circuit, and the setup time of the order cell 1 is not maintained. The signal Q2 is not affected by the metastable generated due to this.

As described above, according to the first embodiment,
Since the order cells 1 and 2 are connected in two stages and the order cells are designed to operate in synchronization with each other, the asynchronous signal IN1 is input to the order cell 1 and the signal Q1 output from the order cell 1 is output. Even if a metastable occurs, the metastable is not input during the set-up time of the sequence cell 2, and the signal Q1 input to the sequence cell 2 is determined. A signal which does not generate metastable and which does not generate metastable inside the LSI circuit can be input as the signal Q2 to be output, and high-precision circuit verification can be performed to design a high-quality circuit. Can be.

Embodiment 2 FIG. FIG. 3 is a block diagram of an apparatus for realizing an LSI design method according to the second embodiment of the present invention. In the figure, reference numeral 10 denotes a main body of an LSI design apparatus, which includes an asynchronous input signal warning unit 11 and a function verification unit 1.
2. It is composed of a circuit diagram generating means 13 and a circuit verifying means 14. The asynchronous input signal warning means 11 further comprises an HD
Search means 11 for searching the description of an ordered cell based on L
A: It is determined whether or not the description includes an asynchronous input signal, and it is determined whether or not the sequential cells are described in two stages for the asynchronous input signal. And a warning output unit 11C that outputs a warning when a warning signal is received. The function verification unit 12 performs function verification based on the HDL.
The circuit diagram generating means 13 generates a circuit diagram based on HDL. The circuit verification unit 14 generates the circuit diagram
Perform circuit verification including timing verification.

Reference numeral 20 denotes a storage unit, which includes an allocated component storage unit 21, a program storage unit 22, and a design information storage unit 23.
It is composed of Here, the assigned component storage means 21 stores data of assigned components to be referred to when the circuit diagram creating means 13 creates a circuit diagram. The design information storage means 23 stores information on the designed circuit diagram.
Numeral 30 is a function description input means, which is input by the operator to the HD.
L is input and transmitted to the LSI design apparatus 10. Reference numeral 40 denotes an output unit. In the present embodiment, it is assumed that the output unit 40 is, for example, a display unit that provides a display to an operator.

The LSI circuit design method for avoiding metastable has been described in the first embodiment. However, due to the inexperience of a design beginner or the lack of attention of a skilled person, the number of ordered cells is two as in the first embodiment. HDL not composed of steps
Is described, and a malfunction due to metastable may occur. In this case, the metastable can be found based on the LSI circuit diagram, and at that time, the problem can be solved by changing the LSI circuit diagram. However, when the metastable workaround is implemented by changing the LSI circuit diagram after the conversion in this way, inconsistencies may occur between the function described in the HDL description stage and the operation of the LSI circuit diagram. ,
If the hardware is used as it is, a situation arises in which the originally intended function does not match the operation of the hardware LSI circuit. Therefore, the present embodiment provides an LSI circuit design apparatus that allows an LSI circuit designer to make a description in consideration of increasing the number of sequential cells in a function description stage by HDL.

FIG. 4 is a flowchart showing an LSI design procedure using the apparatus shown in FIG. The LSI design operation will be described with reference to FIGS. Function description input means 3
When HDL is input from 0 (S1), the asynchronous input signal warning means 11 performs an operation as shown in FIG. 5 when a clock signal name of a design circuit is input (S2).

FIG. 5 is a flowchart showing the processing procedure of the asynchronous input signal warning means 11. When the clock signal name is input from the LSI circuit designer (S11), the search unit 11A of the asynchronous input signal warning unit 11 searches for a description of a sequential cell that operates based on the clock signal based on HDL (S11). S12). The determination means 11B determines whether or not there is a description of an asynchronous input signal input from the outside with respect to the description of the ordered cell, and performs the following loop for the described asynchronous input signal (S13 to S1).
6). Here, in the HDL, the asynchronous input signal includes “A
The description of “SYN_IN” is set as a rule that must be input by the LSI circuit designer, and the determination means 11B
Extracts a signal labeled "ASYN_IN" from the HDL description.

The determining means 11B determines, based on the HDL description, whether or not the ordered cell operating with the clock signal name input in S11 to which the searched asynchronous input signal is input is composed of two or more stages. A determination is made (S14).
Here, when the ordered cells have a single-stage configuration, a warning signal is output, and the warning output unit 11C that has received the warning signal outputs a warning message to the output unit 40 (S15). FIG. 6 is a diagram showing an example of an HDL description in which the order cell has a single-stage configuration and an example of a warning message in that case. If the HDL is described so that the ordered cell is composed of two or more stages, the determining means 11B further determines, for the asynchronous signal denoted by “ASYN_IN”, 2 bits for the described ordered cell.
It is determined whether or not the configuration is equal to or greater than the number of stages (S14).

When the HDL confirmation of the ordered cells by the asynchronous input signal warning unit 11 is completed, the function verification unit 12 performs function verification based on the designed circuit (S3). If the expected function is obtained by function verification (S
4) The circuit diagram generating means 13 allocates the allocated components stored in the allocated component storage means 21 to generate a circuit diagram (S5). If you don't get what you expect,
The operator re-enters HDL to obtain the expected function.
Is described again.

When the circuit diagram is generated, the circuit verification means 14
Performs circuit verification (S6). If timing verification or the like is expected as a result of circuit verification (S7), hardware implementation is attempted. If not as expected, a circuit diagram is created again and circuit verification is performed.

As described above, according to the second embodiment,
The search means 11A searches for a description of a sequential cell operated by a signal based on the input clock signal name, and determines
Determines whether there is a description of an asynchronous input signal that does not adhere to the setup time in the description, determines whether or not the sequential cell is described in two stages for the asynchronous input signal, For example, since the warning output unit 11C issues a warning to the LSI circuit designer via the output unit 40, the malfunction due to the LSI metastable is set to H.
It can be considered at the DL description stage. In particular, it is effective for beginners of LSI circuit design who are unfamiliar with measures against metastable, and improvement in the quality of hardware LSIs can be expected regardless of the level of skill of the designer. In addition, a distinction is made as to whether or not the signal is an asynchronous signal, and the processing is performed only on the sequence cells to which the asynchronous input signal is input, and the processing is not performed on the synchronous signal, so that the processing speed can be increased.

Embodiment 3 FIG. 7 is a block diagram of an apparatus for realizing the LSI design method according to the third embodiment of the present invention. In the figure, the components having the same reference numerals as those in FIG. 3 perform the same operations as those described in the second embodiment, and therefore the description is omitted. In the figure, reference numeral 10A denotes an LSI design apparatus provided with a sequential cell insertion means 15 instead of the asynchronous signal warning means 11. Reference numeral 15 denotes an ordered cell insertion unit. In addition to the search unit 15A and the judgment unit 15B that perform the same operations as the search unit 11A and the judgment unit 11B described in the first embodiment, an asynchronous cell is used instead of the warning output unit 11C. In a sequence cell to which an input signal is input, L
HD in which the SI designer configures ordered cells in one or less stages
When the description of L is made, description changing means 15 for rewriting HDL so that the order cells are automatically described as two levels.
C. In the present embodiment, LS is
If the input of the asynchronous input signal is defined from the outside when the function description of I is made, and if the asynchronous input signal is not described so as to be captured by two or more sequential cells, the input is described. The HDL is provided with means for changing the HDL description so that the order cells are automatically set to two levels.

FIG. 8 is a flowchart showing an LSI design procedure using the apparatus of FIG. In FIG. 8, those having the same step numbers as those in FIG. 4 perform the same processing, and thus the description thereof will be omitted. In the figure, S2A represents the processing of the ordered cell insertion means 15.

FIG. 9 is a flowchart showing the processing procedure of the ordered cell insertion means 15. H from LSI circuit designer
When a clock signal name is input by DL (S21),
Based on the HDL, the description of the ordered cell that operates based on the clock signal is searched (S22). Judgment means 15B
Determines whether there is a description of an asynchronous input signal input from the outside with respect to the description of the sequence cell, and performs the following loop for the described asynchronous input signal (S23)
To S31). Here, in the HDL, the description of “ASYN_IN” is set as a rule that must be input by the LSI circuit designer for the asynchronous input signal, and the determination unit 15B outputs the signal labeled “ASYN_IN” from the HDL description. To be extracted.

Determination means 15B of ordered cell insertion means 15
Is the S21 to which the extracted asynchronous input signal is input.
It is determined based on the HDL description whether or not the ordered cells operating with the clock signal name input in (2) are composed of two or more stages (S24). If there are two or more stages, the loop is repeated until the asynchronous input signal ends (S31). If it is determined that the ordered cell is not composed of two or more stages, it is next determined whether or not the ordered cell is composed of one stage of cells based on the HDL description (S25).

FIG. 10 shows HDL description examples in the case where there is no ordered cell, the case of one stage, and the case of two stages. FIG. 11 is a diagram showing a description example of the HDL corrected by the ordered cell insertion means and a warning message example in that case. When a single-stage sequence cell uses the asynchronous input signal ASYN_IN1 as an input signal and Q1 as an output signal, the description changing means 15C
Uses the asynchronous input signal ASYN_IN1 as an input signal,
A description is automatically made so that a sequence cell is added by one stage such that a sequence cell having ASYN_IN1_TMP as an output signal is a first stage, a sequence cell having ASYN_IN1_TMP as an input signal, and a sequence cell having Q1 as an output signal is a second stage. (S
26). After the HDL is modified, a message to the effect that the HDL has been modified is output to the display means 40 or the output means 41 (S27).

In S25, no sequential cell is formed for the asynchronous input signal based on the HDL description, and the asynchronous input signal (ASYN_IN3 in FIG. 10) is the same as the signal (IN4) directly input to another circuit. If it is determined that there is, the description change unit 15C outputs the asynchronous input signal ASYN
_IN3 as an input signal, and ASYN_IN3_TMP as an output signal.
3_TMP as an input signal and ASYN_IN3_TMP
A description is automatically made to add two stages of ordered cells so that the ordered cells whose output signal is 2 is the second stage (S2).
8). Also, ASYN_IN instead of ASYN_IN3
The HDL to be replaced is automatically described so that 3_TMP2 is input as IN4 (S29). After the HDL is modified, a message to the effect that the HDL has been modified is output to the display means 40 or the output means 41 (S30).
The process is repeatedly performed on the asynchronous input signal with “ASYN_IN” (S31).

As described above, according to the third embodiment,
The searching means 15A of the ordered cell inserting means 15 searches for the description of the ordered cell operated by the signal according to the input clock signal name, and the judging means 15B includes the description of the asynchronous input signal which does not adhere to the setup time. It is determined whether or not the sequence cell is described in two stages for the asynchronous input signal. If the sequence cell is one stage or less, the description changing means 15C causes the sequence cell to be configured in two stages. Since the HDL is rewritten and the fact is output to the output means 40, the possibility of a malfunction due to the metastable of the designed LSI can be automatically avoided at the HDL description stage. Further, processing is performed only on the ordered cells to which the asynchronous input signal is input, and processing is not performed on the synchronous signal, so that the processing speed can be increased.

Embodiment 4 FIG. In the above-described embodiment, a D flip-flop is described as an example of a sequential cell. However, the present invention is not limited to this, and any cell having a function as a register may be used. Further, as long as the two sequential cells are synchronized with each other by the clock, there is no problem even if two different cells are provided in two stages.

Embodiment 5 FIG. Further, in the above-described embodiment, the description has been made on the premise that the order cells have two stages. However, the present invention is not limited to this, and is also effective when connecting two or more order cells. . However, regarding the possibility of circuit malfunction due to metastable,
This can be avoided by configuring at least the order cells in two stages.

Embodiment 6 FIG. Further, in the above-described embodiment, the function verification and the circuit verification are performed simultaneously by one device, but the present invention is not limited to this, and may be configured by another device. Further, storage means and the like may be connected via a network.

Embodiment 7 In the above embodiment, LS
Although the I design apparatus main body 10 is provided with means having respective roles and operated, the present invention is not limited to this, and (in fact) the LSI design apparatus main bodies 10 and 10A are, for example, computers. Means for executing an LSI design process based on an HDL simulator or a circuit simulator program by a logic synthesis tool stored in the program storage means 22 of the storage means 20. Good.

[0038]

As described above, according to the present invention, an asynchronous signal from outside is designed to be input to the first sequential cell, and a signal output from the first sequential cell based on the asynchronous signal is output. , The second order cell operating in synchronization with the first order cell is designed to be input, and the signal output from the second order cell is designed to be input into the circuit. Even if the metastable generated in the signal output from the second order cell is input to the second order cell, since the data is fixed in the second order cell, the signal output from the second order cell A signal in which metastable does not occur and metastable does not occur is input into the circuit, so that highly accurate circuit verification can be performed and a high-quality circuit can be designed.

Further, according to the present invention, when the signal name of the clock signal is inputted by the search means, the search means searches the description of the sequential cell which operates based on the clock signal of the signal name, and the judgment means makes the search. It is determined whether or not the signal name of the signal input asynchronously is described in the description of the ordered cell. If the signal name is described, the description of the ordered cell is described in the metastable Is determined so as to be configured with two or more stages of connections operating in synchronization with a clock signal, and is configured with two or more stages of connections operating in synchronization with a clock signal. If it is determined that such a description has not been made, a warning signal is output, and the warning output means issues a warning when the warning signal is transmitted, and the countermeasures for metastable are made conscious at the function description stage and corrected. Rukoto is possible. Further, the processing is performed only on the description of the sequential cell to which the asynchronous input signal is input, and the processing is not performed on the synchronous signal, so that the processing speed can be increased.

Further, according to the present invention, when the judging means judges that there is no description composed of two or more connections operating in synchronization with the clock signal, Instead of the warning output means, the description is rewritten as a two-stage connection that operates in synchronization with the clock signal based on the warning signal, and the fact is output. This can be automatically avoided at the description stage. Further, processing is performed only on the ordered cells to which the asynchronous input signal is input, and processing is not performed on the synchronous signal, so that the processing speed can be increased.

[Brief description of the drawings]

FIG. 1 is an HDL description example for realizing a circuit design method according to a first embodiment of the present invention, and a circuit diagram generated by the HDL.

FIG. 2 is a diagram illustrating an example of a time chart of signals input to the circuit diagram of FIG. 1;

FIG. 3 is a block diagram of an apparatus for realizing an LSI design method according to a second embodiment of the present invention.

FIG. 4 is a flowchart illustrating an LSI design procedure using the device of FIG. 3;

FIG. 5 is a flowchart illustrating a processing procedure of an asynchronous input signal warning unit 11;

FIG. 6 is a diagram illustrating an example of an HDL description in which a sequential cell has a single-stage configuration and an example of a warning message in that case.

FIG. 7 is a block diagram of an apparatus for realizing an LSI design method according to a third embodiment of the present invention.

FIG. 8 is a flowchart showing an LSI design procedure using the device of FIG. 7;

FIG. 9 is a flowchart showing a processing procedure of the ordered cell insertion means 15;

FIG. 10 is a diagram illustrating an example of an HDL description in the case where there is no ordered cell, in the case of one stage, and in the case of two stages.

FIG. 11 is a diagram illustrating a description example of HDL corrected by the ordered cell insertion unit and a warning message example in that case.

FIG. 12 is a flowchart when a conventional LSI design is performed.

FIG. 13 is an example of an HDL description and L represented by the HDL.
FIG. 3 is a diagram illustrating an example of an SI circuit.

FIG. 14 is a diagram illustrating a setup time of a sequence cell in an LSI circuit.

FIG. 15 is a time chart of a circuit which malfunctions due to input of an asynchronous signal from the outside and its input / output signals.

[Explanation of symbols]

 10, 10A LSI design apparatus body 11 Asynchronous input signal warning means 11A Search means 11B Judgment means 11C Warning output means 12 Function verification means 13 Circuit diagram generation means 14 Circuit verification means 15 Ordered cell insertion means 15A Search means 15B Judgment means 15C Description change Means 20 Storage means 21 Allocated parts storage means 22 Program storage means 23 Design information storage means 30 Function description input means 40 Output means

Claims (5)

[Claims] A step of designing an external asynchronous signal to be input to a first sequential cell; and a step of outputting a signal output from the first sequential cell based on the asynchronous signal to the first sequential cell. A step of designing so as to be input to a second order cell operating in synchronization with the order cell; and a step of designing such that a signal output from the second order cell is input into a circuit. A circuit design method comprising: 2. A circuit design apparatus for performing a function design by describing a function of a circuit to be designed in accordance with a predetermined rule, wherein when a signal name of a clock signal is input, the circuit name is determined based on the clock signal of the signal name. Searching means for searching for a description of an operating sequence cell; determining whether a signal name of a signal input asynchronously is described in the description of the sequential cell searched by the searching means, Is described, it is determined whether or not the description of the sequential cell is described in the signal name so as to be configured by two or more stages of connections operating in synchronization with the clock signal. If it is determined that the description does not include a configuration including two or more connections that operate in synchronization with the clock signal, a determination unit that outputs a warning signal; and a warning signal is transmitted from the determination unit. And a warning output means for issuing a warning. 3. When a warning signal is received from the determination means instead of the warning output means, the description of the sequential cell is described as a two-stage connection which operates in synchronization with the clock signal. 3. The circuit design apparatus according to claim 2, further comprising description changing means for rewriting the information and outputting the fact. 4. When a signal name of a clock signal is input,
A description of the sequence cell operating based on the clock signal of the signal name is searched, and it is determined whether the signal name of the signal input asynchronously is described with respect to the searched description of the sequence cell, If the signal name is described, it is determined whether or not a sequence cell is described for the signal name so as to be configured with two or more stages of connections operating in synchronization with the clock signal, Operates in synchronization with a clock signal 2
A recording medium that records a circuit design program that causes a computer to output a warning when it is determined that the description does not include a connection of more than two stages. 5. An operating circuit which operates in synchronization with the clock signal.
If it is determined that the description is not made up of connections of stages or more, instead of outputting a warning, the description of the sequential cell is made up of two stages of connections operating in synchronization with the clock signal. 5. The recording medium according to claim 4, wherein a circuit design program for causing a computer to rewrite the description as described and output the fact is recorded.