JPH0583885B2 - - Google Patents

Description

[Detailed description of the invention]

TECHNICAL FIELD The present invention relates to an image processing device useful for, for example, a focus detection device of a camera, which processes an image signal of an image sensor having a charge accumulation section and a charge transfer section for outputting the accumulated charges. Prior Art Conventionally, as the above-mentioned camera focus detection device, one using a CCD (Charge Coupled Device) as a self-scanning image sensor is known, and a positive pulse called an integral clear pulse is input to the CCD. Then, each photodiode that makes up the CCD image sensor array is once charged to the power supply voltage level, and then discharged when the integrated clear pulse disappears (hereinafter, this is considered to be the accumulation of negative charge and the charge accumulation ). After this, a positive pulse called a shift pulse is applied.
When input to the CCD, the charge accumulated in each photodiode between the disappearance of the integral clear pulse and the input of the shift pulse is transferred to the corresponding cell of the CCD shift register, and the transfer clock pulse is input to this CCD shift register. The accumulated charges are sequentially transferred to the image signal output circuit each time the image signal is output. This image signal output circuit sequentially outputs the accumulated charges transferred from the CCD shift register as voltage signals, and the voltage signals output one after another represent the light intensity distribution on the image sensor array, that is, the image formed thereon. This shows the intensity distribution of The voltage signal output by this image signal output circuit is converted into a digital signal by an A/D converter, and then processed and calculated by, for example, a microcomputer according to a predetermined program, and as a result, the focus adjustment state of the photographing lens is determined. is determined. Incidentally, conventionally, charge accumulation in each photodiode has generally been configured to start after the previous focus detection operation is completed, that is, after the signal processing operation by the above-mentioned microcomputer is completed. That is, the next integral clear pulse is generated at the time when the processing operation is completed. However, the charge accumulation speed of each photodiode changes depending on the brightness of the subject, and when the brightness of the subject becomes low, it is necessary to continue charge accumulation for a relatively long time, so the timing of shift pulse generation must be controlled according to the brightness of the subject. do. Therefore, when the subject brightness is low, the charge accumulation time becomes longer and the time required for one focus detection operation becomes longer, and the number of focus detection operations that can be performed within a certain period of time becomes smaller. Now, when focus detection is performed continuously and the focus is adjusted by driving the photographing lens based on the focus detection results each time, the more times the focus detection operation is performed within a certain period of time, the shorter the time required for the photographing lens to be adjusted. Therefore, if the charge accumulation in each photodiode was started at the end of the previous focus detection operation, it would take time for the photographic lens to focus when the subject brightness is low. This results in a missed photo opportunity. Purpose It is an object of the present invention to provide an image processing device in which the time required from the start of charge accumulation to the end of image signal processing is relatively short. SUMMARY In order to achieve the above object, the present invention is based on the accumulated charge output from a self-scanning image sensor that has a charge accumulation section and a charge output section that outputs the accumulated charge to an image signal output circuit in the form of an output signal. Obtaining an image signal by the above image signal output circuit,
An image processing device that processes and calculates an image signal using a processing circuit, comprising an integral clear pulse generating means for generating an integral clear pulse for wiping out the accumulated charge in the charge storage section, and an integral clear pulse that is incident on the image sensor after the integral clear pulse disappears. a termination signal output circuit that outputs a termination signal for terminating the charge accumulation operation when the amount of charge accumulated in the charge accumulation section reaches a predetermined value according to the light intensity; and a termination signal output circuit that outputs a termination signal for terminating the charge accumulation operation; Output signal generating means for generating an output signal for outputting the charge subsequently accumulated to the image signal output circuit; and an output signal generating means for inhibiting the generation of the next output signal by the output signal generating means immediately after generation of the output signal. inhibiting means; integral clear pulse generation control means for causing the integral clear pulse generating means to generate the next integral clear pulse in response to the generation of the output signal; If no signal is output, the generation of the next output signal is disabled after the calculation process is completed, and if the above-mentioned end signal is output, an integral clear pulse is generated again at the end of the process calculation, and the next output signal is inhibited. and an output signal control means for disabling the generation of the next output signal. Embodiment Next, an embodiment of the present invention will be described with reference to FIGS. 1 to 11. First, in FIG. 1 showing the overall circuit of this embodiment, numeral 1 indicates a self-scanning image sensor such as a CCD, an image signal output circuit, a light receiving element for brightness monitoring, a brightness monitoring circuit, as will be described later. and a reference signal generation circuit; 10 is a transfer clock pulse generation block; 20 is a circuit block for forming, based on the signal from the photoelectric conversion block 1, a digital signal that is the basis for determining the focus adjustment state of the photographing lens; , 30
is a microcomputer that determines the focusing state of the photographing lens based on the digital signal from the circuit block 20, and also controls each circuit block. Further, 40 controls the amplification factor of the amplifier in the circuit block 20 based on the output of the brightness monitor circuit in the photoelectric conversion block 1, and controls the charge accumulation time (optical) of the self-scanning image sensor in the photoelectric conversion block 1. AN1 and AN2 are AND circuits that together with an OR circuit OR1 form a gate means, and DF1 generates a reset pulse that resets flip-flops (FF0) (FF1) to (FF6), which will be described later. A D flip-flop, DF2, is a D flip-flop that generates a shift pulse to transfer the charge accumulated in the charge storage section to the transfer section in the image sensor.
CL1 is a clock circuit that generates a reference clock pulse, and (FF0) is an R-S flip-flop. Figure 2 shows the above-mentioned photoelectric conversion block 1, consisting of photodiode arrays (P1) (P2) (P3)...
The self-scanning image sensor described above is composed of the image sensor array PA consisting of (Pn-2) (Pn-1) (Pn), the integral clear gate ICG, the shift gate SG, and the CCD shift register SR. Here, the CCD shift register which is the transfer part
The number of cells in SR is three more than the number of photodiodes (pixels) in image sensor array PA, which is a charge storage section. Cells R1, R2, and R3 are for blank feeding, which will be described later, and Diodes P1, P2, P3...Pn-2,
The accumulated charges of Pn-1, Pn are cells R4, R5, R6,
...Transferred to Rn+1, Rn+2, Rn+3. As shown in FIG. 3, each photodiode consists of a pair of diodes D1, D2 and FETQ10 connected in parallel to each other via a switch S corresponding to an integral clear gate ICG with respect to the power supply (+V).
One diode D1 is installed to receive light. The FETQ10 is provided so that the voltage across the diode D1 can be kept substantially constant and the capacitance of the diode D1 can be ignored, and its gate is grounded. Now, when switch S is closed, charge is accumulated between the anode and cathode of diode D2, and the anode voltage becomes equal to the power supply voltage.
Then, when the switch S is opened next, the diode D2 is switched to FETQ by the photocurrent of the diode D1.
10, whose anode voltage drops over time. In other words, this can be thought of as negative charge being accumulated on the cathode of diode D2 at a rate that depends on the intensity of the light incident on diode D1, and therefore each photodiode accumulates negative charge at a rate that depends on the intensity of the incident light. , will be explained assuming that charge is accumulated. The above switch S1 is actually an integral clear gate.
It consists of a semiconductor analog switch that is turned on by the integral clear pulse input to the ICG and turned off when the pulse disappears. shift gate
SG are photodiodes P1, P2, P3...Pn-
2, Pn-1, Pn's accumulated charge is transferred to cell R4 of CCD shift register SR in response to a shift pulse described later.
Transfer in parallel to R5, R6...Rn+1, Rn+2, Rn+3. Photodiodes P1, P2, P3
...The charge accumulation of Pn-2, Pn-1, and Pn is completed by inputting a shift pulse to the shift gate SG.
Furthermore, every time the transfer clock pulses (φ1) (φ2) (described later) are input, the CCD shift register SR sequentially outputs one cell's worth of accumulated charge to the image signal output circuit (described later) at the falling edge of the transfer clock pulse (φ1). .
Furthermore, from one end of the image sensor array PA, a predetermined number (10) of photodiodes P1, P
2...P10 is covered with an aluminum film and is used for dark output correction as described later. Second
T8 and T9 in the figure are the image sensor and circuit described above.
This is a power supply terminal for supplying power (+V) to MC, RS, and VS. Incidentally, the position at which the image sensor array PA is placed in the camera differs depending on the focus detection method. FIG. 4 shows an example of a focus detection optical system to which the present invention can be applied.
TL is a photographic lens, CL is a condenser lens, L
1. L2 is a pair of re-imaging lenses arranged symmetrically with respect to the principal optical axis l of the photographic lens TL, M is a mask, and F is a photographic lens equivalent to the camera's film surface.
This is the planned imaging plane of TL. According to this optical system,
When the photographing lens TL forms a subject image on or before and after the planned imaging plane F, the re-imaging lens L
1, L2 re-forms the subject image as the first and second images on the image sensor array PA, but the first and second images on the image sensor array PA are
The distance between the images changes depending on the focus adjustment state of the photographing lens TL, that is, the shift state of the subject image formed thereby with respect to the intended image formation plane F. Therefore, by detecting the interval between the first and second images based on the output of each pixel of the image sensor array DA, it is possible to determine the amount and direction of focus adjustment that indicate the focus adjustment state of the photographing lens TL. The output processing method will be described later. In addition, in Fig. 4, the image sensor array
PA is arranged at or near a position conjugate with the intended image plane F with respect to the condenser lens CL and the pair of re-imaging lenses L1 and L2. Again in FIG. 2, MP is a photodiode which is a light receiving element for brightness monitoring, MC is a brightness monitoring circuit, RS is a reference signal generation circuit, and VS is an image signal output circuit. Brightness monitor circuit MC
It consists of FETQ1, Q2, Q3 and capacitor C1. FETQ1 has its gate connected to the integral clear gate 3 of the image sensor, and is made conductive by the integral clear pulse that passes through the integral clear gate ICG, thereby causing capacitor C1
is charged to the level of the power supply voltage (+V).
The connection point (J1) between FETQ1 and capacitor C1 is
It is connected to the anode of photodiode MP via EFTQ12, and to the gate of FETQ2. The gate of FETQ12 is grounded, and it is provided so that the voltage across the photodiode MP can be kept substantially constant and the influence of its capacitance can be ignored. FETQ2 and Q3 are connected in series to the power supply, forming a buffer with low output impedance and high input impedance.FETQ3 is used as a source follower, so it can be pulled out from the connection point of FETQ2 and Q3. A voltage (Vm) corresponding to the potential of the connection point (J1) is output from the output terminal T1. When the above integral clear pulse disappears, FET Q1 becomes non-conductive, capacitor C1 is discharged by the photocurrent of photodiode MP, and terminal T1 is accordingly discharged.
output voltage drops. Figure 5 shows the temporal change in the output voltage of this terminal T1, and (l ₁ )
(l ₂ )(l ₃ )(l ₄ )(l ₅ ) shows that the speed of voltage drop changes depending on the brightness. The rising edge indicated by RN represents induced noise due to the integral clear pulse. The reference voltage generation circuit RS consists of FETQ4, Q5, Q
6 and capacitor C2, these have the same characteristics as FETQ1, Q2, Q3 and capacitor C1 described above, and their circuit connection is also similar to FETQ1, Q2, Q3 in the brightness monitor circuit MC.
and the circuit connection of capacitor C1. However, only the gate of FETQ5 is connected to the connection point (J2) between FETQ4 and capacitor C2, and therefore, like FETQ2 and Q3, it forms a buffer with low output impedance and high input impedance. The voltage signal output from the output terminal T2 drawn from the connection point between FETs Q5 and Q6 remains constant as shown in FIG. 5 even after the integral clear pulse disappears. In other words, the connection point (J1) immediately after the disappearance of the integral clear pulse (T0)
(J2) potential is FETQ1, Q2, Q as mentioned above.
3 and capacitor C1, FETQ4, Q5, Q6, and capacitor C2 have the same characteristics, so they are equal, so the voltage signal output from terminal T2 is used to find the amount of drop in the voltage signal output from terminal T1. It can be used as a reference voltage (Vref). Image signal output circuit VS is FETQ7, Q8, Q
9 and capacitor C3, preferably also FETs Q1, Q2, Q3 and capacitor C3.
Use the same characteristics as 1. However, in the circuit connection, the transfer clock pulse (φ1) is applied to the gate of FETQ7,
Also, the connection point (J3) between FETQ7 and capacitor C3 is
FETQ8 gate and image sensor CCD
Connected to the transfer terminal of shift register SR.
Therefore, each time one transfer pulse (φ1) is input, FET Q7 becomes conductive, capacitor C3 is charged to the level of the power supply voltage (+V), and the image signal output circuit VS is reset. CCD shift register transferred by pulse (φ1)
It is repeatedly discharged according to the accumulated charge of SR, and eventually,
From the output terminal T3 drawn out from the connection point of FETQ8 and Q9, which constitute a buffer with low output impedance and high input impedance, the output corresponding to the accumulated charge of each photodiode, which is a pixel of the image sensor, is sequentially converted into a voltage signal ( Vos), and together they form an image signal. In addition, C1 in the above circuits MC, RS, VS,
Although C2 and C3 have been described as capacitors for convenience of explanation, they can be replaced with PN junctions of diodes, and when these circuits are integrated, they are each manufactured as diodes. Further, a photodiode MP, which is a light receiving element for monitoring, is arranged near the image sensor array PA so as to receive a portion of the light that has passed through the photographic lens. Next, referring again to FIG. 1, an example of the circuit configuration of the transfer clock pulse generation block 10 that generates the transfer clock pulses (.phi.1) (.phi.2) will be described.
(FF1) (FF2)...(FF6) are flip-flop circuits that form a frequency dividing circuit, and the T input of the first stage flip-flop (FF1) has a clock circuit CL1.
A clock pulse (period: 2 μs) is input from Flip Flop (FF3) (FF4) (FF5)
The Q outputs of (FF6) are respectively input to an OR circuit OR2, and the output of the OR circuit OR2 is input to one input of an AND circuit AN4. and circuit
The other input of AN4 is connected to the terminal T22 of the microcomputer 30 via the inverter IN1, and when the terminal T22 outputs a "0" signal, the AND circuit AN4 outputs an OR circuit.
A “1” signal of OR2 is output. On the other hand, one input of the AND circuit AN5 is the clock circuit CL2.
, and the other input is connected to the above-mentioned terminal T22. Therefore, when the above-mentioned terminal T22 outputs a signal of "1", the clock circuit CL2
Outputs clock pulses from Here, the period of the clock pulse output from the clock circuit CL2 is set to be several tens of times shorter than the period of the output Q6 of the flip-flop FF6, which is obtained by dividing the clock pulse output from the clock circuit CL1. The OR circuit OR3 outputs a signal of "1" to the CCD shift register SR in the photoelectric conversion block 1 as a transfer clock pulse (.phi.2) when the output signal of either the AND circuits AN4 or AN5 is "1". or,
An inverter IN2 is connected to the OR circuit OR3, and this inverter IN2 transfers a signal with an opposite phase to (φ2) as a clock pulse (φ1) to the CCD shift register SR in the photoelectric conversion block 1 and the image signal output circuit VS. Output (see Figure 2)
Note that the "1" signal from the terminal T22 of the microcomputer 30 is a signal for causing the image sensor to perform an initializing operation. FIG. 6 shows the brightness determination circuit 40 and circuit block 2.
An example of 0 is shown. In this figure, T10, T1
1 and T12 are terminals T1, T2, and T3 in Fig. 2, respectively.
It is a terminal connected to terminals T13, T15,
A latch pulse, a sample designation pulse, and a sample designation reset pulse are input to T16 from the microcomputer 30 via the data bus DB1, respectively, as will be described later. Further, the terminal T14 is connected to one input of the AND circuit AN2 shown in FIG. First, the brightness determination circuit 40 will be explained. This circuit includes comparators AC1, AC2,
Equipped with AC3 and AC4. The inverting inputs of these comparators are respectively connected to terminal T10 via buffer B1. On the other hand, these comparators AC1,
The non-inverting input of AC2, AC3, AC4 is resistor R1
and constant current source I1 (J4), resistor R2 and constant current source I2 (J5), resistor R3 and constant current source I
3 connection point (J6) and the connection point (J7) of resistor R4 and constant current source I4.
2, R3, R4 are connected to terminal T1 via buffer B2.
Connected to 1. With this kind of circuit connection, terminal T1 is connected to connection points (J4) (J5) (J6) (J7).
1 from the voltage (Vref) of the reference voltage generating circuit RS mentioned above, which is applied to the resistors R1, R2, R3, R, respectively.
The voltage after subtracting the voltage drop at 4 is generated,
By selecting the resistance values of resistors R1, R2, R3, and R4 and the current values of constant current sources I1, I2, I3, and I4, the output voltage (Vm) of the above-mentioned brightness monitor circuit MC input to terminal T10 can be determined. Comparators AC1, AC2, AC3, AC4 depending on the degree of voltage drop.
The outputs of are sequentially inverted from "0" to "1". D.F.
3, DF4 and DF5 have D inputs as comparators AC1 and DF5, respectively.
This is a D flip-flop connected to the outputs of AC2 and AC3, and the latch pulse from the microcomputer 30 in Fig. 1 is input to these CP inputs after a predetermined time (100 msec) from the fall of the integral clear pulse via terminal T13. Alternatively, if a shift pulse is generated before the predetermined time has elapsed, it is input in synchronization with the shift pulse. Then, when the latch pulse is input, the D flip-flop DF
3, DF4, DF5 are the immediately preceding comparators AC1, AC
The outputs of 2 and AC3 are output to the Q output, and the inverted output is output from the output. AN6 is an AND circuit with one input connected to the Q output of the D flip-flop DF3 and the other input connected to the output of the D flip-flop DF4, and AN7 has one input connected to the Q output of the D flip-flop DF3.
An AND circuit is connected to the output of the flip-flop DF4 and the other input is connected to the output of the D flip-flop DF5, and the AND circuit AN6,
AN7 output (b) (c), D flip-flop
The output (a) of DF3, the Q output (d) of DF5, and the output (e) of comparator AC4 are sent to the brightness determination circuit 40.
The output is That is, their output becomes a signal indicating the brightness level detected by the monitor light receiving element PM. To explain this _in more detail with reference to FIG _{. 5 ,} in FIG. 100ms) if the voltage drop that occurs up to the elapsed time (t3) is less than 0.35V, from 0.35V to less than 0.7V, from 0.7V to less than 1.4V, from 1.4V to 2.8V
It shows the change in the output voltage of the brightness monitor circuit MC when the voltage is less _than
It shows the change in the output voltage of the same monitor circuit MC when a voltage drop of 2.8V occurs at the time (t2) before the elapse of time. As mentioned above, which voltage drop (l ₁ ) (l ₂ ) (l ₃ ) (l ₄ ) (l ₅ ) will occur depends on the monitor light receiving element.
It depends on the magnitude of the DM photocurrent, and the output voltage change of the brightness monitor circuit MC is (l ₁ ) (l ₂ ) (l ₃ )
When it becomes like (l ₄ ), it is a case of low luminance, and when it becomes like (l ₅ ), it is a case of high luminance. Now, the voltages at terminals J4, J5, J6, and J7 are respectively at terminal T11.
0.35V, 0.7V, 1.4V, and 2.8V, respectively, than the output voltage (Vref) of the reference voltage generation circuit RS input to
The above-mentioned resistors R1, R2, R3,
Resistance value of R4 and constant current sources I1, I2, I3, I
When the current value of 4 is set, the Q outputs of D flip-flops DF3, DF4, and DF5 corresponding to (l ₁ )(l ₂ )(l ₃ )(l ₄ )(l ₅ ) after the latch pulse is generated,
Q output and output of brightness monitor circuit MC (a)
(b), (c), (d), and (e) are as shown in Table 1 below.

[Table] In the case of (l ₅ ), the output of comparator AC4 (d)
changes from "0" to "1" at a time point (t2) before a predetermined time (100 msec) has elapsed from the time point at which the integral clear pulse disappears (t0). The remaining circuit in Figure 6 is circuit block 2 in Figure 1.
Configure 0. 22 is the output voltage (Vos) of the image signal output circuit VS input from the terminal T12 via the buffer B3, and the output voltage (Vos) input from the terminal T12 via the buffer B2.
This is a subtraction circuit that generates an output (V1) corresponding to the difference between the output voltage (Vref) of the reference signal generation circuit RS and the output voltage (Vref) inputted from the reference signal generation circuit RS. 24 is the peak value (V2) of the image signal corresponding to the accumulated charge of a predetermined number (10) of photodiodes P2 to P9 covered with an aluminum film in the image sensor array PA, excluding the diodes P2 and Q9 at both ends.
(lowest level pixel signal), latches it, and outputs it, thereby detecting the image sensor array that is not covered with aluminum film and receiving the above-mentioned first and second images. A so-called dark output correction signal V2 is formed for the pixel signal corresponding to the accumulated charge of the photodiode in PA. That is, the microcomputer 30 receives the transfer clock pulse (φ1).
When the accumulated charge is sequentially transferred from the CCD shift register SR to the image signal output circuit VS by (φ2),
At the same time as the transfer of accumulated charge in cell R5 starts, a sample designation pulse is sent to terminal T1 via data bus DB1.
Then, at the same time as the transfer of the accumulated charge in cell R12 is completed, a sample designation reset pulse is outputted to terminal T16 via data bus DB1. Therefore, the peak value detection circuit 24 takes in the image signals corresponding to the accumulated charges in the cells R5 to R12, in other words, the accumulated charges in the photodiodes P2 to P9, and detects the peak value thereof. 26 is the output signal (V1) of circuits 22 and 24
(V2), whose amplification factor is the output (a) and (b) of the brightness determination circuit 40 described above.
(c) An amplifier configured to be controlled by (d). In this amplifier, OP is an operational amplifier, and its input terminals f and g are input resistances R
5 and R6 to circuits 22 and 24, respectively. R7 to R14 are resistors provided for setting the amplification factor of the operational amplifier OP, and R5,
The resistance values of R6, R7, R8, R11, and R12 are r
When R9 and R13 are the resistance values of 2r, R1
0, R14 has a resistance value of 4r. AS1 to AS8 are analog switches, of which AS
1 to AS4 selectively enable the resistors R7 to R10 according to the outputs (a), (b), (c), and (d) to determine the feedback resistance value of the operational amplifier OP, whereas AS5
AS8 to AS8 selectively enable resistors R11 to R14 according to the outputs (a), (b), (c), and (d) to set the bias resistance value of the amplifier OP. That is,
The states of the analog switches and the enabled resistances when each of the above voltage drops (l ₁ ) (l ₂ ) (l ₃ ) (l ₄ ) (l ₅ ) occur are as shown in Table 2 below. Become.

[Table] In the above table, A is the amplification factor of the operational amplifier OP,
The output voltage of this amplifier OP is Vout=E+(V2−
V1)×A, which is input to an A/D converter (ADC). However, E is the voltage of the constant voltage source (E) and is appropriately set according to the input level range of the A/D converter (ADC). Then, an A/D converter (ADC) corresponding to each pixel signal
Each output is input to the terminal T22 of the microcomputer shown in FIG. 1 via the data bus DB1, and the focus adjustment state of the photographic lens is detected by digital calculation based on a predetermined program. In this way, the amplifier 26 in FIG.
Since the amplification factor is changed according to the output of 0 and a signal suitable for signal processing by an A/D converter (ADC) is output, it is possible to adjust the focal state of the photographing lens over a wide brightness range. Referring to FIG. 1 again, the terminal T17 of the microcomputer 30 is an output terminal for an integral clear pulse. Also, the microcomputer 30
A signal of "1" is output from terminal T19 when generation of shift pulses is permitted, and generation of shift pulses is prohibited during transfer of accumulated charge from image sensor array PA to CCD shift register SR as described later. A signal “0” is output. Further, from the terminal T18 of the microcomputer 30, when the above-mentioned predetermined time has elapsed from the point of disappearance of the integral clear pulse (t0), or if a shift pulse is generated before the elapse of the predetermined time, a shift pulse is generated in response to the occurrence of the shift pulse. A signal of "1" is output.
This signal becomes a latch pulse for the brightness determination circuit 40. The integral clear pulse output from the terminal T17 is passed through the terminal T6 to the integral clear gate ICG of the image sensor in the photoelectric conversion block 1.
On the other hand, the flip-flop (FF0) is set, its Q output is set to "1", and the AND circuit AN1 is opened. Furthermore, when the flip-flop (FF0) is set and a signal of "1" is output from the terminal T19 to permit generation of a shift pulse, the AND circuit AN2 is also opened. From the output terminal T14 of the brightness determination circuit 40, only when the subject brightness is high as shown in (l ₅ ) in FIG. The time before (t2)
A signal (e) of "1" is output. On the other hand, when the subject brightness is low, as shown in (l ₁ ) (l ₂ ) (l ₃ ) (l ₄ ) in FIG. ) becomes "1", and the output (e) of the output terminal T15 of the brightness determination circuit 40 is kept at "0". Therefore, if the subject brightness is high, the AND circuit AN
The output of 2 becomes “1” at the time (t2), and if the subject brightness is low, the AND circuit AN outputs at the time (t3).
1 output becomes “1”, and either one “1”
The output of is inputted to the D input of the D flip-flop DF1 via the OR circuit OR1. The CK (clock) input of this D flip-flop receives a reference clock pulse (period: 2 μs) from clock circuit CL1.
is input, as shown in Figure 6, D
Immediately after a “1” signal is input to the input, the D flip-flop is activated at the falling edge of the reference clock pulse.
The Q output of DF1 becomes "1", the flip-flop (FF0) is reset, the open AND circuit AN1 or AN2 is closed, and the flip-flops (FF1) to (FF6) in the transfer clock pulse generation block 10 are reset. All of those Q outputs Q1 to Q6 become "0". When the AND circuit AN1 or AN2 is closed in this way, the Q output of the D flip-flop DF1 returns to "0" at the next falling edge of the reference clock pulse, and eventually a positive pulse with a time width of 2 μs is generated from the Q output. will be output. This positive pulse is the reset pulse. On the other hand, the Q output of the D flip-flop DF2 becomes "1" at the fall of the reference clock pulse from the clock circuit CL1 immediately after the Q output of the D flip-flop DF1 becomes "1", and the Q output of the D flip-flop DF1 becomes "0". ”
The Q output returns to "0" at the falling edge of the reference pulse of the same clock circuit immediately after returning to "0". Therefore, at the Q output of the D flip-flop DF2, a positive pulse having a time width of 2 .mu.seconds rises in synchronization with the falling edge of the reset pulse, and this is a shift pulse.
This shift pulse is input to the terminal T21 of the microcomputer 30, and is also input to the shift gate SG of the image sensor in the photoelectric conversion block 1 via the terminal T7. The above is an explanation of the overall circuit configuration in Figure 1 and the circuit blocks that make up it. Next, before explaining the overall operation, we will refer to Figures 7 and 8 to explain the signal flow in each part. Let me explain. Figure 7 shows the outputs of the flip-flops (FF1) to (FF6) immediately after being reset by the reset pulse generated at the Q output of the D flip-flop DF1, the transfer pulse (φ1), and the output of the D flip-flop DF1.
It shows the relationship between shift pulses that are the Q output of DF2. As mentioned above, the flip-flops (FF1) to (FF6) are reset at the rising edge of the reset pulse, and their Q outputs (Q1) to (Q6) all become "0". As a result, the OR circuit OR2
Since the output of is "0", the transfer clock pulse (.phi.2) falls to "0", and conversely, the transfer clock pulse (.phi.1) rises to "1". Then, after 2 .mu. seconds have elapsed, the reset pulse falls, and at the same time, the shift pulse rises to "1", and this shift pulse falls to "0" after another 2 .mu. seconds. Next, the output of the OR circuit OR2 becomes "1" when the Q output Q3 of the flip-flop (FF3) becomes "1", which means that the reset pulse becomes "0".
This is 8 microseconds after the clock falls, and in the end, the transfer clock pulse (φ1) is kept at "1" for 10 microseconds. The shift pulse is generated and disappears while the transfer clock pulse (φ1) is in the "1" state. In this way, the transfer clock pulse generation block 10 is reset immediately after time (t2) or (t3) and the shift pulse is generated while the newly output transfer clock pulse (φ1) continues. Photodiode arrays P1, P2, P3...Pn- in image sensor array PA
This is to avoid unnecessarily delaying the end point of charge accumulation (integration) of 2, Pn-1, and Pn. If a shift pulse is generated in synchronization with the first transfer clock pulse (φ1) that occurs after time (t2) or (t3), then (t2) or (t3)
From the point in time, the photodiodes P1, P2, P3...
Charge accumulation of Pn-2, Pn-1, and Pn may be performed unnecessarily, and if the subject is extremely bright, the charge accumulation may become saturated and a correct image signal may not be obtained. Furthermore, since the timing at which the shift pulse is generated after time (t2) or (t3) is not necessarily constant, a problem may arise in which the image signal level is not constant. In contrast,
In FIG. 7, a shift pulse always occurs within two cycles (4 μsec) of the reference clock pulse from time (t2) or (t3), so there is no such possibility. In addition, as shown in FIG. 7, the next transfer clock pulse (φ1) is outputted from Q3, Q4, Q5, Q6.
120 microseconds after all become "0", it becomes "1", and this state is maintained for 8 microseconds. All transfer clock pulses after this transfer clock pulse are in the "1" state for 8 microseconds and then in the "0" state for 120 microseconds. Therefore, the period of the transfer clock pulse (φ1) is 128 μsec, its duty cycle is not 1/2, and the duration ratio of the “1” state and the “0” state is 1/15. If you do this, 1 of the CCD shift register SR
Since the transfer of the accumulated charge from the cell to the image signal output circuit VS is performed at the falling edge of the transfer clock pulse, it is necessary to ensure sufficient A/D time for signal processing, especially the A/D converter (ADC). Since it is possible to use an inexpensive A/D converter with a low conversion speed as the ADC, it is possible to reduce the cost of a camera using this A/D converter. FIG. 8 shows the outputs of the image signal output circuit VS and the amplifier 26 after generation of the shift pulse of the image sensor, together with the transfer clock pulses (.phi.1) (.phi.2) and the output of the reference signal generation circuit RS. In the case of Figure 7, when the shift pulse occurs, the CCD
It is assumed that the shift register SR is in an empty state. To create this empty state, photodiodes P1, P2, P3...Pn-2, Pn-1,
Instead of transferring the accumulated charge of Pn to the CCD shift register SR, it is sufficient to apply transfer clock pulses (φ1) (φ2) as many as the number of cells of the CCD shift register SR to that register. For example, that register SR
When the number of cells in the register is 100, if 100 transfer clock pulses (φ1) and (φ2) are applied, all the accumulated charges in the register will be discharged. However, in reality, when the image sensor is first started up, the accumulated charge in the CCD shift register SR is not completely discharged in one charge discharge operation.
In this case, a completely empty state is usually created by repeating the evacuation operation several times. This series of operations is called the initialization operation of the image sensor. In FIG. 8, photodiodes P1, P2, P3...Pn-2,
The accumulated charge of Pn-1 and Pn is the CCD shift register SR
The charges accumulated in the cell R1 are transferred to the image signal output circuit VS at the fall of the first transfer clock pulse (φ1). As a result, the image signal output circuit VS outputs an output (Vos1) corresponding to the accumulated charge of the cell R1 to the terminal T3. From then on, each time the transfer clock pulse (φ1) falls, the cell R
Outputs (Vos2) (Vos3)...(Vos(n+3)) corresponding to the accumulated charges of 2, R3...Rn+3 are sequentially output from the image signal output circuit VS. Among these outputs, (Vos1), (Vos2), and (Vos3) are the outputs corresponding to the accumulated charges of the empty feed cells R1, R2, and R3, and (Vos4) to (Vos13) are the outputs corresponding to the aluminum-coated photo cells. Diodes P1 to P10,
That is, it is a dark output corresponding to the accumulated charges of cells R4 to R13. Between these two types of output,
As shown by ΔS, there is a difference corresponding to the amount of accumulated charge based on the dark current generated in the photodiodes P1 to P10. Arithmetic circuit 2 shown as (V1)
The output of 2 is V1=Vref− for each (Vos)
It is obtained by calculating Vos, and among the outputs of the arithmetic circuit 22 corresponding to the dark outputs (Vos4) to (Vos13), those corresponding to (Vos5) to (Vos12) are the peak value detection circuits described above. 24. Then, the one having the maximum value among them is outputted from the peak value detection circuit 24 as (V2). In Figure 8, the dashed line indicates this (V2), so V' = V1 - V2 is Vout
It corresponds to the output of the amplifier 26 expressed as =E+(V1-V2)×A. Next, referring to the flowchart in FIG.
The operation of the microcomputer 30 shown in the figure and the effect of the entire circuit will be explained. First, when a start signal is given to the microcomputer 30 by operating a switch (not shown), the microcomputer 30 is started at step #1.
outputs a signal of "1" to terminal T22 to initialize the image sensor. That is, fast-cycle clock pulses from clock circuit CL2 as transfer clock pulses (φ1) (φ2) are sent to the CCD shift register via terminals T4 and T5.
Input into SR. At this time, the signal "0" that prohibits the generation of shift pulses is output from terminal T19, and no shift pulses are generated.
The CCD shift register SR does not receive accumulated charges from the image sensor array PA, but sequentially discharges its own accumulated charges. (Alternatively, without prohibiting shift pulse generation, an integral clear pulse is generated in the same way as normal CCD driving, and then a shift pulse is generated immediately so that the accumulated charge can be ignored.
Next, the accumulated charge in the CCD shift register may be discharged by the transfer clock pulse. ) This ejection action is repeated several times as described above, thereby
CCD shift register SR becomes empty. here,
One discharge operation is completed by applying transfer clock pulses (φ1) (φ2) equal to the number of cells in the CCD shift register SR. After the predetermined time period that guarantees the discharge operation several times has elapsed, the microcomputer 30 sets the output of the terminal T22 to "0" and changes the state of "1" formed based on the reference clock pulse from the clock circuit CL1 to "0". ``A pulse with a state duration ratio of 1/15 is set as a transfer clock pulse (φ1), and a pulse with the opposite phase is input as a transfer clock pulse (φ2) to the CCD shift register SR. Next, in step #2, the microcomputer 30 outputs a signal of "1" from the terminal T19 to permit generation of a shift pulse, thereby opening the AND circuit AN2. Then, when an integral clear pulse is output from the terminal T17 in step #3, the flip-flop (FF0) is set and the AND circuit AN1 is also opened. At the same time, the integral clear pulse is input to the integral clear gate ICG, and the image sensor array
While the accumulated charge in each photodiode of PA is cleared, FETQ1 and Q4 are turned on and capacitors C1 and C2 are charged to the level of the power supply voltage. This integral clear pulse disappears at the time (t0), and each photodiode of the image sensor array PA starts accumulating charge, and
As shown in FIG. 5, the output voltage (Vm) of the brightness monitor circuit MC begins to drop at a speed corresponding to the subject brightness detected by the monitor light receiving element PM. or,
At the same time as the integral clear pulse disappears, the microcomputer 30 sets an internal programmable reset counter in step #4, and this counter starts counting a predetermined time of 100 msec. Next, the microcomputer 30 determines the output voltage (Vm) of the brightness monitor circuit MC in step #5.
Check whether the voltage drop reaches 2.8V at terminal T.
Output (e) of the brightness determination circuit 40 input to 20
When it is determined that the output (e) is "1" and the case is shown as (l5) in FIG. 5, the process moves to step #9 and the output of the terminal T19 is set to "0". and prohibits the generation of shift pulses.
However, when the output (c) becomes "1", as shown in FIG. 6, a reset pulse is issued from the D flip-flop DF1 and a shift pulse is issued from the D flip-flop DF2 in a very short time.
The flip-flop (FF0) is reset by the reset pulse, and the AND circuits AN1 and AN
2 is closed, the shift pulse that is prohibited from being generated in step #9 is a shift pulse that may be newly generated after step #10, which will be described later. On the other hand, in step #5, the output (e) is "0" and one of the cases shown as (l ₁ ) (l ₂ ) (l ₃ ) (l ₄ ) in FIG. When the determination is made, the microcomputer 30 sets "1" from the contents of the programmable reset counter described above in step #6.
Then, in step #7, it is determined whether the contents of the counter have become "0". If the content has not become "0", the process returns to step #5, passes through step #6, and then returns to step #7 to determine whether the content of the programmable reset counter has become "0". Determine whether it has become. Here, if the time required for step cycles #5, #6, and #7 is ts, then ts
×N=100 msec. Therefore, if steps #5, #6, and #7 are repeated N times, the content of the programmable reset counter becomes "0". That is, when 100 milliseconds have elapsed since this counter was set in step #4, the microcomputer 30 outputs a signal of "1" from terminal T18 in step #8, and this signal passes through the AND circuits AN1 and OR1. It is input to the D input of the D flip-flop DF1 through the D flip-flop DF1. Therefore, a reset pulse is output from the D flip-flop DF1, the flip-flop (FF0) is reset, and the AND circuits AN1 and AN2 are closed, while a shift pulse is subsequently generated from the D flip-flop DF2. However, in this case, when further time passes and the amount of drop in the output voltage (Vm) of the brightness monitor circuit MC reaches 2.8V, the output (e) of the brightness determination circuit 40 becomes "1", and Since the determination is made in step #5, a signal of "0" is output from the terminal T19, which prohibits the generation of shift pulses thereafter. The shift pulse generated as described above is input to the terminal T21 of the microcomputer 30, and is also input to the shift gate SG via the terminal T7. This allows the image sensor array to be
The accumulated charge in each photodiode of PA is transferred to the corresponding cell of CCD shift register SR, and then the accumulated charge in each cell of that register SR is transferred to the image signal output circuit VS in sequence by transfer clock pulses (φ1) (φ2). be transferred. Then, image signals (Vos1) (Vos2)...(Vos(n+3)) are sequentially output from the output terminal T3 of the image signal output circuit VS, and Vout=E+(V1-V2) is output from the amplifier 26.
Signals represented by A are sequentially output. These signals are sequentially converted into digital signals by an A/D converter (ADC) and input to the microcomputer 30 via the data bus DB1. On the other hand, when the above-mentioned shift pulse is input to the terminal T21, the microcomputer 30 outputs an integral clear pulse from the terminal T17 in step #10. Therefore, the accumulated charge in each photodiode of the image sensor array PA is cleared, and charge accumulation in each photodiode is restarted at the same time as the integral clear pulse disappears. Of course, the output of the brightness monitor circuit MC also begins to fall at a speed corresponding to the subject brightness detected by the monitor light receiving element PM, as described above. That is, the second charge accumulation cycle is started, and the microcomputer 30 sets the internal programmable preset counter to count the number of cells in the CCD shift register SR at the same time as the integral clear pulse disappears. . This is step #11. The microcomputer 30 converts the digital signal corresponding to the accumulated charge in each cell into an A/D converter.
Receive it from the converter (ADC) and store it in the internal random access memory (step #12), and each time subtract 1 from the contents of the programmable preset counter (step #13).
It is determined in step #14 whether the content has become "0". The content of the programmable preset counter set in step #11 is “0”
When this happens, move on to the next step #15. In this step, the microcomputer 30 calculates the focus adjustment state of the photographing lens TL, that is, the amount and direction of defocus with respect to the expected focal plane F, by performing the following calculations, for example. That is, photodiodes P1, P2, P3...Pn-2, Pn-1,
Of the Pn minus P1 to P10, those included in the area where the first image is formed in FIG. 4 are referred to as the photodiodes of the reference section, and those included in the area where the second image is formed are referred to. The photodiodes of the reference part and the reference part are respectively A1, A2, ... Am, B1, B2, ... from one side of the image sensor array PA.
When Bm+k-1, the digital signals from the A/D converter (ADC) corresponding to the charges accumulated in them are (a1), (a2)...(am), (b1), respectively.
(b2)…(bm+k-1), then C1= _n 〓 ⁱ⁼¹ ｜ai−bi｜ C2= _n- 〓 ⁱ⁼¹ ｜ai−(bi+1)…｜ … Ck−1= _n 〓 ⁱ⁼¹ |ai−(bi+k−2)| Ck= _n 〓 ⁱ⁼¹ |ai−(bi+k−1)| demand. For example, if the value of C2 is the minimum, the photodiode A1 in the reference section,
The images formed on the photodiodes B2, B3, . . . , Bm, Bm+1 of the reference section most closely match the images formed on A2, . . . , Am. Therefore, in this case, the distance between the photodiodes A1 and B2 on the image sensor array PA is the same as the above-mentioned first and second photodiodes.
This is the interval between the images, and by comparing this with a predetermined interval between the first and second images at the time of focusing determined by the focus detection optical system, it is possible to calculate the amount of defocus and the direction of defocus of the photographic lens at that time. Note that the calculation method described here is just an example, and in order to more accurately determine the amount of defocus, the present applicant, for example, has
The calculation method proposed in this issue can be used. When the above calculation in step #15 is completed, the microcomputer 30 again operates the brightness determination circuit 40.
Based on the output (e) of the brightness monitor circuit
Voltage drop amount of MC output (Vm) is step #11
During the period from #15, it is determined in step #16 whether 2.8V has been reached. It is assumed that, for example, 50 msec is required to execute steps #11 to #15. If the output (e) is “1” and the voltage drop of the output (Vm) reaches 2.8V,
At step #17, apply the integral clear pulse again to terminal T.
17 to clear the charges accumulated in each photodiode of the image sensor array PA during the execution of steps #12 to #15, and cause them to start accumulating charges again. This is done because if the output (e) is "1" during the determination in step #16, there is a possibility that the charge accumulation in each photodiode of the image sensor array PA has already been saturated. . In this case, the microcomputer 30 sets the internal programmable preset counter to count 100 msec at step #17 at the same time as the integral clear pulse disappears, and then sets the internal programmable preset counter to count 100 msec at step #18.
outputs a "1" signal that allows generation of shift pulses. After this, the process returns to step #5 and repeats the above-described steps in sequence. On the other hand, if the output (e) is "0" at step #16 and the voltage drop of the output (Vm) has not reached 2.8V, the microcomputer 30 will set the above programmable preset at step #20. Set the counter to count 50ms, then proceed to step #19 above. At this time,
Setting the counter to count 50ms means that approximately 50m has already passed since the integral clear pulse output in step #10 disappears, as described above.
This is because if the remaining 50 msec is counted by the counter, each photodiode of the image sensor array PA will be allowed to accumulate charge for a total of 100 msec. That is,
In this case, step cycles #5, #7, and #8 are repeated a maximum of 50/ts times. Of course, if the programmable preset counter can be used exclusively for other purposes, the programmable preset counter can be set to count 100ms after step #10 is completed. Step #20 is no longer necessary. The operation of the microcomputer 30 and the effect of the entire circuit have been explained above with reference to FIG. 9. As can be understood from the above, in this embodiment, the image sensor is The generation of new shift pulses is prohibited from the time the transfer of the accumulated charges of the photodiodes of the array PA begins until the calculation of the amount of defocus and the direction of defocus is completed in the microcomputer 30. Each photodiode starts accumulating charges immediately after the previous shift pulse is generated, without waiting for the completion of its calculation. The reason for this is as follows. That is, when the photographic lens is driven and its focus adjusted based on focus detection, the photographic lens can be brought into focus in a shorter time as the number of focus detection operations performed within a certain period of time increases. Therefore, 1
Considering the time required for the focus detection operation, it is determined that the charge accumulation (photocurrent integration) time Ti in the CCD image sensor array PA and the accumulated charge in the image sensor array are transferred to the CCD shift register.
The sum (Ti + Td) of the time Td (this is called data processing time for convenience) required to transfer the image signal to the image signal output circuit VS via SR, and then perform signal processing and calculation of the amount of defocus and the direction of defocus.
When performing focus detection operations repeatedly and continuously, if the next detection operation is performed after the previous detection operation is completed, the time required to perform n detection operations is (Ti + Td) ×n. However, the speed of charge accumulation (photocurrent integration) in the CCD image sensor array PA depends on the intensity of the light incident on it, and if the intensity of the incident light is low, the speed slows down and charge accumulation cannot be carried out for a long time. I have to let it happen. For this reason, the time required for one focus detection operation becomes longer, and the number of focus detection operations that can be performed within a certain period of time is restricted, making it impossible to bring the photographic lens into focus in a short time. on the other hand,
In the case of a CCD, there is no problem if the image sensor array PA is allowed to accumulate charges while the accumulated charges are being transferred from the shift register SR to the image signal output circuit VS. Therefore, the integral clear pulse can be generated immediately after the shift pulse is generated, which reduces the data processing time mentioned above.
Since the image sensor array PA performs new charge accumulation during Td, even when the incident light intensity is low,
The time required for one focus detection operation is shortened, the number of focus detection operations performed within a certain period of time is increased, and the photographic lens can be brought into focus in a short time. However, on the other hand, the accumulated charge of the CCD shift register SR is
While being transferred to the CCD, new accumulated charge is transferred to the CCD.
When transferred to shift register SR (this is CCD
), CCD shift register SR
The old and new accumulated charges are mixed together, and an erroneous image signal is output. Also, microcomputer 3
0 as well, new signals cannot be accepted because the data in the random access memory must be held during the calculation in step #15. Therefore, the above data processing time Td
This means that shift pulses are prohibited during this period. FIGS. 10A and 10B illustrate how the focus detection operation is repeated in the above embodiment; FIG. 10A shows Ti<Td, and B shows Ti>
This is the case for Td. In Figure A, the dotted line indicates the charge accumulation period after the integral clear pulse generated at step #10 disappears; however, as mentioned above, the charge accumulated during this period is accumulated by the integral clear pulse generated at step #17. Cleared by . On the other hand, in Figures 11A and B, as assumed earlier,
Figure A shows the case where the photodiodes of the image sensor array (PA) always start accumulating charge after data processing is completed, and Ti<Td.
In this case, Figure B shows the case where Ti>Td. 11th
Comparing FIG. B with FIG. 10B, it can be seen that the number of focus detection operations within a certain period of time is clearly increased in the case of the above embodiment. Although the present invention has been described above with reference to one embodiment, the present invention is not limited to the above embodiment. For example, self-scanning image sensors include not only CCDs but also BBDs (Bucket Brigades).
Device), CID (Charge Injection Device),
A MOS (Metal Oxide Semiconductor) type image sensor or the like can be used. Furthermore, the focus detection method is not limited to the one using the focus detection optical system shown in FIG. As shown in et al., by arranging a lenslet on the intended focal plane of the photographic lens or a plane conjugate thereto, and arranging a self-scanning image sensor behind it, the amount of defocus can be adjusted as the focus adjustment state of the photographic lens. A method of calculating both the and the defocus direction, or JP-A-55-155308, JP-A-57-72110, JP-A-57-88418.
As shown in the publication, self-scanning image sensors are placed on the intended focal plane of the photographic lens or on a plane conjugate thereto, and in front and behind it, respectively, and detect only the defocus direction as the focus adjustment state of the photographic lens. The present invention is also applicable to other systems. Effects As explained above, in the image processing device of the present invention, charge transfer from the transfer section of the image sensor to the image signal output circuit is started by generating an integral clear pulse in response to a shift pulse. Since the image sensor's charge storage unit is made to accumulate new charges while image signal processing calculations are being performed, if the charge accumulation time is longer than the data processing time, the image will be The time required for an image processing operation until the end of signal processing is now determined only by the charge accumulation time, and compared to the case where the sum of the charge accumulation time and data processing time is one cycle of one image processing operation, The number of image processing operations within the camera increases, and for example, the photographic lens can be brought into focus more quickly. Furthermore, even if the charge accumulation time is longer than the data processing time, the generation of the next shift pulse is prohibited, so new charge accumulation within the image sensor will occur until the image signal processing operation is completed. There is no fear that the charge accumulated in the transfer section will be transferred to the transfer section and that the new and old accumulated charges will be mixed in the transfer section, thereby forming a meaningless image signal. Note that if the charge accumulation time is shorter than the data processing time, a new integral clear pulse is generated when the processing operation is completed to wipe out the charge accumulated in the charge accumulation section until then, and the integral clear pulse disappears. The structure is configured so that charge accumulation is started again by the 1st shift pulse, and the generation of the next shift pulse is allowed following the generation of the new integral clear pulse, so that the image sensor is Even if the charge accumulation in the charge storage section is once saturated, a reliable image signal can be obtained regardless of the saturation.

[Brief explanation of drawings]

FIG. 1 is an overall circuit diagram of an embodiment of the present invention, FIG. 2 is a diagram showing details of the photoelectric conversion block 1 in FIG. 1, and FIG. An equivalent circuit diagram of the clear gate, FIG. 4 is a diagram showing the focus detection optical system in the above embodiment, FIG. 5 is a diagram showing temporal changes in the output of the monitor circuit, and FIG. 6 is a diagram showing the brightness determination of FIG. 1. A circuit diagram showing a specific example of the circuit 40 and block 20, FIGS. 7 and 8 are diagrams showing output waveforms at each part of the circuit in FIG. 1, and FIG. 9 is a flowchart showing the operation of the microcomputer in the above embodiment. Figures 10A and 10B are time charts showing how the focus detection operation is repeated in the above embodiment. Figure 11 is a time chart showing how the focus detection operation is repeated in the above embodiment. Figure 11 shows charge accumulation in each photodiode constituting the image sensor array of the image sensor after data processing. 3 is a time chart showing how the focus detection operation is repeated when starting . PA, ICG, SG, SR...Self-scanning image sensor, PA...Charge storage unit, SR...Charge output unit, VS...Image signal output circuit, MP...Monitor light receiving means, MC...Monitor circuit ,30,T
17... Integral clear pulse generation means, 40... Brightness determination circuit, DF2,10... Output signal generation means,
30, T19...shift pulse generation prohibition means and shift pulse generation permission means, 30...integral clear pulse generation control means.

Claims (1)

[Claims] 1. An image signal is obtained by the image signal output circuit based on the accumulated charge output from a self-scanning image sensor having a charge accumulation section and a charge output section that outputs the accumulated charge to the image signal output circuit by an output signal, and the processing circuit In an image processing device that processes and calculates an image signal by means of an integral clear pulse generating means for generating an integral clear pulse for wiping out accumulated charge in the charge storage section, and a means for generating an integral clear pulse that changes the intensity of light incident on the image sensor after the integral clear pulse disappears, a termination signal output circuit that outputs a termination signal for terminating the charge accumulation operation when the amount of charge accumulated in the charge accumulation section reaches a predetermined value; output signal generation means for generating the output signal for outputting the electric charge to the image signal output circuit; and output signal generation inhibiting means for prohibiting the output signal generation means from generating the next output signal immediately after generation of the output signal. an integral clear pulse generation control means for causing the integral clear pulse generating means to generate the next integral clear pulse in response to the generation of the output signal; If it is not output, the generation of the next output signal is disabled after the calculation process is completed, and if the above end signal is output, the integral clear pulse is generated again at the end of the process calculation, and then the next output signal is generated. An image processing apparatus comprising: an output signal control means for disabling the generation of an output signal.