JPH0762734B2 - Focus detection device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a focus detection device, and more particularly to detecting the state of a light image based on an image sensor output obtained by forming a light image on a light receiving portion of the image sensor. Device, for example, a focus detection device suitable for use in an optical device such as a camera.

In a conventional focus detection device of this type, for example, a focus detection device used in a camera, photoelectrically detects a relative shift amount of a pair of subject images due to a light beam that has passed through different portions of the exit pupil of the projection lens. The focus of the projection lens is detected from the shift amount. FIG. 9 shows the optical system. In FIG. 9, each of the light fluxes passing through the first portion 2 and the second portion 3 of the exit pupil of the taking lens 1 is represented by the taking lens 1
The first and second subject images are formed in the vicinity of the planned image forming surface 4. Each of the first and second subject images is passed through the field lens 5 and the first and second re-imaging lenses 6 and 7 for the first and second photoelectric conversion element arrays (hereinafter referred to as image sensor SA, It is re-imaged on SB.
The image sensors SA and SB each include N photoelectric conversion units a1 to
It is formed of aN and b1 to bN, and the width of the photoelectric conversion units in the arrangement direction is almost the same as the arrangement pitch PO of the photoelectric conversion units.
The image sensors SA and SB output time-series analog outputs SA1 to SAN and SB1 to SBN corresponding to the light intensity distribution on the photoelectric conversion unit.

FIG. 10 shows the image sensors SA and S thus obtained.
SAN of SB and SB1 ... SBN, and a conventional example of an arithmetic processing system of a focus detection device for detecting the relative shift amount of the first and second object images on the image sensors SA and SB. Show. The operation of such a conventional focus detection device will be described with reference to FIGS. 10 and 11.

The image sensors SA and SB accumulate charges at time TO from time t0 to time t1, and photoelectric conversion outputs SA1 ... S from time t1.
The AN, SB1 ... SBN are sequentially sent to the A / D converter 8 in time series. A / D
The converter 8 A / D-converts these time-series outputs and outputs them at time t1.
To photoelectric conversion outputs SA1 ... SAN, SB1 ... SBN corresponding digital data E1 ... EN, F1 ... FN to the microprocessor 9 (hereinafter
Call it CPU). The microprocessor 9 has a data transfer means 11, a filter means 12, and a focus detection calculation means 13, and each of these means is driven according to programming prestored in the CPU. That is, from time t1, A /
The output digital data E1 ... EN, F1 ... FN of the D converter 8 are sequentially stored in a predetermined storage area of the memory 10 by the data transfer means 11. In this way, digital data transfer is performed by the data transfer means 11 at time T1 from time t1 to time t2, and at time t2 all digital data E1 to EN, F1 to
When the FN is stored in the memory 10, the filtering means 12 starts filtering the digital data E1 to EN and F1 to FN.

Here, the filtering means, for example, the addition digital data GL (G1 to G2 where P = N−Q +
Refers to 1).

Here, the digital data GL is obtained by sequentially changing L, and in the equation (1), K = S−L +
1, Q is the number of filtering terms, and WK is the weighting factor of the filter. L = 1, Q = 5, weighting factor wk is shown in FIG. 12 (a).
When set as above, the equation (1) becomes the following equation (2).

G1 = W1 ・ E1 ＋ W2 ・ E2 ＋ W3 ・ E3 ＋ W4 ・ E4 ＋ W5 ・ E5 = 0.28 ・ E1 ＋ 0.76 ・ E2 ＋ 1.0 ・ E2 ＋ 0.76 ・ E4 ＋ 0.28 ・ E5… (2) Fig. 12 (b) shows the number 12 It shows the MTF of the filter means having a weighting coefficient as shown in FIG. In this way, by appropriately setting the value of the weighting factor wk of the filter means 12 and the number of terms Q, the high frequency that adversely affects the focus detection calculation from the digital data E1 to EN, F1 to FN corresponding to the intensity distribution of the optical image. It is possible to remove components and low frequency components.

Referring to FIG. 11, at time T2 from time t2 to time t3, digital data E1 to EN, F1 to F1
The addition digital data G1 to GP and H1 to HP corresponding to FN are calculated and stored in the memory. Next, at time T3 from time t3 to time t4, the focus detection calculation 13 performs calculation to obtain the relative shift amount between the added digital data G1 to GP and H1 to HP. At time t4, the focus detection calculation means 13 detects the shift amount, and based on that, the focus adjustment state is displayed and / or the photographing lens is driven, and the series of sequences is completed. Then, at time t4, charge accumulation of the next image sensor is started and the next sequence starts.

In such a conventional focus detection device, since the operation of the filter means is performed after the transfer operation of the A / D converted digital data to the memory is completed, when the data amount becomes large, these The total time of the above operations becomes long, and the responsiveness of the focus detection apparatus as a whole deteriorates. It is conceivable to use a high-speed A / D conversion means in order to shorten the data transfer operation time, but it not only increases power consumption but is expensive.

(Object of the Invention) An object of the present invention is to solve these drawbacks and to provide a focus detection apparatus which performs data transfer and filtering in parallel with AD conversion.

(Summary of the Invention) The present invention converts one analog data into digital data
It is characterized in that the digital data is transferred to the memory and the other digital data already stored in the memory is read out during the time of D conversion, and the calculation related to the focus detection is performed.

(Examples) -First Example-FIG. 1 shows an example of the present invention, in which outputs of a pair of image sensors (for example, CCD image sensors) SA and SB are A.
It is connected to the / D converter 14, and the output of the A / D converter 14 is connected to the microprocessor 15. The microprocessor 15 is a well-known one, and the focus information calculation program shown in FIGS. 2 and 3 is stored in advance in its ROM. By the program, the image sensor S in the A / D converter 14
Digital data E1, E2 ... EN from A and data F1, F2 ... FN from the image sensor are sequentially transferred, filtered, and arithmetically processed to add digital data G1 to GP, H1.
~ HP is configured to be calculated. Therefore, the microprocessor 15 has the data transfer means 17 and the filter means.
18 and a calculation means 19.

The processing procedure of the focus information calculation program shown in FIGS. 2 and 3 will be described below.

Data obtained by the processing of the programs of FIGS. 2 and 3 are stored in the memory as shown in the memory map of FIG. First, an outline of the flow until the data is stored in the memory will be described. In the memory map of FIG. 4, digital data E1 to AD converted based on the image sensor SA
When EN is stored in the addresses Ad10 to AdN0, and after the storage is completed, the digital data F1 to FN converted to AD based on the image sensor SB is stored in the addresses Ad11 to AdN1 and when the data E1 to EN are filtered. The added digital data G1 to GP are stored in the addresses Ad12 to AdP2, and after the storage is completed, the added digital data H1 to HP when the data F1 to FN are filtered are stored in the addresses Ad13 to AdP3. ing. At this time, when the data transfer program of FIG. 3 stores the minimum number of data required for the filter operation in the addresses Ad10 to AdN0, the filter program of FIG. 2 operates to multiply the data by a weighting coefficient. Start filter calculation. As described above, the filter calculation and the data transfer program are operated alternately, and the data (added digital data) as the result of this filter calculation is stored in addresses Ad12 to AdP2 and addresses Ad13 to AdP3.
Are stored in order. When all the data are arithmetically processed and stored in the memory, focus detection calculation is performed next, the data from the image sensor is again stored in the memory, and the above-described operation is repeated to bring the image into a focused state. In the following description,
The number of weighting factors in the filter calculation is 3, and W1 = C1, W2 = C2 and W3 = C3, respectively. Further, the A / D converter 14 is assumed to generate an interrupt signal to the CPU 15 when the A / D conversion is completed.

When the program shown in FIG. 2 is started at a predetermined timing, in step S1, before valid digital data E1 to EN and F1 to FN are sent from the A / D converter 14,
Generates an interrupt disable signal to disable interrupts. As a result, the interrupt from the A / D converter 14 is not accepted. In the next step S2, the address A1 is changed to Ad10, that is, the digital data E1 to EN.
The address AY is set to Ad12, that is, the storage start address of the addition digital data G1 to GP, and the address A2 is set to Ad10, that is, the storage start address of the digital data E1 to EN. Then proceed to step S3, A / D
An interrupt enable signal is generated to allow the interrupt from the converter 14. An interrupt enable signal is generated immediately before the first valid digital data E1 is output from the A / D converter 14 to permit interrupt acceptance.

In step S4, it is determined whether the address A1 is greater than or equal to the address A2 + 3. This is to check whether the number of digital data stored in the memory has reached the number necessary for performing the filter operation. At this point of time, A1 = Ad10 <A2 + 3 = Ad10 + 3, the negative decision is made in step S4, and this step is repeated again to wait for the interrupt from the A / D converter 14.

When the A / D converter 14 outputs the first effective digital data E1 and sends an interrupt signal to the CPU 15, the program shown in FIG. 2 is interrupted and the digital data transfer program shown in FIG. 3 is started. In step S21, A / D
Read the output digital data E1 from the converter 14 and
Store in the internal register of U15. Next, in step S22, the read data E1 in the register is transferred to and stored in address A1 of the memory, that is, Ad10, and then step S2.
Go to 3. In step S23, the address A1 is the address AdN1
It is determined whether or not At this point A1 = Ad10 ≠ Ad
Since it is N1, this step S23 is negatively determined and step S
In step 24, it is determined whether the address A1 reaches the address AdN0. At this point in time, A1 = Ad10 ≠ AdN0, so that a negative decision is made in step S24, and the routine proceeds to step S25. In step S25, 1 is added to the address A1 to set A1 = A1 + 1 = Ad20. When step S25 ends, the program returns to the predetermined step of the program shown in FIG. 2, that is, the step to which the interrupt is applied last. In this case, step S4
Return to. The address at the time of the second determination in step S4 is A1 = Ad20 = Ad10 + 1 <A2 + 3 = Ad10 + 3.
Therefore, a negative decision is made in step S4, and the same step S4 is repeated again, waiting for the next interrupt signal from the A / D converter 14.

When the A / D converter 14 outputs the next digital data E2 and interrupts the CPU 15, the CPU 15 executes the data transfer program again and stores the digital data E2 in the address Ad20 as described above, and then the original step. In S4, it is again determined whether the address is A1 or A2 + 3 or more. The address in this case is A1 = Ad30 = Ad10 + 2 <A2 + 3 = Ad10 + 3
Therefore, a negative determination is made in step S4, and A / D
It waits for the reception of the interrupt signal from the converter 14.

By repeating such operation, the digital data is stored in the memory 16.
When E3 is stored and the process returns to step S4 in the program of FIG. 2, the address A1 = Ad40 = Ad10 + 3 = A2 + 3 =
Since it is Ad10 + 3, an affirmative decision is made and step S5.
Proceed to. In step S5, addition digital data FY = 0 is set, and the flow advances to step S6. In step S6, the address
The digital data E1 of A2 = Ad10 is read, multiplied by the weighting coefficient C1, and the multiplication result is added to the data FY. That is, the result of C1 · E1 is stored in the internal register as the data FY. Next, in step S7, 1 is added to the address A2, A2 = A2 + 1 = Ad10 + 1 = Ad20 is set, and the process proceeds to step S8. The digital data E2 of the address A2 = Ad20 is read and multiplied by the weighting coefficient C2, and the multiplication result is the data FY. Add to.
That is, the result of C1, E1 + C2, E2 is stored in the internal register as data FY. Next, in step S9, add 1 to A2 and set A2 = A2 + 1 = Ad20 + 1 = Ad30
Proceeding to S10, the digital data E3 of the address A2 = Ad30 is read, multiplied by the weighting coefficient C3, and the multiplication result is added to the data FY. That is, as data FY, C1 ・ E1 ＋ C2 ・ E2 ＋ C3
-The result of E3 is stored in the internal register. The data FY at this time becomes the addition digital data G1 as the first signal. Therefore, the addition digital data G1 temporarily stored in the internal register as the data FY in step S11 is stored in the address AY = Ad12 of the memory 16.

In the next step S12, the address A2 is the digital data F1.
~ Determine whether or not the storage end address AdN1 of FN has been reached. At this point in time, the address A2 is A2 = Ad30 ≠ AdN1, so that a negative decision is made in step S12 and the operation proceeds to step S13.
In step S13, the address A2 is the digital data E1 to EN.
Storage end address AdN0 is determined,
At this time point, the address A2 is A2 = Ad30 ≠ AdN0, so a negative determination is made and the process proceeds to S14. In the step S14, 1 is subtracted from the address A2 to set A2 = A2-1 = Ad30-1 = Ad20, and 1 is added to the address AY, AY = AY + 1 = Ad12 +
1 = Ad22 and the process returns to step S4 again. By the above procedure, the added digital data G1 to GP are obtained and stored in the memory 16.

As a result, the digital data E1 to EN output from the AD converter 14
Are sequentially stored in the memory 16. Here, when the digital data EN corresponding to the last photoelectric conversion output from the image sensor SA is transferred, the address A1 = AdN0 is set, so that the affirmative decision is made in step S24 and step S24 is made.
Going to 26, the address A1 is set to the storage start address Ad11 of the digital data F1 to FN, so that the digital data F1 to FN from the image sensor SB AD-converted thereafter are sequentially stored at the addresses Ad11 and thereafter. Become. Further, at the stage where the addition digital data GP is obtained by the filter calculation, the address A2 = AdN0, so that the affirmative decision is made in step S13 of FIG. Since it is set to the start address Ad11 and the address AY is also set to the storage start address Ad13 of the added digital data H1 to HP, the subsequent filter operation is performed on the digital data F1 to FN and the obtained second data is obtained. Digital data as a signal of
H1 to HP will be stored at address Ad13 and later.

Further, since the address A1 = AdN1 is set when the digital data FN is transferred, an affirmative decision is made in step S23 of FIG. 3 and the operation proceeds to step S27 so that no interrupt from the AD converter 14 is accepted thereafter. An interrupt disable signal is generated at. Therefore, after that,
The CPU 15 repeats only the filtering operation without performing the data transfer operation. Then, when the added digital data HP is obtained by the filter calculation, the address A2 = AdN1 is set. Therefore, an affirmative decision is made in step S12 of FIG. 2, and a series of data transfer and filter calculation is completed, and the next focus detection calculation is performed. To proceed.

The time sequence of various processes by the program described above will be described below with reference to FIG.

At time t0, charge accumulation of the pair of image sensors SA and SB is started, charges are accumulated in all photoelectric conversion units during time T0 until time t1, and charge accumulation ends at time t1. Subsequently, at time t1, the photoelectric conversion output SA1 is sent from the image sensor SA to the A / D converter 14, and from time t1 to time t2.
The photoelectric conversion output SA1 is A / D converted at time T1. At time t2, digital data E1 as A / D conversion value is sent to the CPU
Output to 15. In the CPU 15, the data transfer means 17 causes the digital data E to be transferred between time t2 and time t20.
Transfer 1 to memory 16.

On the other hand, at time t2, since the next photoelectric conversion output SA2 is sent from the image sensor SA to the A / D converter 14, time t2
From time t3 to time t3, the output SA2 is A / D converted and is output to the CPU 15 as digital data E2 at time t3. Then, the CPU 15 performs the filtering process on the digital data stored in the memory 16 by the filter means 18 during the period from the time t20 to the time t3. At this point, since only the digital data E1 is stored in the memory 16, no substantial filtering process is performed. In this way, the photoelectric conversion output from the image sensor SA is sequentially
SA1, SA2 ... are sent to the A / D converter 14 and digital data E1, E
2 ... and the data E1, E2 ...
Is stored in the memory 16 by. Then, when the number of stored digital data is stored at least as much as necessary to perform the filter operation as in the equation (1), the filter means
18 stores the added digital data G1, G2 ... In the memory 16 by performing a filter operation as shown in the equation (1) at a time excluding the time used for the data transfer operation in the AD conversion operation time.

When these processes for the photoelectric conversion outputs SA1 to SAN from the image sensor SA are completed, next, similar processes are sequentially performed to the photoelectric conversion outputs SB1 to SBN from the image sensor SB to perform A / D conversion. Analog data SB1 to SB
N is converted into digital data F1 to FN and data transfer means 17
Is stored in the memory 16 by. The filter means 18 is
In the same manner as described above, the filter operation is performed on the digital data F1 to FN at the time excluding the data transfer time in the A / D conversion operation time to calculate the added digital data H1 to HP and store it in the memory 16. Store it. When the data transfer of the final digital data FN is completed at time t510, the filter means 18 performs the filter operation at time T51 from time t510 to time t52, and completes the filter operation at time t52. At this point, the added digital data G1 to GP and H1 to HP are stored in the memory 16.
The calculating means 19 performs a calculation for obtaining the relative deviation amount of the added digital data G1 to GP and H1 to HP at the time T52 from the time t52 to the time t53. At time t53, a signal indicating the focus adjustment state is generated based on the calculated shift amount, the display and / or the photographic lens is driven, and a series of focus detection operations ends. Then, at time t53, charge accumulation of the next image sensor is started, and thereafter, a series of operations for focus detection are similarly started.

-Second Embodiment- Next, a second embodiment of the present invention will be described. In the first embodiment, the number of data swept from the image sensors SA and SB in one scan, that is, 2N times CP
U is being interrupted. Usually the CPU
When the interrupt from the A / D converter 14 is accepted, processing such as saving the contents of the register currently used in the stack is performed. Therefore, when the number of interrupts increases, the time required for it increases proportionally. The second embodiment is an improvement of the first embodiment with respect to such a problem. As shown in FIG. 6, a CPU 22 is provided with a buffer memory 21 between the A / D converter 20 and the CPU 22. It reduces the number of interrupts to. Therefore, in the ROM of the CPU 22 in this example, the data transfer program shown in FIG. 7 as the data transfer means 24 is stored in place of the data transfer program of FIG. Since the operation of the filter means 25 and the memory map of the memory 23 of the second embodiment are similar to those of FIGS. 2 and 4, only the operation of the data transfer means 24 will be described here.

In response to the time when the first M digital data E1 to EM are all stored in the M registers 1 to M of the buffer memory 21, the buffer memory 21 sends an interrupt signal to the CPU 22 to generate an interrupt. Call. The CPU shifts the data transfer operation by the data transfer means 24. That is, the program shown in FIG. 7 is activated in response to the interrupt signal. In step S31, the digital data E1 stored in the register 1 of the buffer memory 21 is transferred to the internal register in the CPU 22. Next, in step S32, the address A1 in the memory 23, that is, the address Ad
The digital data E1 is transferred to 10 and stored. Step S3
In 3, the address A1 is incremented by 1, A1 = A1 = Ad20 is set, and the process proceeds to step S34 to read the digital data E2 from the register 2 of the buffer memory 21 and temporarily store it in the internal register of the CPU 22. Then, in step S35,
The data is transferred to the address A1 = Ad20 of the memory 23 and stored. Then, in step S36, 1 is added to the address A1 to set A1 = A1 + 1 = Ad30. This operation is repeated, and finally, in steps S36 and S37, the address
By transferring and storing the digital data EM stored in the register M of the buffer memory 21 to A1 = AdM0, all the data temporarily stored in the buffer memory 21 is transferred to and stored in the memory 23. Next, in step S39, it is determined whether the address A1 reaches the storage end address AdN1 of the digital data F1 to FN. At this time point, the address A1 = AdM0 ≠ AdN1, so a negative determination is made, and the process proceeds to step S40 to determine whether or not the address A1 reaches the storage end address AdN0 of the digital data E1 to EN.
At this point, the address A1 = AdM0 ≠ AdN0, so a negative determination is made, and the process advances to step S41 to add 1 to the address A1 and A1 = A.
Set to 1 + 1. Such an operation is repeated, and every time M pieces of A / D converted digital data are accumulated in the buffer memory 21, the CPU 22 is interrupted and M pieces of digital data are transferred and stored in the memory 23 at a time. When all the digital data E1 to EN are stored in the memory 23, an affirmative decision is made in step S40 and the operation proceeds to step S42 where the address A1 is set to the storage start address Ad11 of the digital data F1 to FN. Thereafter, the digital data F1 to FN are stored in the memory 23 in the same manner as the above-mentioned transfer operation. When all the digital data F1 to FN are finally stored in the memory means 23, an affirmative decision is made in step S39, and in step S43, an interrupt disable signal is generated, and interrupt acceptance from the buffer memory 21 is prohibited,
The data transfer operation by the data transfer means 24 ends.

The time sequence of various processes according to the second embodiment will be briefly described below with reference to FIG. A / D converter for photoelectric conversion outputs SA1 to SAN and SB1 to SBN of image sensors SA and SB
Are sequentially sent to the buffer memory 21 to be converted into digital data E1 to EN and F1 to FN. The buffer memory 21 is composed of M registers, for example, nine registers 1 to 9, and the digital data sent from the A / D converter 20 is sequentially stored in the registers 1 to 9 sequentially. . Then, in response to the digital data being stored in all nine registers at time t11, the buffer memory 21 interrupts the CPU 22. As a result, the CPU 22 transfers the nine pieces of digital data stored in the registers 1 to 9 of the buffer memory 21 to the memory 23 by the data transfer means 24 and stores them. The buffer memory 21 includes registers 1 to 9
When the digital data stored in is transferred and swept out sequentially, the digital data sent from the A / D converter 20 is stored again. In the CPU 22, after the data in the buffer memory 21 is transferred to the memory 23, the filter processing is performed by the filter means 25 until the next interrupt signal is generated, that is, until the data is stored in all the registers. To be executed. In this way, from the time t53 when the digital data E1 to EN, F1 to FN and the added digital data G1 to GP, H1 to HP are finally stored in the memory 23, the CPU 22 operates in the same manner as in the first embodiment. The focus detection calculation is performed by 26, the relative shift amount of the digital data G1 to GP, H1 to HP is obtained, and the focus adjustment state is displayed and / or the lens is driven based on the shift amount.

As described above, in the second embodiment, the number of interrupts applied to the CPU can be reduced to about 1 / M of that in the first embodiment. Here, the number M of registers of the buffer memory 21 is determined as an optimum value in consideration of the calculation speed of the CPU 22, the time required for data transfer, the A / D conversion speed, and the like.

(Effect of the Invention) According to the present invention as described above, data transfer and filter processing are performed in parallel with AD conversion, so that the calculation time for focusing as a whole can be shortened. Therefore, the same effect as using a high-speed A / D converter can be obtained at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the focus detection apparatus of the present invention, FIGS. 2 and 3 are flow charts showing an example of a program for focus calculation stored in the microprocessor, and FIG. 4 is a memory. 5 is a memory map showing an example of the address of FIG. 5, FIG. 5 is a time sequence diagram of various arithmetic processing by the programs shown in FIGS. 2 and 3, and FIG. 6 is a block diagram of a second embodiment of the focus detection apparatus of the present invention. ,
FIG. 7 is a flow chart showing an example of the data transfer program, FIG. 8 is a time sequence diagram of various arithmetic processing by the program shown in FIG. 7, FIG. 9 is a diagram showing an optical system of the focus detection device, and FIG. FIG. 11 is a block diagram of a conventional focus detection device, FIG. 11 is a time sequence diagram in the conventional focus detection device, and FIG. 12 is a diagram showing an example of weighting factors and MTF of the filter means. SA, SB: Image sensor 9,15,22: CPU 11,17,24: Data transfer means 13,19,26: Arithmetic means 8,14,20: A / D converter 10,16,23: Memory 12, 18,25: Filter means 21: Buffer memory means

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kunihisa Hoshino 1-6-3 Nishioi, Shinagawa-ku, Tokyo Inside Oi Manufacturing Co., Ltd. of Japan Optical Industry Co., Ltd. (56) Reference JP-A-60-125817 (JP, A)

Claims (3)

[Claims] 1. A photoelectric conversion element array in which a large number of charge storage type photoelectric conversion elements are arranged, and the charges accumulated in each photoelectric conversion element are sequentially output as analog data to the outside in time series, and the photoelectric conversion element. A focus detection optical system that forms an optical image of an object on the element, and an analog that sequentially converts analog data output from the photoelectric conversion element array in time series into digital data.
Digital conversion means, memory means for storing the digital data converted by the analog-to-digital conversion means, transfer means for transferring the digital data to the memory means, and predetermined arithmetic processing for the digital data A focus detection device including a focus detection calculation unit that generates a signal indicating a focus state based on the predetermined calculation process, while the analog-to-digital conversion unit sequentially converts the analog data into digital data. 1. A focus detecting apparatus, further comprising control means for controlling the focus detecting arithmetic means to sequentially perform the predetermined arithmetic processing from digital data already stored in the memory means. 2. The control means causes the focus detection calculation means to perform the predetermined calculation within a time from when the transfer means finishes transferring one digital data to when it starts transferring the next digital data. The focus detection apparatus according to item (1), characterized in that processing is performed. 3. The focus detection device according to claim 1, wherein the predetermined calculation is a calculation process for removing a constant frequency component.